SiT3808数据手册-晶圆电子SiTime硅晶振一级代理商

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Supply Voltage and Current Consumption
VCXO Characteristics ±25, ±50, ±100, ±150, ±200, ±400, ±800, ±1600 1.7 2.4 2.7 3.2 Lower Control Voltage Control Voltage Input Impedance Control Voltage Input Capacitance Linearity Frequency Change Polarity Control Voltage Bandwidth (-3dB) VC_L Z_in C_in Lin – V_BW – – 100 – – – – – – – – 5 0.1 Positive slope 8 – – – – 0.1 – – 1
1 MHz to 80 MHz High Performance MEMS VCXO
The Smart Timing Choice The Smart Timing Choice
SiT3808
Features

Applications

Any frequency between 1 MHz and 80 MHz with 6 decimal places of accuracy 100% pin-to-pin drop-in replacement to quartz-based VCXO Frequency stability as tight as ±10 ppm Widest pull range options from ±25 ppm to ±1600 ppm Industrial or extended commercial temperature range Superior pull range linearity of ≤1%, 10 times better than quartz LVCMOS/LVTTL compatible output Four industry-standard packages: 2.5 mm x 2.0 mm (4-pin), 3.2 mm x 2.5mm (4-pin), 5.0 mm x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin) Instant samples with Time Machine II and field programmable oscillators RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free


Electrical Specifications
Parameter Output Frequency Range Frequency Stability
ristics[1, 2, 3]
Symbol f F_stab Min. 1 -10 -25 -50 Aging Operating Temperature Range F_aging T_use -5 -20 -40 Supply Voltage Vdd 1.71 2.25 2.52 2.97 Current Consumption Standby Current Idd I_std – – – – Pull Range[5, 6] Upper Control Voltage PR VC_U Typ. – – – – – – – 1.8 2.5 2.8 3.3 31 29 – – Max. 80 +10 +25 +50 +5 +70 +85 1.89 2.75 3.08 3.63 33 31 70 10 Unit MHz ppm ppm ppm ppm °C °C V V V V mA mA A A ppm V V V V V kΩ pF % – – kHz Contact SiTime for 16 kHz and other high bandwidth options No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V No load condition, f = 20 MHz, Vdd = 1.8V Vdd = 2.5V, 2.8V, 3.3V, ST = GND, output is Weakly Pulled Down Vdd = 1.8V, ST = GND, output is Weakly Pulled Down See the Absolute Pull Range and APR table on page 10 Vdd = 1.8V, Voltage at which maximum deviation is guaranteed. Vdd = 2.5V, Voltage at which maximum deviation is guaranteed. Vdd = 2.8V, Voltage at which maximum deviation is guaranteed. Vdd = 3.3V, Voltage at which maximum deviation is guaranteed. Voltage at which minimum deviation is guaranteed. 10 years, 25°C Extended Commercial Industrial Additional supply voltages between 2.5V and 3.3V can be supported. Contact SiTime for additional information. Inclusive of Initial tolerance[4] at 25 °C, and variation over temperature, rated supply voltage and load. Condition Frequency Range Frequency Stability and Aging
Startup and Resume Timing
Notes: 1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated. 2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at 25°C temperature. 3. All max and min specifications are guaranteed across rated voltage variations and operating temperature ranges, unless specified otherwise 4. Initial tolerance is measured at Vin = Vdd/2 5. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage. 6. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
Output Low Voltage
VOL


10%
Vdd
Input Characteristics Input Pull-up Impedance Input Capacitance Startup Time OE Enable/Disable Time Resume Time RMS Period Jitter RMS Phase Jitter (random) Z_in C_in T_start T_oe T_resume T_jitt T_phj – – – – – – – – 100 5 – – 7 1.5 2 0.5 250 – 10 180 10 Jitter 2 3 1 ps ps ps kΩ pF ms ns ms
Telecom clock synchronization, instrumentation Low bandwidth analog PLL, jitter cleaner, clock recovery, audio Video, 3G/HD-SDI, FPGA, broadband and networking
SiT3808
Electrical Specifications (continued) Table 1. Electrical Characteristics[1, 2, 3]
Parameter Duty Cycle Rise/Fall Time Output High Voltage Symbol DC Tr, Tf VOH Min. 45 – 90% Typ. – 1.5 – Max. 55 2 – Unit % ns Vdd Condition All Vdds. Refer to Note 11 for definition of Duty Cycle Vdd = 1.8V, 2.5v, 2.8V or 3.3V, 10% - 90% Vdd level IOH = -7 mA (Vdd = 3.0V or 3.3V) IOH = -4 mA (Vdd = 2.8V or 2.5V) IOH = -2 mA (Vdd = 1.8V) IOL = 7 mA (Vdd = 3.0V or 3.3V) IOL = 4 mA (Vdd = 2.8V or 2.5V) IOL = 2 mA (Vdd = 1.8V) For the OE/ST pin for 6-pin devices For the OE/ST pin for 6-pin devices See Figure 7 for startup resume timing diagram f = 40 MHz, all Vdds. For other freq, T_oe = 100 ns + 3 clock periods See Figure 8 for resume timing diagram f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V f = 20 MHz, Vdd = 1.8V f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz, All Vdds LVCMOS Output Characteristics