200度高温DSP芯片

TX5350
Vref Out 2.500V Temperature Sensor Voltage Reference 32K X 16 SRAM PWM D/A Converters(3) Analog Out (3)
+5 GND Analog In (8) Texas Instruments TMS320F240 A/D Converters Real Time Clock and Watch Dog Timer I/O 16K Flash Debugger and Serial Boot Loader ACTEL A42MX09 Serial I/O (2) Digital I/O (16)
TX5350
DSP Based Data Acquisition System with ADC’s, DAC’s, Digital I/O in a 40-pin Metal DIP Package for Extreme Environments / Applications
FEATURES
• • • • • • • • • • • Powerful 16-bit TI TMS320F240 DSP core 16K words of FLASH and 32K words of SRAM Internal PGA supports custom applications 8 10-Bit ADC Channels 3 10-Bit DAC Channels Internal 2.500 volt reference 16 programmable digital I/O’s High speed asynchronous serial port Internal temperature sensor Low power, single supply operation Operation to 200C°
EMU0 33
TDI 36
ADCIN8 29
ADCIN2 27
ADCIN1 26
ADCIN10 31
ADCIN0 25
VCC 40
VREF 24
JTAG (7)
Temperature Stable RC Clock
External Clk
Copyright 2007 Texas Components Corp
October 10, 2007
TX5350 Specifications @ 5V and 25C°
Operating Temperature Range -50C to +200C Analog Inputs 8 Available user inputs 2 For used Internal State of Health ( VCC, Substrate Temperature ) Resolution : 10 Bit Accuracy : ± 1 Lsb Conversion Time : 10 us Conversion Voltage Range : 2.500 Volts Lsb = 2.44 mV ( 2.500 / 1024 ) Reference Voltage : 2.500 V ± 0.05% Drift (-50C to +150C) : 5 ppm Drift (+150C to +200C) : 10 ppm Buffer Output Current : ± 5 mA Analog Outputs(3) 10 Bit PWM filtered outputs Output Range : 0.0 V to 2.500 V Output Ripple : 1.5 mV Output Impedence : 40 K ohms Settling Time to 0.1% : 13 ms Standard Package 40 pin Ceramic / Kovar dip Pins on 0.6” centers L = 2.1”, W = 0.85” Primary Components TI TMS320F240 DSP ACTEL A42MX09 PGA 32K x 16 SRAM Power Supply Input 4.75 to 5.25 Volts Power Consumption 40 ma typ --- ( Clock and Load dependent ) Internal RC Oscillator Frequency : 2.304 MHz ± 1% Stability : 100 ppm TMS320F240 CPU Clock PLL scaleable (X4) 2.304 MHz to 9.216 MHz External Clock Input 1 CMOS load Frequency Range : 1 to 20 MHz ( Internal clock is disabled upon detect ) Digital I/O 16 user configurable I/O ports 7 JTAG I/O Voltage Input - Any Input Max input range : -0.3 V to + 5.3 V Input capacitance : 10 pf Digital Outputs Output voltage : 0.2 to 4.8 V @ 10 mA load Floating point capacity > 30,000 operations / sec @ 9.216 MHz DSP Clock Serial Communication Up to 115200 baud TX5350 Pin out – Top View
TCK 37
DACOUT2 23
DACOUT1 22 19 DIGIO15
ADCIN11 32
ADCIN9 30
ADCIN3 28
TRST 39
TMS 38
TDO 35
EMU1 34
14 DIGIO10
15 DIGIO11

16 DIGIO12
17 DIGIO13
10 DIGIO6
11 DIGIO7
18 DIGIO14
PGA source code would be provided to Texas Components after debug on the SX5350 development system and devices using a new part number device would be manufactured. Additionally, the T5350 contains a full duplex, high-speed asynchronous serial interface which can be used for host-to-device communication. The resident DSP/PGA combination can be used to implement almost any communication protocol and provide local control independent of the host. Resident software includes a serial boot loader and debugger to facilitate loading of new executables into flash memory, allowing the entire personality of the TX5350 to be reconfigured without removing it from the circuit.
2 SEROUT
1 EXTCLK
12 DIGIO8
13 DIGIO9
4 DIGIO0
5 DIGIO1
6 DIGIO2
7 DIGIO3
8 DIGIO4
9 DIGIO5
3 SERIN
Copyright 2007 Texas Components Corp
October 10, 2007
20 GND
DACOUT0 21
DEVELOPMENT TOOLS
• • SX5350 board level TX5350 equivalent JTAG emulator
DESCRIPTION The TX5350 is a complete, low-power data acquisition system in a single package. Major internal components are a powerful 16-bit DSP with two 10-bit analog-to-digital converters each with an 8-channel single-ended multiplexer (only 8 channels are available in the 40 pin package), a stable, internal 2.500 volt reference, three 10-bit digital-to-analog converters, an internal temperature sensor and sixteen independent digital pins that can be user programmed to any I/O pin of the DSP. The TX5350 also contains an antifuse PGA that is programmed at the die level to implement the personality of the device. All DSP I/O is routed through this PGA to provide maximum flexibility for any application. For custom configurations,