L6393DTR;L6393D;中文规格书,Datasheet资料

August 2010Doc ID 14497 Rev 41/19L6393Half-bridge gate driverFeatures■High voltage rail up to 600 V■dV/dt immunity ± 50 V/nsec in full temperature range■Driver current capability: –290 mA source, –430 mA sink■Switching times 75/35 nsec rise/fall with 1 nF load■ 3.3 V, 5 V CMOS/TTL inputs comparators with hysteresis■Integrated bootstrap diode ■Uncommitted comparator ■Adjustable dead-time ■Compact and simplified layout ■Bill of material reduction ■Flexible, easy and fast designApplication■Motor driver for home appliances ■Factory automation ■Industrial drives and fans ■HID ballasts ■Power supply unitsDescriptionThe L6393 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT .The high side (floating) section is designed to stand a voltage rail up to 600 V.The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP .The IC embeds an uncommitted comparator available for protections against overcurrent, overtemperature, etc.Table 1.Device summaryOrder codes Package Packaging L6393N DIP-14T ube L6393D SO-14L6393DTRTape and reelContents L6393Contents1Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.3Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.1AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.2DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.1CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182/19Doc ID 14497 Rev 4L6393Block diagramDoc ID 14497 Rev 43/191 Block diagramPin connection L63934/19Doc ID 14497 Rev 42 Pin connectionTable 2.Pin descriptionPin N# Pin name Type Function1PHASEI Driver logic input (active high) 2 SD (1)1.The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. Thisallows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.I Shut down input (active low) 3 BRAKE I Driver logic input (active low) 4VCCPLower section supply voltage5 DT I Dead time setting 6CPOUTOComparator output (open drain)7 G ND P G round 8CP-IComparator negative input9 CP+ I Comparator positive input10 LV G(1) O Low side driver output 11 NC Not connected12OUTP High side (floating) common voltage 13 HV G(1) OHigh side driver output14 BOOT P Bootstrapped supply voltageL6393Truth tableDoc ID 14497 Rev 45/193 Truth tableNote:X: don’t careIn the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port andthe resulting signal is in phase with the high side output HVG and in opposition of phase with the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG output. If BRAKE is set to low level the low side output LVG is always ON and the high side output HVG is always OFF , whatever the PHASE signal. This kind of logic interface provides the possibility to control the power stages using the PHASE signal to select the current direction in the bridge and the BRAKE signal to perform current slow decay on the low sides.From the point of view of the logic operations the two signals PHASE and BRAKE arecompletely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see the Figure 1 on page 3).Note:The dead time between the turn OFF of one power switch and the turn ON of the other power switch is defined by the resistor connected between DT pin and the ground.Table 3.Truth tableInputs OutputsSD PHASE BRA K E LVG HVG L X X L L H L L H L H L H H L H H L H L H H H L HElectrical data L63936/19Doc ID 14497 Rev 44 Electrical data4.1Absolute maximum ratingsNote:ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model)4.2 Thermal dataTable 4.Absolute maximum ratingsSymbol ParameterValueUnitMin maxV CC Supply voltage -0.321V V OUT Output voltage V boot - 21 V boot + 0.3V V boot Bootstrap voltage-0.3620V V hvg High side gate output voltage V OUT - 0.3 V boot + 0.3 V V lvg Low side gate output voltage -0.3V CC + 0.3 V V cp+ Comparator positive input voltage -0.3V CC + 0.3 V V cp-Comparator negative input voltage -0.3V CC + 0.3V V iLogic input voltage-0.315V V od Open drain voltage -0.315V dV OUT /dt Allowed output slew rate50V/ns P tot Total power dissipation (T A = 25 °C) 800mW T J Junction temperature 150°C T STGStorage temperature-50150°C Table 5.Thermal dataSymbol Parameter SO-14 DIP-14 Unit R th(JA)Thermal resistance junction to ambient max.165100°C/WL6393Electrical dataDoc ID 14497 Rev 47/194.3 Recommended operating conditionsTable 6.Recommended operating conditionsSymbol Pin ParameterTest conditionMin Max Unit V CC 4Supply voltage 1020V V BO (1)1.V BO = V boot - V out14-12 Floating supply voltage 9.820V V out 12DC Output voltage - 9 (2)2.LVG off. V CC = 10 V. Logic is operational if V boot > 5 V, refer to AN2785 for more details.580V V CP-8Comparator negative inputvoltageV CP+≤ 2.5V V cc(3)3.At least one of the comparator's input must be lower than 2.5V to guarantee proper operation.V V CP+9Comparator positive input voltageV CP-≤ 2.5VV cc(3)V f sw Switching frequency HVG, LVG load C L = 1 nF800kHz T JJunction temperature-40125°C8/19Doc ID 14497 Rev 45 Electrical characteristics5.1 AC operationV CC = 15 V , T J = +25 °CTable 7.AC operation electrical characteristicsSymbol Pin ParameterTest conditionMin Typ Max UnitAC operationt on 1,3vs 10, 13High/low side driver turn-on propagation delay V out = 0 V V boot = V cc C L = 1 nFV i = 0 to 3.3 Vsee Figure 3 on page 950 125 200 ns t off High/low side driver turnoff propagation delay50 125 200 nst sd 2 vs10,13Shut down to high/low side propagation delay 50 125 200 nsMTDelay matching, HS and LS turn-on/off30 nsDT 5Dead time setting range (1)R DT = 0, C L = 1 nF0.1 0.18 0.25μsR DT = 37 k Ω, C L = 1 nF , C DT = 100 nF 0.48 0.6 0.72 R DT = 136 k Ω, C L = 1 nF , C DT = 100 nF 1.35 1.6 1.85 R DT = 260 k Ω, C L = 1 nF , C DT = 100 nF 2.63.03.4 MDT Matching dead time(2)R DT = 0 Ω; C L = 1 nF80 nsR DT = 37 k Ω; C L = 1 nF; C DT = 100 nF 120 R DT = 136 k Ω; C L = 1 nF; C DT = 100 nF 250 R DT = 260 k Ω; C L = 1 nF; C DT = 100 nF400 t r 10, 13 Rise timeC L = 1 nF 75 120 ns t fFall timeC L = 1 nF3570ns1.See Figure 4 on page 92.MDT = I DT LH - DT HL I see Figure 5 on page 12Doc ID 14497 Rev 49/195.2 DCoperationV CC = 15 V; T J = +25 °CTable 8.DC operation electrical characteristicsSymbol Pin Parameter Testcondition Min TypMaxUnit Low supply voltage sectionV cc_hys4V cc UVhysteresis 1.2 1.5 1.8 VV cc_thON V cc UV turn ON threshold 99.510V V cc_thOFF V cc UV turn OFF threshold 7.688.4I qccu Undervoltage quiescent supply current V CC= 7 V; SD = 5 V;PHASE andBRAKE = GND;R DT = 0 Ω;CP + = GND; CP - = 0.5 V110150µAI qcc Quiescent current V CC= 15 V; SD = 5 V;PHASE andBRAKE = GND;R DT = 0 Ω;CP + = GND; CP - = 0.5 V6001000Bootstrapped supply voltage section (1)V BO_hys14V BO UVhysteresis 0.8 1.0 1.2 VV BO_thON V BO UV turn ON threshold 8.299.8V V BO_thOFF V BO UV turn OFF Threshold 7.388.7VI QBOU UndervoltageV BOOT quiescent current V BO = 7 V SD = 5 V;PHASE andBRAKE = 5 V; R DT = 0 Ω;CP + = GND; CP - = 0.5 V40100µAI QBO V BOOT quiescent current V BO = 15 V SD = 5 V;PHASE andBRAKE = 5 V; R DT = 0 Ω;CP + = GND; CP - = 0.5 V140210I LK High voltage leakage current V hvg = V out = V boot=600 V10R DSon Bootstrap driver on resistance (2)LVG ON 120ΩDriving buffers sectionI so10,13 High/low side source short circuitcurrentV IN = V ih(t p< 10 µs) 200290mAI si High/low side sink short circuit current V IN = V il (t p < 10 µs)250430mA Logic inputsV il 1,2, 3 Low logic level voltage0.8VV ih High logic level voltage 2.25V10/19Doc ID 14497 Rev 4分销商库存信息:STML6393DTR L6393D。