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L6398DTR;L6398D;中文规格书,Datasheet资料

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April 2011Doc ID 18199 Rev 31/16L6398High voltage high and low side driverFeatures■High voltage rail up to 600 V■dV/dt immunity ±50 V/ns in full temperature range■Driver current capability:–290 mA source,–430 mA sink■Switching times 75/35 ns rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS input comparators with hysteresis■Integrated bootstrap diode ■Fixed 320 ns dead-time ■Interlocking function■Compact and simplified layout ■Bill of material reduction ■Flexible, easy and fast designApplications■Motor driver for home appliances, factory automation, industrial drives and fans.DescriptionThe L6398 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT .The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP .Table 1.Device summaryOrder codes Package Packaging L6398N DIP-8T ube L6398D SO-8T ube L6398DTRSO-8Tape and reelContents L6398Contents1Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.3Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.1AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.2DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118.1CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152/16Doc ID 18199 Rev 3L6398Block diagramDoc ID 18199 Rev 33/161 Block diagramPin connection L63984/16Doc ID 18199 Rev 32 Pin connectionTable 2.Pin descriptionPin n #Pin nameType Function1 LIN I Low side driver logic input (active low)2 HIN I High side driver logic input (active high) 3VCCPLower section supply voltage4 G ND P G round5 LV G(1)1.The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with V CC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low.O Low side driver output6 OUTP High side (floating) common voltage 7 HV G(1) O High side driver output 8 BOOTPBootstrapped supply voltageL6398Truth tableDoc ID 18199 Rev 35/163 Truth tableTable 3.Truth tableInputOutputLIN H IN LVG H VG HLLLL H L L L L H L H H LHElectrical data L63986/16Doc ID 18199 Rev 34 Electrical data4.1Absolute maximum ratingsNote:ESD immunity for pins 6, 7 and 8 is guaranteed up to 1 kV (human body model)4.2 Thermal data4.3 Recommended operating conditionsTable 4.Absolute maximum ratingSymbolParameterValueUnitMinMax V cc Supply voltage -0.321V V outOutput voltageV boot - 21 V boot + 0.3V V boot Bootstrap voltage -0.3620V V hvg High side gate output voltage V out - 0.3 V boot + 0.3 V V lvg Low side gate output voltage -0.3V cc + 0.3 V V iLogic input voltage-0.315V dV out /dt Allowed output slew rate 50V/ns P tot Total power dissipation (T A = 25 °C) 800mW T J Junction temperature 150°C T stgStorage temperature-50150°CTable 5.Thermal dataSymbol Parameter SO-8DIP-8Unit R th(JA)Thermal resistance junction to ambient150100°C/WTable 6.Recommended operating conditionsSymbol Pin ParameterTest conditionMin Max Unit V cc 3Supply voltage 1020V V BO (1)1.V BO = V boot - V out8-6Floating supply voltage 9.820V V out 6Output voltage - 11 (2)2.LVG off. Vcc = 10 VLogic is operational if V boot > 5 V580V f sw Switching frequency HVG, LVG load C L = 1 nF800kHz T JJunction temperature-40125°CDoc ID 18199 Rev 37/165 Electrical characteristics5.1 AC operationTable 7.AC operation electrical characteristics (V CC = 15 V; T J = +25 °C)Symbol Pin ParameterTest conditionMin TypMax Unitt on1, 2vs 5, 7High/low side driver turn-on propagation delay V out = 0 V V boot = VccC L = 1 nFV IN = 0 to 3.3 VSee Figure 350125 200nst offHigh/low side driver turn-offpropagation delay50 125 200 ns DT Dead time(1)C L = 1 nF 225320415ns t r 5, 7Rise time C L = 1 nF 75 120 ns t fFall timeC L = 1 nF3570ns1.See Figure 4 on page 9.5.2 DCoperationTable 8.DC operation electrical characteristics (V CC = 15 V; T J = + 25 °C)Symbol Pin Parameter Test condition Min Typ Max UnitV cc_hys3 V cc UV hysteresis 1.2 1.5 1.8VV cc_thON V cc UV turn ON threshold99.510V V cc_thOFF V cc UV turn OFF threshold 7.688.4VI qccu Undervoltage quiescentsupply currentV cc = 7 VLIN = 5 V; HIN = GND;90150μAI qcc Quiescent current V cc = 15 VLIN = 5 V; HIN = GND;380440μABootstrapped supply voltage section (1)V BO_hys8V BO UV hysteresis0.81 1.2VV BO_thON V BO UV turn ON threshold 8.299.8V V BO_thOFF V BO UV turn OFF threshold 7.388.7VI QBOU Undervoltage V BO quiescentcurrentV BO = 7 V, LIN = HIN = 5V3060μAI QBO V BO quiescent current V BO = 15 V, LIN = HIN = 5V190240μA I LK High voltage leakage current V hvg = V out = V boot = 600 V10μAR DS(on) Bootstrap driver on resistance(2)LVG ON120ΩDriving buffers sectionI so5,7High/low side source shortcircuit currentV IN = V ih (t p < 10 μs) 200290mAI si High/low side sink shortcircuit currentV IN = V il (t p < 10 μs) 250430mALogic inputsV il1, 2Low logic level voltage0.8VV ih High logic level voltage 2.25VV il_S 1, 2Single input voltageLIN and HIN connectedtogether and floating0.8VI HINh2HIN logic “1” input biascurrentHIN = 15 V110175260μAI HINl HIN logic “0” input biascurrentHIN = 0 V1μAI LINl1LIN logic “0” input bias current LIN = 0 V3620μAI LINh LIN logic “1” input bias current LIN = 15 V1μA1.V BO = V boot - V out2.R DSON is tested in the following way: R DSON = [(V CC - V CBOOT1) - (V CC - V CBOOT2)] / [I1(V CC,V CBOOT1) - I2(V CC,V CBOOT2)]where I1 is pin 8 current when V CBOOT = V CBOOT1,I2 when V CBOOT = V CBOOT2.8/16Doc ID 18199 Rev 3L6398Waveforms definitionsDoc ID 18199 Rev 39/166 Waveforms definitionsFigure 4.Dead time and interlocking waveforms definitionsLINHINLVG HVGLINHIN LVGHVGLINHIN LVGHVGLINHIN LVGHVGDT LHDT HLDT LHDT HLDT LHDT HLDT LHDT HLgate driver outputs OFF(HALF-BRIDGE TRI-STATE)I L I N T E RO C KN GCONTROL SIGNAL EDGES OVERLAPPED:INTERLOCKING + DEAD TIMECONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIMECONTROL SIGNALS EDGES NOT OVERLAPPED,BUT INSIDE THE DEAD TIME:DEAD TIMECONTROL SIGNALS EDGES NOT OVERLAPPED,OUTSIDE THE DEAD TIME:DIRECT DRIVING(*) HIN and LIN can be connected togheter and driven by just one control signalI N T E R L O C K I N Ggate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)gate driver outputs OFF (HALF-BRIDGE TRI-STATE)Typical application diagram L6398 7 Typical application diagram10/16Doc ID 18199 Rev 3分销商库存信息:STML6398DTR L6398D。

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maxim MAX6394 Datasheet说明书

maxim MAX6394 Datasheet说明书

General DescriptionThe MAX6394 low-power CMOS microprocessor (µP)supervisory circuit is designed to monitor power sup-plies in µP and digital systems. It offers excellent circuit reliability by providing 1% accurate thresholds over temperature and by eliminating external components and adjustments. The MAX6394 also provides a debounced manual reset input.This device performs a single function: it asserts a reset signal whenever the V CC supply voltage falls below a preset threshold or whenever manual reset is asserted.RESET remains asserted for an internally programmed interval (reset timeout period) after V CC has risen above the reset threshold or manual reset is deasserted. The MAX6394’s open-drain RESET output can be pulled up to a voltage higher than V CC .The MAX6394 comes with factory-trimmed reset thresh-old voltages from 2.4V to 4.8V. Preset timeout periods of 0.7ms, 14ms, 105ms, and 826ms are also available.The device comes in a SOT143 package.ApplicationsComputers ControllersIntelligent InstrumentsCritical μP and μC Power Monitoring Portable/Battery-Powered EquipmentFeatureso ±0.6% Threshold Accuracy at T A = +25°Co ±1.0% Threshold Accuracy from -40°C to +125°C o Small SOT143 Packageo Open-Drain RESET Output Can Exceed V CC oPrecision, Factory-Set V CC Reset Thresholds:Nine Options from 2.4V to 4.8Vo Four Reset Timeout Periods Available:0.7ms, 14ms, 105ms, and 826ms (minimum) o Immune to Short V CC Transients o 5µA Supply CurrentMAX6394High-Accuracy µP Reset Circuit________________________________________________________________Maxim Integrated Products 11+243VCCMR RESET GNDMAX6394SOT143TOP VIEWPin ConfigurationMAX6394VCCV CCGNDRESETμPRESETMRLASER-TRIMMED RESISTORSRESET CIRCUITRYTypical Operating Circuit19-3202; Rev 0; 1/08For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .Note:This device is specified over the -40°C to +125°C operat-ing temperature range.+Denotes a lead-free package.Note:The "_ _ _" is a placeholder for the input voltage thresholds.Nine threshold options are available. See Tables 1 and 2 for more information.Note:The "_" is a placeholder for the timeout option. Fouroptions are available. See the Timeout Options section for more information.Four standard versions are available (see the Standard Versions Selector Guide section). Samples are generally available in standard versions. Contact factory for availability of nonstandard versions.Note:All devices are available in tape-and-reel only. Tape and reel is offered in 2.5k increments.Ordering InformationPARTPIN-PACKAGE PKG CODEMAX6394US_ _ _D_+T4 SOT143-4U4-1查询"MAX6394"供应商M A X 6394High-Accuracy µP Reset Circuit 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Other thresholds may be available. Contact factory for availability.VCC.......................................................................-0.3V to +6.0V RESET ....................................................................-0.3V to +6.0V All Other Pins..............................................-0.3V to (V CC + 0.3V)Input Current (V CC ).............................................................20mA Output Current (RESET )......................................................20mA Rate of Rise (V CC )...........................................................100V/µsContinuous Power Dissipation (T A = +70°C)SOT143 (derate 4mW/°C above +70°C)........................320mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10s).................................+300°CMAX6394High-Accuracy µP Reset Circuit_______________________________________________________________________________________360-50-303090SUPPLY CURRENT vs. TEMPERATURE215TEMPERATURE (°C)S U P P L Y C U R R E N T (μA )-101050347060135SUPPLY CURRENT vs. SUPPLY VOLTAGE215SUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (μA )2344500-50-301090POWER-DOWN RESET DELAYvs. TEMPERATURE1040TEMPERATURE (°C)P O W E R -D O W N R E S E T D E L A Y (μs )-1020303050701.040.96-50-301090NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE (V CC RISING)0.970.981.021.001.03M A X 6394 t o c 04TEMPERATURE (°C)N O R M A L I Z E D R E S E T T I M E O U T P E R I O D-100.991.013050701.0060.994-50-301090NORMALIZED RESET THRESHOLD vs. TEMPERATURE (V CC FALLING)0.9960.9981.0041.000M A X 6394 t o c 05TEMPERATURE (°C)N O R M A L I Z E D R E S E T T H R E S H O L D-101.0023050701000101001000MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE20RESET COMP. OVERDRIVE, V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (μs )406080Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)Detailed DescriptionReset OutputA microprocessor’s (µP’s) reset input starts the µP in a known state. The MAX6394 asserts a reset signal to prevent code-execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic-low for V CC > 1V (see the Electrical Characteristics table). Once V CC exceeds the reset threshold, the internal timer keeps RESET asserted for the reset timeout period (t RP ); after this interval RESET goes high. If a brownout condition occurs (monitored voltage dips below its programmed reset threshold),RESET goes low. Any time V CC dips below the reset threshold, the internal timer resets to zero and RESET goes low. The internal timer starts when V CC returns above the reset threshold, and RESET remains low for the reset timeout period.The MAX6394’s RESET output structure is a simple open-drain n-channel MOSFET switch. Connect a pullup resistor to any supply in the 0 to +6V range. Select a resistor value large enough to register a logic-low when RESET is asserted (see the Electrical Characteristics table), and small enough to register a logic-high while supplying all input current and leakage paths connect-ed to the RESET line. A 10k Ωpullup is sufficient in most applications.Often, the pullup connected to the MAX6394’s RESET output connects to the supply voltage monitored at the IC’s VCC pin. However, some systems may use the open-drain output to level-shift from the monitored sup-ply to reset circuitry powered by some other supply (F igure 1). This is one useful feature of an open-drain output. Keep in mind that as the MAX6394’s V CC decreases below 1V, so does the IC’s ability to sink current at RESET . F inally, with any pullup, RESET is pulled high as V CC decays toward 0V. The voltage where this occurs depends on the pullup resistor value and the voltage to which it connects (see the Electrical Characteristics table).Manual-Reset InputMany µP-based products require manual-reset capa-bility, allowing the operator, a test technician, or exter-nal logic circuitry to initiate a reset. A logic-low on MR asserts reset. RESET remains asserted while MR is low, and for the reset active timeout period after MR returns high.MR has an internal 63k Ωpullup resistor, so it can be left open if not used. Connect a normally open momen-tary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to ground provides additional noise immunity.Applications InformationNegative-Going V CC TransientsIn addition to issuing a reset to the µP during power-up,power-down, and brownout conditions, these devices are relatively immune to short-duration negative-going transients (glitches). The Typical Operating Character-istics show the Maximum Transient Duration vs. Reset Threshold Overdrive, for which reset pulses are not generated. The graph was produced using negative-going pulses, starting at VRST max and ending below the programmed reset threshold by the magnitude indi-cated (reset threshold overdrive). The graph shows the maximum pulse width that a negative-going V CC tran-sient may typically have without causing a reset pulse to be issued. As the transient amplitude increases (i.e.,goes farther below the reset threshold), the maximum allowable pulse width decreases. A 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity.M A X 6394High-Accuracy µP Reset Circuit 4_______________________________________________________________________________________Figure 1. MAX6394 Open-Drain RESET Output Allows Use with Multiple SuppliesChip InformationTRANSISTOR COUNT: 519MAX6394High-Accuracy µP Reset Circuit_______________________________________________________________________________________5Table 1. ±0.6% of ThresholdsStandard VersionsSelector GuideTable 2. ±1% of ThresholdsM A X 6394High-Accuracy µP Reset Circuit 6_______________________________________________________________________________________Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX6394High-Accuracy µP Reset CircuitMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________7©2008 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc. Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages.)。

WP3A8YD;中文规格书,Datasheet资料

WP3A8YD;中文规格书,Datasheet资料


PACKING & LABEL SPECIFICATIONS
WP3A8YD
SPEC NO: DSAH3029 APPROVED: WYNEC
REV NO: V.2 CHECKED: Allen Liu
DATE: MAY/10/2007 DRAWN: Y.L.LI
PAGE: 4 OF 6 ERP: 1101011317
Part No. Dice Lens Type Iv (mcd) [2] @ 10mA Min. WP3A8YD Yellow (GaAsP/GaP) YELLOW DIFFUSED 5 Typ. 15 Viewing Angle [1] 2θ1/2 50°
Notes: 1. θ1/2 is the angle from optical centerline where the luminous intensity is 1/2 the optical centerline value. 2. Luminous intensity/ luminous Flux: +/-15%.
Notes: 1.Wavelength: +/-1nm. 2. Forward Voltaum Ratings at TA=25°C
Parameter Power dissipation DC Forward Current Peak Forward Current [1] Reverse Voltage Operating/Storage Temperature Lead Solder Temperature [2] Lead Solder Temperature [3]
Notes: 1. 1/10 Duty Cycle, 0.1ms Pulse Width. 2. 2mm below package base. 3. 5mm below package base.
DC9S08QB8;DC9S08QE8;DEMO9S08QB8;中文规格书,Datasheet资料

DC9S08QB8;DC9S08QE8;DEMO9S08QB8;中文规格书,Datasheet资料

/Purchase AgreementP&E Microcomputer Systems, Inc. reserves the right to make changes without further notice to anyproducts herein to improve reliability, function, or design. P&E Microcomputer Systems, Inc. does notassume any liability arising out of the application or use of any product or circuit described herein.This software and accompanying documentation are protected by United States Copyright law andalso by International Treaty provisions. Any use of this software in violation of copyright law or theterms of this agreement will be prosecuted.All the software described in this document is copyrighted by P&E Microcomputer Systems, Inc.Copyright notices have been included in the software.P&E Microcomputer Systems authorizes you to make archival copies of the software anddocumentation for the sole purpose of back-up and protecting your investment from loss. Under nocircumstances may you copy this software or documentation for the purpose of distribution to others.Under no conditions may you remove the copyright notices from this software or documentation.This software may be used by one person on as many computers as that person uses, provided thatthe software is never used on two computers at the same time. P&E expects that group programmingprojects making use of this software will purchase a copy of the software and documentation for eachuser in the group. Contact P&E for volume discounts and site licensing agreements.P&E Microcomputer Systems does not assume any liability for the use of this software beyond theoriginal purchase price of the software. In no event will P&E Microcomputer Systems be liable foradditional damages, including any lost profits, lost savings or other incidental or consequentialdamages arising out of the use or inability to use these programs, even if P&E Microcomputer Systemshas been advised of the possibility of such damage.By using this software, you accept the terms of this agreement.© 2009 P&E Microcomputer Systems, Inc. “MS-DOS” and “Windows” are registered trademarks ofMicrosoft Corporation. “Freescale” and “ColdFire” are registered trademarks of Freescale, Inc. “IBM”and “PowerPC” are registered trademarks of IBM corporation.P&E Microcomputer Systems, Inc.98 Galen St.Watertown, MA 02472617-923-0053Manual version 1.03/DEMO9S08QB8 User Manualii1INTRODUCTION (1)1.1Overview ........................................................................................................11.2Package Contents..........................................................................................11.3Supported Devices.........................................................................................11.4Recommended Materials On DEMO9S08QB8 Resources CD......................11.5Handling Precautions.....................................................................................22HARDWARE FEATURES. (2)2.1DEMOQE Base Board Features ....................................................................22.2On-Board Logic Analyzer...............................................................................42.3On-Board Virtual Serial Port...........................................................................42.4DEMOQE Daughter Card Features................................................................52.5DC9S08QB8 Specific Connections................................................................52.6Signal Mapping of DC9S08QB8 to MCU_PORT............................................63SYSTEM SETUP.. (8)3.1Overview ........................................................................................................83.2Operating System Requirements...................................................................83.3Software Setup...............................................................................................83.4Quick Startup..................................................................................................93.5Hardware Setup ...........................................................................................104OPERATING MODES.. (13)4.1Overview ......................................................................................................134.2Debug Mode.................................................................................................134.3Run Mode.....................................................................................................144.4External BDM Mode.....................................................................................145DEMOQE TOOLKIT PC APPLICATIONS . (14)5.1DEMOQE Logic Analyzer Application..........................................................145.2DEMOQE Terminal Application....................................................................165.3DEMOQE Unsecure Application ..................................................................165.4DEMOQE Accelerometer Demo Application................................................175.5DEMOQE Serial Grapher Application (18)6DEMONSTRATION MICROCONTROLLER APPLICATIONS (21)/iiiDEMO9S08QB8 User Manual 6.1Quick Start Application (21)6.2Serial Accelerometer Application (22)7JUMPER SETTINGS (22)7.1System Power (22)7.2RS232 Communications (24)7.3LED Display Port (26)7.4Input and Reset Switches (27)7.53-Axis Accelerometer Jumper Settings (28)7.6Buzzer (30)7.7IIC Pull-up (31)7.8Analog Input Potentiometer (31)7.9Optional External Crystal Circuitry Jumper Enable (31)7.10Optional Jumpers For Various VDD And VSS (32)8DEMO9S08QB8 CODE DEVELOPMENT SOFTWARE (32)8.1Using CodeWarrior With The DEMO9S08QB8 (32)8.2Using P&E Software With The DEMO9S08QB8 (33)9TRANSITIONING TO YOUR OWN TARGET (33)9.1Hardware Solutions At A Glance (33)9.2Working With P&E’s USB Multilink (34)9.3Working With P&E’s Cyclone PRO (35)10TROUBLESHOOTING (36)10.1DEMO9S08QB8 Is Undetected (36)10.2CodeWarrior Installation Fails (WinDriver Error) (38)/DEMO9S08QB8 User Manual11INTRODUCTION1.1OverviewThe DEMO9S08QB8 is a low-cost development system designed for demonstrating, evaluating, and debugging the Freescale MC9S08QB8microcontroller. P&E’s Embedded Multilink circuitry on the DEMO9S08QB8 board allows the processor on the DEMO9S08QB8 to be debugged and programmed via USB from the PC. In addition, the demo board can be powered using the USB bus.Note:Freescale has an older device called 908QB8. 908QB8 is different from this new 9S08QB8 device. When searching for “QB8” online resources, make sure that the resources pertain to the 9S08QB8 device and NOT the 908QB8 device.1.2Package ContentsThe DEMO9S08QB8 package includes the following items:•DEMOQE Base Board with a MC9S08QB8 Daughter Card installed •2-cell AAA battery package •USB Cable •Quick Start Guide •Freescale Warranty Card1.3Supported DevicesThe DEMO9S08QB8 supports the MC9S08QB8CWL device.1.4Recommended Materials On DEMO9S08QB8 Resources CD•DEMO9S08QB8 Embedded Multilink hardware interface driver/2DEMO9S08QB8 User Manual •DEMO9S08QB8 User Manual (this document)•DEMO9S08QB8 Quick Start Guide•DEMO9S08QB8 Quick Start Application Source Code•DEMO9S08QB8 Base Board and Daughter Cards Schematics •DEMO9S08QB8 Component Breakdown List•DEMOQE Toolkit Applications•Links to P&E Evaluation Software•Links to Freescale documentation, P&E Discussion Forums, and DEMO9S08QB8 FAQs.1.5Handling PrecautionsTake care to handle the package contents, including the DEMOQE baseboard and MC9S08QB8 daughter card, in a manner such as to preventelectrostatic discharge.2HARDWARE FEATURESThe DEMO9S08QB8 is a demonstration and development system forFreescale’s MC9S08QB8 microcontroller. Application development is quickand easy using P&E’s Embedded Multilink circuitry and the included softwaretools and examples. An optional BDM port is provided to allow use of anexternal BDM interface such as P&E’s Cyclone PRO automated programmeror USB Multilink. The USB Multilink is functionally comparable to theDEMO9S08QB8’s Embedded Multilink circuitry.Note:The DEMO board’s onboard Embedded Multilink circuitry is intended to function with the onboard processor and any daughter cards that may beincluded. It cannot be used to communicate with other devices.2.1DEMOQE Base Board Features•On-board Logic Analyzer•On-board Virtual Serial Port•Asymmetrically positioned 4 8x2 male connectors for interchangeabledaughter cards/DEMO9S08QB8 User Manual3•P&E’s Embedded Multilink circuitry populated on the bottom •RS-232 Serial Port w/ DB9-F Connector•SCI signals connected to P&E’s Embedded Multilink through jumpers •ON/OFF Power Switch w/ LED indicator•A 5VDC to 8VDC power supply input barrel connectorNote:The DEMOQE board power connector is incorrectly labelled as 5-12VDC. The maximum voltage is 8VDC.•Power Input Selection Jumpers for selecting the input voltage source:•Power Input from Embedded Multilink to LDO regulator •Power Input from DC Power Jack to LDO regulator •Regulated VDD Output at 3.0V •Regulated VDD Output at 2.1V •Power Input from Battery•Power Input from MCU_PORT connector•RESET Push Button and LED indicator w/ Enable •Optional External Crystal Circuitry Layout (not populated)•User Features:•3-axis Accelerometer w/Enable •8 User LED’s w/ Enable • 4 User Push Buttons w/ Enable • 1 Piezzo Buzzer w/ Enable •IIC Pullups w/ Enable •10K Ohm POT w/ Enable•Option Jumpers:•COM_EN for 1.8V to 4.25V RS232 Transceiver •TXD_EN for SCI_TXD to Embedded Multilink •RXD_EN for SCI_RXD to Embedded Multilink•INPUT_EN for two input channels to Embedded Multilink/4DEMO9S08QB8 User Manual •Specifications:•Board Size 3.5 x 4.0•Power Input:•USB Cable: 5VDC, 500mA max•DC Power Jack: 2.5/5.5mm barrel connector, 5VDC to 8VDCCenter PositiveNote:The DEMOQE board power connector is incorrectly labelled as 5-12VDC.The maximum voltage is 8VDC.•Two AAA Battery CellsFigure 2-1: DEMOQE Top Component Placement2.2On-Board Logic AnalyzerThe DEMOQE board has a built-in 2-channel logic analyzer which may beused to display captured data in real-time on a host PC. The logic analyzerchannels (IN0/IN1) are connected to the PTC0 and PTC1 signals on theDEMOQE board by default via the J11 jumpers. The channels may beconnected to any of the processor pins by wire jumpers (not included).The DEMOQE Logic Analyzer Utility, included in the DEMOQE Toolkit on theaccompanying DVD-ROM, displays the logic analyzer signals on a PC. /DEMO9S08QB8 User Manual52.3On-Board Virtual Serial PortThe DEMOQE board has a built-in virtual serial port which may be connected to the QE processor’s SCI RXD/TXD. This allows certain PC applications to be able to connect in a serial fashion to the microcontroller without the actual use of serial port hardware.The DEMOQE Terminal Window Utility, included in the DEMOQE Toolkit on the accompanying DVD-ROM, is a generic serial port utility which works with the DEMOQE virtual serial port or actual serial port hardware.2.4DEMOQE Daughter Card Features•Four bottom-mounted asymmetrically positioned 8x2 female connectors to mate with the DEMOQE Base Board •A top-mounted MC9S08QB8CWL chip2.5DC9S08QB8 Specific ConnectionsThe labels on the DEMOQE do not necessarily represent actual pin portfunction from the MC9S08QB8 microcontroller. In order to take full advantage of the DEMOQE Base Board resources, MC9S08QB8 signals are mapped to the DEMOQE Base Board 64-Pin Header as following:SIGNALS OF QB8SIGNALS OF DEMOQE BOARDPTA0-3PTA0-3PTA4/BKGD PTA4/BKGD PTA5/RESETPTA5/RESET PTA6PTD2/KEY PTA7PTD3/KEY PTB0-1PTB0-1PTB2/ADP PTA6/ADP PTB3/ADPPTA7/ADP/6DEMO9S08QB8 User Manual2.6Signal Mapping of DC9S08QB8 to MCU_PORTPTB4-5PTB4-5PTB6/XTAL PTB6/XTAL PTB7/EXTAL PTB7/EXTAL PTC0-5PTC0-5PTC6PTE6/LED PTC7PTE7/LEDSignal MappingMCU PORT NUMBERMC9S08QB8 PINSIGNAL MCU PORT NUMBERMC9S08QB8 PINSIGNAL 1VDD 2PTA5/IRQ/TCLK/~RESET 3VSS4PTA5/IRQ/TCLK/~RESET5PTB1/KBIP5/TxD/ADP56PTA4/ACMPO/BKGD/MS 7PTB0/KBIP4/RxD/ADP48PTC79PTA2/KBIP2/ADP210VREFH 11PTA3/KBIP3/ADP312VREFL13PTC014PTA0/KBIP0/TPMCH0/ADP0/ACMP+SIGNALS OF QB8SIGNALS OF DEMOQE BOARD/分销商库存信息:FREESCALEDC9S08QB8DC9S08QE8DEMO9S08QB8。

L6599D中文资料

L6599D中文资料

L6599D中⽂资料May 2006 Rev 11/36L6599High-voltage resonant controllerFeatures■50% duty cycle, variable frequency control of resonant half-bridge ■High-accuracy oscillator■Up to 500kHz operating frequency■Two-level OCP: frequency-shift and latched shutdown■Interface with PFC controller ■Latched disable input■Burst-mode operation at light load ■Input for power-ON/OFF sequencing or brownout protection■Non-linear soft-start for monotonic output voltage rise■600V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity■-300/800mA high-side and low-side gate drivers with UVLO pull-down ■DIP-16, SO-16N packagesApplications■LCD & PDP TV■Desktop PC, entry-level server ■Telecom SMPS■AC-DC adapter, open frame SMPSOrder codePart number Package Packaging L6599D SO-16N T ube L6599TR SO-16N Tape and reelL6599NDIP-16T ube/doc/128b95b11a37f111f1855bea.htmlContents L6599Contents1Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.2Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.3Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.4Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.6Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.7Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297.8Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352/36L6599Device description3/361 Device descriptionThe L6599 is a double-ended controller specific for the resonant half-bridge topology. Itprovides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON 180° out-of-phase for exactly the same time.Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-time inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode.The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well.The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum.IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart.A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP .An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.Pin Settings L65994/362 Pin Settings2.1 Connection2.2 FunctionsTable 1.Pin functionsN.NameFunction1C SSSoft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4)that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (V CC < UVLO, LINE < 1.25V or > 6V , DIS > 1.85V , ISEN > 1.5V , DELAY > 3.5V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V , as long as it stays above 0.75V .2DELAYDelayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8V the capacitor is charged by an internal 150µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2V , the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150µA is kept always on. As the voltage on the pin exceeds 3.5V the IC stops switching and the internal generator is turned OFF , so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V . In this way, under short circuit conditions, the converter will work intermittently with very low input average power.3CFTiming capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.L6599Pin Settings5/364RFminMinimum oscillator frequency setting. This pin provides a precise 2V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. T o close the feedback loop that regulates the converter output voltage bymodulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operatingfrequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).5STBYBurst-mode operation threshold. The pin senses some voltage related to the feedbackcontrol, which is compared to an internal reference (1.25V). If the voltage on the pin is lower than the reference, the IC entersan idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50mV . Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.6ISENCurrent sense input. The pin senses the primary current though a sense resistor or acapacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.7LINELine sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V . The comparator is provided with current hysteresis: an internal 15µA current generator is ON as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6V if the function is not used.8DISLatched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85V , shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the V CC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.9PFC_STOPOpen-drain ON/OFF control of PFC controller. This pin, normally open, is intended forstopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85V , ISEN > 1.5V , LINE > 6V and STBY < 1.25V .The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V . During UVLO, it is open. Leave the pin unconnected if not used.10GNDChip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.Table 1.Pin functionsTypical system block diagram L65996/363 Typical system block diagramTypical system block diagram11LVGLow-side gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.12V CC Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.13N.C.High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.14OUTHigh-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.15HVGHigh-side floating gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.16VBOOTHigh-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.Table 1.Pin functionsL6599Electrical data7/364 Electrical data4.1 Maximum ratingsNote:ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V4.2 Thermal dataTable 2.Absolute maximum ratingsSymbol Pin ParameterValue Unit V BOOT 16 Floating supply voltage -1 to 618 V V OUT 14 Floating ground voltage -3 to V BOOT -18V dV OUT /dt 14 Floating ground max. slew rate 50V/nsV CC 12 IC Supply voltage (I CC ≤ 25 mA) Self-limited V V PFC_STOP 9 Maximum voltage (pin open) -0.3 to V CC V I PFC_STOP 9 Maximum sink current (pin low)AV LINEmax 7Maximum pin voltage (Ipin ≤ 1mA) Self-limited VI RFmin4 Maximum source current 2 mA 1 to 6, 8 Analog inputs & outputs-0.3 to 5VTable 3.Thermal dataSymbol DescriptionValue Unit R thJA Max. thermal resistance junction to ambient (DIP16)80°C/W Max. thermal resistance junction to ambient (SO16)120T STG Storage temperature range-55 to 150°C T J Junction operating temperature range-40 to 150°C P TOTRecommended max. power dissipation @T A = 70°C (DIP16) 1 WRecommended max. power dissipation @T A = 50°C (SO16)0.835 ElectricalcharacteristicsT J = 0 to 105°C, V CC = 15V, V BOOT = 15V, C HVG = C LVG = 1nF; C F = 470pF;R RFmin = 12k?; unless otherwise specified.Table 4.Electrical characteristicsSymbol Parameter TestconditionMin Typ Max Unit IC supply voltageV CC Operating range After device turn-on8.85 16 VV CC(ON)Turn-ON threshold Voltage rising10 10.7 11.4 VV CC(OFF)Turn-OFF threshold Voltagefalling 7.45 8.15 8.85 V Hys Hysteresis 2.55 VV Z V CC clamp voltage Iclamp = 10mA 16 17 17.9 V Supply currentI start-up Start-up current Before device turn-ONV CC = V CC(ON) - 0.2V200 250 µAI q Quiescent current Device ON, V STBY = 1V 1.5 2 mAI op Operating current Device ON,V STBY = V RFmin 3.5 5 mAI q Residual consumption V DIS> 1.85V or V DELAY> 3.5V or V LINE < 1.25 Vor V LINE = V clamp300 400 µAHigh-side floating gate-drive supplyI LKBOOT V BOOT pin leakagecurrentV BOOT= 580V 5 µAI LKOUT OUT pin leakage current VOUT= 562V 5 µAr DS(on)Synchronous bootstrapdiode ON-resistanceV LVG= High 150 ?Overcurrent comparatorI ISEN Input bias current V ISEN = 0 to V ISENdis-1 µAt LEB Leading edge blanking After V HVG and V LVGlow-to-high transition250 nsV ISENx Frequency shiftthreshold Voltage rising(1)0.76 0.8 0.84 VHysteresis Voltagefalling 50 mV V ISENdis Latch OFF threshold Voltage rising (1) 1.44 1.5 1.56 V td(H-L)Delay to output 300400 ns8/369/36Symbol Parameter Test condition Min Typ Max UnitLine sensing V th Threshold voltage Voltage rising or falling(1)1.2 1.25 1.3 V I Hyst Current hysteresis V CC > 5V , V LINE = 0.3V 12 15 18 µA V clamp Clamp levelI LINE = 1mA6 8 VDIS functionI DIS Input bias current V DIS = 0 to V th -1 µAV th Disable thresholdVoltage rising (1)1.77 1.85 1.93 VOscillatorDOutput duty cycleBoth HVG and LVG4850 52 %f oscOscillation frequency58.2 60 61.8kHzR RFmin = 2.7 k ?240 250 260Maximumrecommended500kHz T D Dead-time Between HVG and LVG0.20.3 0.4µs V CFp Peak value 3.9 V V CFv Valley value 0.9 VV REF Voltage reference at pin 4(1)1.92 22.08 VK M Current mirroring ratio 1A/A RF MINTiming resistor range1100k ?PFC_STOP functionI leak High level leakage currentV PFC_STOP = V CC ,V DIS = 0V 1 µAV LLow saturation levelI PFC_STOP =1mA,V DIS = 2V0.2 VSoft-start functionI leakOpen-state currentV(Css) = 2V0.5µA R Discharge resistance V ISEN > V ISENx 120Standby functionI DIS Input Bias Current V DIS = 0 to V th -1 µAV thDisable thresholdVoltage falling (1) 1.2 1.25 1.3 VHys HysteresisVoltage rising50mVTable 4.Electrical characteristics10/36Symbol Parameter Test condition Min TypMax UnitDelayed shutdown functionI leak Open-state current V(DELAY) = 0 0.5 µAI CHARGE Charge current V DELAY = 1V , V ISEN = 0.85V 100 150 200 µA Vth 1 Threshold for forcedoperation at max. frequencyVoltage rising (1)1.92 22.08 VVth 2Shutdown threshold Voltage rising (1) 3.3 3.5 3.7 V Vth 3Restart thresholdVoltage falling (1)0.25 0.3 0.35 VLow - side gate driver (voltages referred to GND)V LVGL Output low voltage I sink = 200mA 1.5 VV LVGH Output high voltage I source = 5mA12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8A t f Fall time 30 ns t rRise time 60nsUVLO saturationV CC = 0 to V CC(ON),I sink = 2mA 1.1 VHigh-side gate driver (voltages referred to OUT)V HVGL Output low voltage I sink = 200 mA 1.5 V V HVGH Output high voltage I source = 5 mA12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8A t f Fall time 30 ns t rRise time60 ns HVG-OUT pull-down25k ?1.Values traking each otherTable 4.Electrical characteristics11/366 Typical electrical performanceFigure 3.Device consumption vssupply voltageFigure 4.IC consumption vs junction temperatureV CC clamp voltage vs junction temperatureFigure 6.UVLO thresholds vs junction temperature12/36Figure 7.Oscillator frequency vsjunction temperature Figure 8.Dead-time vsjunction temperatureFigure 9.Oscillator frequency vstiming components Figure 10.Oscillator ramp vs junction temperature13/36Figure 11.Reference voltage vsjunction temperatureFigure 12.Current mirroring ratio vsjunction temperatureFigure 13.OCP delay source current vsjunction temperature Figure 14.OCP delay thresholds vs junction temperatureFigure 15.Standby thresholds vsjunction temperatureFigure 16.Current sense thresholds vsjunction temperatureFigure 17.Line thresholds vsjunction temperatureFigure 18.Line source current vsjunction temperatureFigure /doc/128b95b11a37f111f1855bea.html tched disable threshold vs junction temperature7 ApplicationinformationThe L6599 is an advanced double-ended controller specific for resonant half-bridge topology. In these converters the switches (MOSFETs) of the half-bridge leg are alternately switched on and OFF (180° out-of-phase) for exactly the same time. This is commonly referred to as operation at "50% duty cycle", although the real duty cycle, that is the ratio of the ON-time of either switch to the switching period, is actually less than 50%. The reason is that there is an internally fixed dead-time T D, inserted between the turn-OFF of either MOSFET and the turn-ON of the other one, where both MOSFETs are OFF. This dead- time is essential in order for the converter to work correctly: it will ensure soft-switching and enable high-frequency operation with high efficiency and low EMI emissions.To perform converter's output voltage regulation the device is able to operate in different modes (Figure20), depending on the load conditions:1.Variable frequency at heavy and medium/light load. A relaxation oscillator (see "Oscillator" section for more details) generates a symmetrical triangular waveform,which MOSFETs' switching is locked to. The frequency of this waveform is related to a current that will be modulated by the feedback circuitry. As a result, the tank circuitdriven by the half-bridge will be stimulated at a frequency dictated by the feedback loopto keep the output voltage regulated, thus exploiting its frequency-dependent transfer characteristics.2. Burst-mode control with no or very light load. When the load falls below a value, the converter will enter a controlled intermittent operation, where a series of a fewswitching cycles at a nearly fixed frequency are spaced out by long idle periods whereboth MOSFETs are in OFF-state. A further load decrease will be translated into longeridle periods and then in a reduction of the average switching frequency. When theconverter is completely unloaded, the average switching frequency can go down evento few hundred Hz, thus minimizing magnetizing current losses as well as all frequency-related losses and making it easier to comply with energy saving recommendations.Figure 20.Multi-mode operation15/3616/367.1 OscillatorThe oscillator is programmed externally by means of a capacitor (CF), connected from pin 3 (CF) to ground, that will be alternately charged and discharged by the current defined with the network connected to pin 4 (RF min ). The pin provides an accurate 2V reference with about 2mA source capability and the higher the current sourced by the pin is, the higher the oscillator frequency will be. The block diagram of Figure 21 shows a simplified internal circuit that explains the operation. The network that loads the RFmin pin generally comprises three branches:1. A resistor RF min connected between the pin and ground that determines the minimum operating frequency;2.A resistor RF max connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side; while in operation, the phototransistor will modulate the current through this branch - hence modulating the oscillator frequency - to perform output voltage regulation; the value of RF max determines the maximum frequency the half-bridge will be operated at when the phototransistor is fully saturated;3.An R-C series circuit (C SS + R SS ) connected between the pin and ground that enables to set up a frequency shift at start-up (see Chapter 7.3: Soft-start ). Note that the contribution of this branch is zero during steady-state operation.The following approximate relationships hold for the minimum and the maximum oscillatorfrequency respectively:f min 13CF RF min------------------------------------------=f max 13CF RF min RF max ||()--------------------------------------------------------------------------=17/36After fixing CF in the hundred pF or in the nF (consistently with the maximum sourcecapability of the RF min pin and trading this off against the total consumption of the device), the value of RF min and RF max will be selected so that the oscillator frequency is able to cover the entire range needed for regulation, from the minimum value f min (at minimum input voltage and maximum load) to the maximum value f max (at maximum input voltage and minimum load):A different selection criterion will be given for RF max in case burst-mode operation at no-load will be used (see "Operation at no load or very light load" section).In Figure 22 the timing relationship between the oscillator waveform and the gate-drive signals, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the low-side gate-drive is turned on while the oscillator's triangle is ramping upand the high-side gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the IC resumes switching during burst-mode operation, the low-side MOSFET will be switched on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be charged and ready to supply the high-side floating driver.RF min 13CF f min-----------------------------------=RF max RF minf maxf min----------1–--------------------=7.2 Operation at no load or very light loadWhen the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency willbe at its maximum value. T o keep the output voltage under control in these conditions and toavoid losing soft-switching, there must be some significant residual current flowing throughthe transformer's magnetizing inductance. This current, however, produces someassociated losses that prevent converter's no-load consumption from achieving very lowvalues.To overcome this issue, the L6599 enables the designer to make the converter operateintermittently (burst-mode operation), with a series of a few switching cycles spaced out bylong idle periods where both MOSFETs are in OFF-state, so that the average switchingfrequency can be substantially reduced. As a result, the average value of the residualmagnetizing current and the associated losses will be considerably cut down, thusfacilitating the converter to comply with energy saving recommendations.The device can be operated in burst-mode by using pin 5 (STBY): if the voltage applied tothis pin falls below 1.25V the IC will enter an idle state where both gate-drive outputs arelow, the oscillator is stopped, the soft-start capacitor C SS keeps its charge and only the 2Vreference at RF min pin stays alive to minimize IC's consumption and V CC capacitor'sdischarge. The IC will resume normal operation as the voltage on the pin exceeds 1.25V by50mV.To implement burst-mode operation the voltage applied to the STBY pin needs to be relatedto the feedback loop. Figure23 shows the simplest implementation, suitable with a narrowinput voltage range (e.g. when there is a PFC front-end).18/3619/36Essentially, RF max will define the switching frequency f max above which the L6599 will enter burst-mode operation. Once fixed f max , RF max will be found from the relationship:Note that, unlike the f max considered in the previous section ("Chapter 7.1: Oscillator "), here f max is associated to some load Pout B greater than the minimum one. Pout B will be such that the transformer's peak currents are low enough not to cause audible noise.Resonant converter's switching frequency, however, depends also on the input voltage; hence, in case there is quite a large input voltage range with the circuit of Figure 23 the value of Pout B would change considerably. In this case it is recommended to use thearrangement shown in Figure 24 where the information on the converter's input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction R A / (R A + R B ) needed to minimize the change of Pout B . Just be careful in choosing the total value R A + R B much greater than R C to minimize the effect on the LINE pin voltage (see Chapter 7.6: Line sensing function ).Whichever circuit is in use, its operation can be described as follows. As the load falls below the value Pout B the frequency will try to exceed the maximum programmed value f max and the voltage on the STBY pin (V STBY ) will go below 1.25V . The IC will then stop with both gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The voltage V STBY will now increase as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.3V, the IC will restart switching. After a while, V STBY will go down again in response to the energy burst and stop the IC. In this way the converter will work in a burst-mode fashion with a nearly constant switching frequency. A further load decrease will then cause a frequency reduction, which can go down even to few hundred hertz. The timing diagram of Figure 25 illustrates this kind of operation, showing the most significant signals. A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, will help get clean operation. To help the designer meet energy saving requirements even in power-factor-correctedsystems, where a PFC pre-regulator precedes the DC-DC converter, the device allows that the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the no-load consumption of this stage (0.5 ÷ 1W). There is no compliance issue in that because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load.To do so, the device provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst-mode operation. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in Figure 26 When the L6599 is in UVLO the pin is kept open, to let the PFC controller start first.RF max 38--RF min f maxf min----------1–--------------------?=。