FPGA 控制舵机程序
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FPGA 控制舵机程序（verilog）
module PWM(clk,pwm1,jiaodu);
input clk;
input[7:0] jiaodu;
output pwm1;
reg pwm1;
reg[32:0] counter;
reg[32:0] counter1;
always@(posedge clk)
begin
counter = counter + 1;
if(counter ==32'd5000) // 50MHz 0.1ms
begin
counter = 0;
counter1= counter1 + 1;
end
if(counter1 == 8'd1)
pwm1 <= 1;
else if(counter1 ==jiaodu)
pwm1 <= 0;
else if (counter1 == 16'd200)
counter1=0;
end
endmodule
例化可控制三个舵机
`include"PWM.v"
module PWM1(clk,pwm3);
input clk;
output[2:0] pwm3;
//reg pwm2;
parameter jiaodu1 = 8'd10;
parameter jiaodu2 = 8'd15;
parameter jiaodu3 = 8'd20;
PWM a1(clk,pwm3[0],jiaodu1);
PWM a2(clk,pwm3[1],jiaodu2);
PWM a3(clk,pwm3[2],jiaodu3);
endmodule
