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MESC-PM4中文资料

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Features

- Adjunct device to the Lucent ATM Port Controller (APC version 3b) in ORCA 3T FPGA- PM function can be carried out anywhere in the connection- Extends the functionnality already available within the APC- Directly connected to the Transmit ESI Interface of a single APC- Maintain a different set of per VC statistics for up to 32 connections simultaneously

• Ingress Received Cell Blocks (for convenience called - Stat 0)

• Ingress Severely Errored Cell Blocks (Bellcore GR1248 PM - Stat A)

• Ingress CLP0+1 Errored Cells (Bellcore GR1248 PM - Stat B)

• Ingress Lost CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat C)

• Ingress Misinserted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat E)

• Ingress Total Transmitted CLP0+1 User Information Cells (Bellcore GR1248 PM - Stat F)

- Handle four Block size type per channel : 128, 256, 512 and 1024 cells- Handle independant threshold for Lost, Misinserted and Errored statistics- Simple CPU interface with Ready signal- Available in VHDL source code format for ease of customization- Can be customised by Logic Design Solutions

General Description

The MESC_PM4 function, implemented on a ORCA FPGA, is to extend the functionnality already available within the APC.L.D.S. can integrate your decoding logic in the FPGA in addition to any other predesigned functions.

Design PackageDevice FamilyORCA 3T30-6-S208

PFUs 176 – 90% used *

I/O64 **

1Bitstream + Data Sheet

Package file options2VHDL Source codeVHDL Test Bench for behavioural and gate level simulation.Data SheetUser’s guide : Simulation, Synthesis and Place and Route procedures.Constraint Files : « .prf » file

Design Tool UsedVHDL synthesis Leonardo Spectrum from Exemplar.VHDL ModelSim simulation tool from ModelTech.ORCA Foundry from Lucent Technologies.

SupportSupport provided by Logic Design Solutions 90 days e-mail and telephone supportfrom Logic Design Solutions included in the Macro price. Support does not cover userMacro modifications. Maintenance Contracts available.

* Synthesis option dependant (area/speed)** Assuming all Macro signals are routed off chip.Data Sheet

August. 2000 – Ver. 3MESC-PM4

Enhanced Services Controller MACRO

Performance Monitor - 32 Connections元器件交易网www.cecb2b.com August 2000MESC_PM4 MACRO

Data Sheet Logic Design Solutions

2/151.Description................................................................................................................................................................................................3

1.1Implementation example....................................................................................................................................................................3

1.2Symbol...................................................................................................................................................................................................3

1.3Pin Description...................................................................................................................................................................................4

1.4Functionnal Description....................................................................................................................................................................4

1.5E.S.I. interface.....................................................................................................................................................................................5

1.6Performance Monitor Register........................................................................................................................................................61.6.1Register Address Map.............................................................................................................................................................61.6.2Registers.....................................................................................................................................................................................61.6.2.1Connection memory............................................................................................................................................................61.6.2.2Error Threshold Divider Register......................................................................................................................................71.6.2.3Lost Threshold Divider Register.......................................................................................................................................71.6.2.4Misinserted Threshold Divider Register..........................................................................................................................81.6.2.5Connection Counter Read Request Register...................................................................................................................91.6.2.6Stat. 0 read register..............................................................................................................................................................91.6.2.7Stat. A read register.............................................................................................................................................................91.6.2.8Stat. B read register...........................................................................................................................................................101.6.2.9Stat. C read register...........................................................................................................................................................101.6.2.10Stat. E read register......................................................................................................................................................101.6.2.11Stat. F read register......................................................................................................................................................111.6.2.12Status Interupt register................................................................................................................................................11

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MEMORY存储芯片MTFC8GAKAJCN-4M IT中文规格书

MEMORY存储芯片MTFC8GAKAJCN-4M IT中文规格书

Block Lock Feature

The block lock feature protects either the entire device or ranges of blocks from being

programmed and erased. Using the block lock feature is preferable to using WP# to pre-

vent PROGRAM and ERASE operations.

Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if

LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at

power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on

the device are protected, or locked, from PROGRAM and ERASE operations, even if WP#

is HIGH.

Before the contents of the device can be modified, the device must first be unlocked.

Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE

operations complete successfully only in the block ranges that have been unlocked.

Blocks, once unlocked, can be locked again to protect them from further PROGRAM

MT4LC4M16R6资料

MT4LC4M16R6资料

14 Meg x 16 EDO DRAMMicron Technology, Inc., reserves the right to change products or specifications without notice.D29_C.p65 – Rev. 2/01©2001, Micron Technology, Inc.4 MEG x 16EDO DRAM

FEATURES

•Single +3.3V ±0.3V power supply

•Industry-standard x16 pinout, timing, functions,

and package

•12 row, 10 column addresses (R6)

13 row, 9 column addresses (N3)

•High-performance CMOS silicon-gate process

•All inputs, outputs and clocks are LVTTL-compatible

•Extended Data-Out (EDO) PAGE MODE access

•4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

•Optional self refresh (S) for low-power data

retention

OPTIONSMARKING

•Plastic Package

50-pin TSOP (400 mil)TG

•Timing

50ns access-5

60ns access-6

•Refresh Rates

4KR6

8KN3

Standard RefreshNone

Self RefreshS*

•Operating Temperature Range

Commercial (0°C to +70°C)None

NOTE:1.The “#” symbol indicates signal is active LOW.

Cortex-M4内核资料

Cortex-M4内核资料

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P4C22-15PMB中文资料

P4C22-15PMB中文资料

1P4C422FEATURES

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25/35 ns (Commercial)– 15/20/25 /35 ns (Military)CMOS for Low Power– 495 mW Max. – 10/12/15/20/25 (Commercial)

– 495 mW Max. – 15/20/25/35 (Military)

DESCRIPTION

The P4C422 is a 1,024-bit high-speed (10ns) Static RAM

with a 256 x 4 organization. The memory requires no

clocks or refreshing and has equal access and cycle

times. Inputs and outputs are fully TTL compatible.

Operation is from a single 5 Volt supply. Easy memory

expansion is provided by an active LOW chip select one

(CS1) and active HIGH chip select two (CS2) as well as 3-

state outputs.P4C422

ULTRA HIGH SPEED 256 x 4

STATIC CMOS RAM

Means Quality, Service and Speed

1Q97元器件交易网 P4C422元器件交易网P4C422

minimum write recovery times by eliminating the “write

recovery glitch.” Reading is performed with chip selct one