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MC100LVEP11DG资料

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© Semiconductor Components Industries, LLC, 2006December, 2006 − Rev. 111Publication Order Number:MC10LVEP11/DMC10LVEP11, MC100LVEP11

2.5V / 3.3V󰀁ECL 1:2

Differential Fanout Buffer

DescriptionThe MC10/100LVEP11 is a differential 1:2 fanout buffer. Thedevice is pin and functionally equivalent to the EP11 device. With ACperformance the same as the EP11 device, the LVEP11 is ideal forapplications requiring lower voltage. Single−ended CLK inputoperation is limited to a VCC w 3.0 V in PECL mode, or VEE v−3.0 V in NECL mode.The 100 Series contains temperature compensation.

Features•240 ps Typical Propagation Delay•Maximum Frequency > 3.0 GHz Typical•PECL Mode Operating Range: VCC = 2.375 V to 3.8 Vwith VEE = 0 V•NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V•Open Input Default State•Q Output Will Default LOW with Inputs Open or at VEE•LVDS Input Compatible•Pb−Free Packages are Available

*For additional marking information, refer to Application Note AND8002/D.H= MC10A= Assembly LocationK= MC100L= Wafer Lot5X= MC10Y= Year4K= MC100W= Work WeekM= Date CodeG= Pb−Free PackageALYWGGHU11ALYWGGKU11MARKINGDIAGRAMS*

SOIC−8D SUFFIXCASE 751

TSSOP−8DT SUFFIXCASE 948R18

18

18

See detailed ordering and shipping information in the packagedimensions section on page 8 of this data sheet.ORDERING INFORMATIONhttp://onsemi.com

18HVP11ALYWG18KVP11ALYWG18

DFN8MN SUFFIXCASE 506AA5X MGG

14

(Note: Microdot may be in either location)4K MGG

14元器件交易网www.cecb2b.comMC10LVEP11, MC100LVEP11

http://onsemi.com2

1

2

3

45678

D

VEEVCC

Q0

DQ1

Q1Q0

Figure 1. 8−Lead Pinout (Top View) and Logic

DiagramTable 1. PIN DESCRIPTION

PINFUNCTION

D*, D**ECL Data Inputs

Q0, Q0, Q1, Q1ECL Data Outputs

VCCPositive Supply

VEENegative Supply

EPExposed pad must be connected to asufficient thermal conduit. Electricallyconnect to the most negative supply orleave floating open.

*Pins will default to 2/3 VCC when left open.**Pins will default LOW when left open.

Table 2. ATTRIBUTESCharacteristicsValue

Internal Input Pulldown Resistor75 kW

Internal Input Pullup Resistor37.5 kW

ESD ProtectionHuman Body ModelMachine ModelCharged Device Model> 4 kV> 200 V> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)Level 1

Flammability RatingOxygen Index: 28 to 34UL 94 V−0 @ 0.125 in

Transistor Count110 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1.For additional information, see Application Note AND8003/D.元器件交易网www.cecb2b.comMC10LVEP11, MC100LVEP11

http://onsemi.com3Table 3. MAXIMUM RATINGSSymbolParameterCondition 1Condition 2RatingUnit

VCCPECL Mode Power SupplyVEE = 0 V6V

VEENECL Mode Power SupplyVCC = 0 V−6V

VIPECL Mode Input VoltageNECL Mode Input VoltageVEE = 0 VVCC = 0 VVI v VCCVI w VEE6−6VV

IoutOutput CurrentContinuousSurge50100mAmA

TAOperating Temperature Range−40 to +85°C

TstgStorage Temperature Range−65 to +150°C

qJAThermal Resistance (Junction−to−Ambient)0 lfpm500 lfpmSOIC−8SOIC−8190130°C/W°C/WqJCThermal Resistance (Junction−to−Case)Standard BoardSOIC−841 to 44°C/W

qJAThermal Resistance (Junction−to−Ambient)0 lfpm500 lfpmTSSOP−8TSSOP−8185140°C/W°C/WqJCThermal Resistance (Junction−to−Case)Standard BoardTSSOP−841 to 44°C/W

qJAThermal Resistance (Junction−to−Ambient)0 lfpm500 lfpmDFN8DFN812984°C/W°C/W

TsolWave SolderPbPb−Free<2 to 3 sec @ 248°C<2 to 3 sec @ 260°C265265°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.元器件交易网www.cecb2b.comMC10LVEP11, MC100LVEP11

http://onsemi.com4Table 4. 10LVEP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2)

SymbolCharacteristic−40°C25°C85°C

UnitMinTypMaxMinTypMaxMinTypMax

IEEPower Supply Current253340293340323442mA

VOHOutput HIGH Voltage (Note 3)136514901615143015551680149016151740mV

VOLOutput LOW Voltage (Note 3)565740865630805930690865990mV

VIHCMRInput HIGH Voltage Common ModeRange (Differential Configuration)(Note 4)1.22.51.22.51.22.5V

IIHInput HIGH Current150150150mA

IILInput LOW CurrentDD0.5−1500.5−1500.5−150mA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declaredoperating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.2.Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.3.All loading with 50 W to VCC − 2.0 V.4.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal. Single−Ended input CLK pin operation is limited to VCC w 3.0 V in PECL mode.

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MC100EL51中文资料

MC100EL51中文资料

MOTOROLASEMICONDUCTOR TECHNICAL DATA

3–1REV 2© Motorola, Inc. 199612/93Differential Clock D FlipĆFlop

The MC10EL/100EL51 is a differential clock D flip-flop with reset. Thedevice is functionally similar to the E151 device with higher performancecapabilities. With propagation delays and output transition timessignificantly faster than the E151 the EL51 is ideally suited for thoseapplications which require the ultimate in AC performance.The reset input is an asynchronous, level triggered signal. Data entersthe master portion of the flip-flop when the clock is LOW and istransferred to the slave, and thus the outputs, upon a positive transition ofthe clock. The differential clock inputs of the EL51 allow the device to beused as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability underopen input (pulled down to VEE) conditions.

MC100EP101FAR2G,MC10EP101FAR2G,MC100EP101MNR4G,MC10EP101MNR4G,MC10EP101MNG, 规格书,Datasheet 资料

MC100EP101FAR2G,MC10EP101FAR2G,MC100EP101MNR4G,MC10EP101MNR4G,MC10EP101MNG, 规格书,Datasheet 资料

© Semiconductor Components Industries, LLC, 2006November, 2006 − Rev. 111Publication Order Number:MC10EP101/DMC10EP101, MC100EP101

3.3V / 5V󰀁ECL Quad 4−Input

OR/NOR

DescriptionThe MC10/100EP101 is a Quad 4−input OR/NOR gate. The deviceis functionally equivalent to the E101. With AC performance fasterthan the E101 device, the EP101 is ideal for applications requiring thefastest AC performance available.The 100 Series contains temperature compensation.

Features•250 ps Typical Propagation Delay•Maximum Frequency > 3 GHz Typical•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V•NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V•Open Input Default State•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.

MC100ELT21D中文资料

MC100ELT21D中文资料

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–1REV 3© Motorola, Inc. 19967/96Differential PECL to TTL

Translator

The MC10ELT/100ELT21 is a differential PECL to TTL translator.Because PECL (Positive ECL) levels are used only +5V and ground arerequired. The small outline 8-lead SOIC package and the single gate ofthe ELT21 makes it ideal for those applications where space,performance and low power are at a premium. Because the matureMOSAIC 1.5 process is used, low cost can be added to the list offeatures.The VBB output allows the ELT21 to also be used in a single-endedinput mode. In this mode the VBB output is tied to the IN input for anon-inverting buffer or the IN input for an inverting buffer. If used the VBBpin should be bypassed to ground via a 0.01µF capacitor.The ELT21 is available in both ECL standards: the 10ELT is compatiblewith positive MECL 10H logic levels while the 100ELT is compatible withpositive ECL 100K logic levels.

mc100ept21 -d 3.3v差分lvpecl lvds cml到lvttl lvcmos转换

mc100ept21 -d 3.3v差分lvpecl lvds cml到lvttl lvcmos转换

© Semiconductor Components Industries, LLC, 2012September, 2012 − Rev. 221Publication Order Number:MC100EPT21/DMC100EPT21

3.3V Differential

LVPECL/LVDS/CML to

LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML toLVTTL/LVCMOS translator. Because LVPECL (Positive ECL),LVDS, and positive CML input levels and LVTTL/LVCMOS outputlevels are used, only +3.3 V and ground are required. The smalloutline 8−lead SOIC package makes the EPT21 ideal for applicationswhich require the translation of a clock or data signal.The VBB output allows this EPT21 to be cap coupled in eithersingle−ended or differential input mode. When single−ended capcoupled, VBB output is tied to the D input and D is driven for anon−inverting buffer, or VBB output is tied to the D input and D isdriven for an inverting buffer. When cap coupled differentially, VBBoutput is connected through a resistor to each input pin. If used, theVBB pin should be bypassed to VCC via a 0.01 mF capacitor. Foradditional information see AND8020/D. For a single−ended directconnection use an external voltage reference source such as a resistordivider. Do not use VBB for a single−ended direct connection or port toanother device.