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GS8170DW72AC-300中文资料

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GS8170DW36/72AC-350/333/300/25018Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™250 MHz–350 MHz1.8 V V DD 1.8 V I/O209-Bump BGA Commercial Temp Industrial Temp Features• Double Late Write mode, Pipelined Read mode• JEDEC-standard SigmaRAM ™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface• ZQ controlled user-selectable output drive strength • Dual Cycle Deselect• Burst Read and Write option• Fully coherent read and write pipelines• Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes)• 2 user-programmable chip enable inputs• IEEE 1149.1 JTAG-compliant Serial Boundary Scan• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices• Pb-Free 209-bump BGA package availableSigmaRAM Family OverviewGS8170DW 36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.ΣRAMs are offered in a number of configurations includingLate Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to writecueing and data transfer rates. The ΣRAM ™ family standard allows a user to implement the interface protocol best suited to the task at hand.Functional DescriptionBecause SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. ΣRAMs support pipelined reads utilizing a rising-edge-triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol.ΣRAMs are implemented with high performance CMOStechnology and are packaged in a 209-bump BGA.209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump ArrayBottom ViewParameter SynopsisKey Fast Bin SpecsSymbol - 350Cycle Time tKHKH 2.86 ns Access TimetKHQV1.7 nsGS8170DW36/72AC-350/333/300/250SigmaRAM Pinouts256K x 72 Common I/O—Top View (Package C)1234567891011A DQg DQg A E2A ADV A E3A DQb DQbB DQg DQg Bc Bg NC W A Bb Bf DQb DQbC DQg DQg Bh Bd NC(144M)E1NC Be Ba DQb DQbD DQg DQg V SS NC NC MCL NC NC V SS DQb DQbE DQg DQc V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQf DQbF DQc DQc V SS V SS V SS ZQ V SS V SS V SS DQf DQfG DQc DQc V DDQ V DDQ V DD EP2V DD V DDQ V DDQ DQf DQfH DQc DQc V SS V SS V SS EP3V SS V SS V SS DQf DQfJ DQc DQc V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQf DQf K CQ2CQ2CK NC V SS MCL V SS NC NC CQ1CQ1 L DQh DQh V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQa M DQh DQh V SS V SS V SS MCL V SS V SS V SS DQa DQa N DQh DQh V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQa P DQh DQh V SS V SS V SS MCL V SS V SS V SS DQa DQa R DQd DQh V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQa DQe T DQd DQd V SS NC NC MCL NC NC V SS DQe DQeU DQd DQd NC A NC(72M)A NC(36M)A NC DQe DQeV DQd DQd A A A A1A A A DQe DQe W DQd DQd TMS TDI A A0A TDO TCK DQe DQe • 2002.0611 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch• Note:Users of CMOS I/O SigmaRAMs may wish to connect “NC, V REF” and the “NC, CK” pins to V REF (i.e., V DDQ/2) to allow alternate use of future HSTL I/O SigmaRAMs.GS8170DW36/72AC-350/333/300/250512K x 36 Common I/O—Top View (Package C)1234567891011A NC NC A E2A ADV A E3A DQb DQbB NC NC Bc NC A W A Bb NC DQb DQbC NC NC NC Bd NC(144M)E1NC NC Ba DQb DQbD NC NC V SS NC NC MCL NC NC V SS DQb DQbE NC DQc V DDQ V DDQ V DD V DD V DD V DDQ V DDQ NC DQbF DQc DQc V SS V SS V SS ZQ V SS V SS V SS NC NCG DQc DQc V DDQ V DDQ V DD EP2V DD V DDQ V DDQ NC NCH DQc DQc V SS V SS V SS EP3V SS V SS V SS NC NCJ DQc DQc V DDQ V DDQ V DD MCH V DD V DDQ V DDQ NC NCK CQ2CQ2CK NC V SS MCL V SS NC NC CQ1CQ1L NC NC V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQaM NC NC V SS V SS V SS MCL V SS V SS V SS DQa DQaN NC NC V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQa DQaP NC NC V SS V SS V SS MCL V SS V SS V SS DQa DQaR DQd NC V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQa NCT DQd DQd V SS NC NC MCL NC NC V SS NC NCU DQd DQd NC A NC(72M)A NC(36M)A NC NC NCV DQd DQd A A A A1A A A NC NC W DQd DQd TMS TDI A A0A TDO TCK NC NC • 2002.0611 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch• Note:Users of CMOS I/O SigmaRAMs may wish to connect “NC, V REF” and the “NC, CK” pins to V REF (i.e., V DDQ/2) to allow alternate use of future HSTL I/O SigmaRAMs.GS8170DW36/72AC-350/333/300/250Operation ControlAll address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.Pin Description Table SymbolDescriptionTypeCommentsA Address Input —ADV Advance Input Active High Bx Byte Write Enable Input Active Low W Write Enable Input Active Low E1Chip Enable Input Active LowE2 & E3Chip Enable Input Programmable Active High or Low EP2 & EP3Chip Enable Program PinMode Input To be tied directly to V DD , V DDQ or V SSCK Clock Input Active HighCQ, CQ Echo Clock Output Three State - Deselect via E2 or E3 FalseDQ Data I/O Input/Output Three StateMCH Must Connect High Input Active HighTo be tied directly to V DD or V DDQMCLMust Connect LowInputActive LowTo be tied directly to V SS ZQ Output Impedance ControlMode Input Low = Low Impedance [High Drive]High = High Impedance [Low Drive]To be tied directly to V DDQ or V SSTCK Test Clock Input Active HighTDI Test Data In Input —TDO Test Data Out Output —TMS Test Mode Select Input —NC No Connect —Not connected to die or any other pinV DD Core Power Supply Input 1.8 V Nominal V DDQ Output Driver Power SupplyInput 1.8 V NominalV SSGroundInput—GS8170DW36/72AC-350/333/300/250Read OperationsPipelined ReadRead operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write OperationsWrite operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.Single Data Rate Pipelined ReadGS8170DW36/72AC-350/333/300/250Double Late WriteDouble Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline mode NBT SRAMs.Byte Write ControlThe Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.Example of x36 Byte Write Truth TableFunction W Ba Bb Bc Bd Read H X X X X Write Byte A L L H H H Write Byte B L H L H H Write Byte C L H H L H Write Byte D L H H H L Write all Bytes L L L L L Write AbortLHHHHSigmaRAM Double Late Write with Pipelined ReadGS8170DW36/72AC-350/333/300/250Two Byte Write Control Example with Double Late Write SigmaRAMSpecial FunctionsBurst CyclesAlthough SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance theinternal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.GS8170DW36/72AC-350/333/300/250SigmaRAM Pipelined Burst Reads with Counter Wrap-aroundGS8170DW36/72AC-350/333/300/250SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-aroundBurst OrderThe burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have been accessed. SigmaRAMs always count in linear burst order.Note:The burst counter wraps to initial state on the 5th rising edge of clock.Echo ClockSRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks.Linear Burst OrderA[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110GS8170DW36/72AC-350/333/300/250Programmable EnablesΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V DD , E2 functions as an active high enable. If EP2 is held to V SS , E2 functions as an active low chip enable input.Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four SRAMs can be made to look like one larger RAM to the system.Example Four Bank Depth Expansion Schematic—Σ1x1DpA CK E1E2E3W A 0–A nCK W DQ 0–DQ n Bank 0Bank 1Bank 2Bank 3Bank Enable Truth TableEP2EP3E2E3Bank 0V SS V SS Active Low Active Low Bank 1V SS V DD Active Low Active High Bank 2V DD V SS Active High Active Low Bank 3V DDV DDActive HighActive HighE1A n – 1A nA 0–A n – 2A n – 1A nA 0–A n – 2A n – 1A nA 0–A n – 2A n – 1A nA 0–A n – 2DQ A CK E2E3W DQ A CK E2E3W DQ A CK E2E3WDQ E1E1E1CQCQCQCQCQEP2EP300EP2EP310EP2EP301EP2EP311GS8170DW36/72AC-350/333/300/250It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks.In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming readoperations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.Echo Clock Control in Two Banks of SigmaRAMsGS8170DW36/72AC-350/333/300/250.CMOS Output Driver Impedance ControlCMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point applications.Pipelined Read Bank Switch with E1 DeselectGS8170DW36/72AC-350/333/300/250Double Late Write, Pipelined Read Truth Table CK E1(t n )E (t n )ADV (t n )W (t n )B (t n)PreviousOperationCurrent OperationDQ/CQ (t n )DQ/CQ (t n+1)DQ/CQ (t n+2)0→1X F 0X X X Bank Deselect ***/***Hi-Z/Hi-Z ---0→1X X 1X X Bank DeselectBank Deselect (Continue)Hi-Z/Hi-Z Hi-Z/Hi-Z ---0→11T 0X X X Deselect ***/***Hi-Z/CQ ---0→1XX1XXDeselectDeselect (Continue)Hi-Z/CQHi-Z/CQ---0→10T 00T X WriteLoads new address Stores DQx if Bx = 0***/******/***D1/CQ0→10T 00F X Write (Abort)Loads new address No data stored ***/******/***Hi-Z/CQ0→1X X 1X T Write Write Continue Increments address by 1Stores DQx if Bx = 0***/***Dn-1/CQ Dn/CQ0→1X X 1X F Write Write Continue (Abort)Increments address by 1No data stored ***/***Dn-1/CQ Hi-Z/CQ0→10T 01X X ReadLoads new address ***/***Q1/CQ ---0→1X X 1X X Read Read Continue Increments address by 1Qn-1/CQ Qn/CQ ---Notes:1.If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.2.If one or more Bx = 0, then B = “T” else B = “F”.3.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.4.“***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.5. “---” indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.6.DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.7.CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.8.Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct piecesof data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-nal (base) address.GS8170DW36/72AC-350/333/300/250Common I/O State DiagramNotes:1.The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.2.If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.3.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.DeselectBank DeselectReadRead WriteWrite ContinueX,F,0,X or X,X,1,XContinueX,F,0,X1,T,0,XX,F,0,X1,T,0,X1,T,0,XX,F,0,X1,T,0,X 1,T,0,X or X,X,1,X0,T,0,00,T,0,10,T,0,00,T,0,1X,F,0,XX,F,0,X0,T,0,00,T,0,1X,X,1,XX,X,1,X0,T,0,00,T,0,11,T,0,X 0,T,0,00,T,0,1X,X,1,XX,X,1,X0,T,0,10,T,0,0Clock (CK)CommandCurrent StateNext StateƒƒƒƒCurrent State & Next State Definition for Read /Write Control State DiagramCurrent State (n)Next State (n + 1)TransitionƒInput Command CodeKeyn n+1n+2n+3GS8170DW36/72AC-350/333/300/250Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.Recommended Operating ConditionsAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.5V V DDQ Voltage in V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ + 0.5 (≤ 2.5 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ + 0.5 (≤ 2.5 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o CT STGStorage Temperature–55 to 125ºCPower SuppliesParameterSymbolMin.Typ.Max.UnitNotesSupply Voltage V DD 1.7 1.8 1.95V 1.8 V I/O Supply Voltage V DDQ 1.7 1.8V DD V Ambient Temperature (Commercial Range Versions)T A 02570°C 1Ambient Temperature (Industrial Range Versions)T A–402585°C1Note:The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.CMOS I/O DC Input CharacteristicsParameterSymbolMin.Typ.Max.UnitNotesCMOS Input High Voltage V IH 0.65 * V DDQ—V DDQ + 0.3V 1CMOS Input Low VoltageV IL–0.3—0.35 * V DDQV1Note: For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.GS8170DW36/72AC-350/333/300/250Note:This parameter is sample tested.AC Test Load DiagramCapacitance(T A = 25o C, f = 1 MH Z , V DD = 1.8 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output CapacitanceC OUTV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /220% tKCV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 1.0 V50%V DDV ILDQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)GS8170DW36/72AC-350/333/300/250Input and Output Leakage CharacteristicsParameter Symbol Test Conditions Min.Max Notes Input Leakage Current(except mode pins)I IL V IN = 0 to V DDQ–2 uA 2 uA—ZQ, MCH, MCL, EP2, EP3Pin Input CurrentI INM V IN = 0 to V DDQ–50 uA50 uA—Output Leakage Current I OLOutput Disable,V OUT = 0 to V DDQ–2 uA 2 uA—Selectable Impedance Output Driver DC Electrical CharacteristicsParameter Symbol Test Conditions Min.Max Notes Low Drive Output High Voltage V OHL I OHL = –4 mA V DDQ – 0.4 V—1 Low Drive Output Low Voltage V OLL I OLL = 4 mA—0.4 V1 High Drive Output High Voltage V OHH I OHH = –8 mA V DDQ – 0.4 V—2 High Drive Output Low Voltage V OLH I OLH = 8 mA—0.4 V2 Notes:1.ZQ = 1; High Impedance output driver setting2.ZQ = 0; Low Impedance output driver settingGS8170DW36/72AC-350/333/300/250Operating CurrentsParameterSymbol-350-333-300-250Test Conditions0°C to 70°C–40°C to +85°C0°C to 70°C–40°C to +85°C0°C to 70°C–40°C to +85°C0°C to 70°C–40°C to +85°COperating Currentx72I DDP (PL)365 mA 375 mA 345 mA 355 mA 320 mA 330 mA 275 mA 285 mA E1 ≤ V IL HKH ≥ tKHKH Min.All other inputs V IL ≥ V IN ≥ V IH x36I DDP (PL)265 mA 275 mA 245 mA 255 mA 225 mA 235 mA 200 mA 210 mA Chip Disable Currentx72I SB1 (PL)80 mA 90 mA 75 mA 85 mA 70 mA 80 mA 65 mA 75 mA E1 ≥ V IH Min. or tKHKH ≥ tKHKH Min.All other inputs V IL ≥ V IN ≥ V IH x36I SB1 (PL)75 mA 85 mA 70 mA 80 mA 65 mA 75 mA 60 mA 70 mA Bank Deselect Currentx72I SB2 (PL)80 mA 90 mA 75 mA 85 mA 70 mA 80 mA 65 mA 75 mA E2 or E3 False tKHKH ≥ tKHKH Min.All other inputs V IL ≥ V IN ≥ V IH x36I SB2 (PL)75 mA85 mA70 mA80 mA65 mA75 mA60 mA70 mACMOS Deselect CurrentI DD345 mA 55 mA 45 mA 55 mA 45 mA 55 mA 45 mA 55 mADevice DeselectedAll inputs V SS + 0.10 V ≥ V IN ≥V DD – 0.10 VGS8170DW36/72AC-350/333/300/250AC Electrical CharacteristicsParameterSymbol-350-333-300-250UnitNotesMin Max Min Max Min Max Min Max Clock Cycle Time tKHKH 2.86— 3.0— 3.3— 4.0—ns —Clock High Time tKHKL 1.0— 1.2— 1.3— 1.6—ns —Clock Low Time tKLKH 1.0— 1.2— 1.3— 1.6—ns —Clock High to Echo Clock Low-Z tKHCX10.5—0.5—0.5—0.5—ns 2Clock High to Echo Clock High tKHCH — 1.7— 1.8 1.8— 2.1ns —Clock Low to Echo Clock Low tKLCL — 1.7— 1.8 1.8— 2.1ns Clock High to Echo Clock High-Z tKHCZ — 1.7— 1.8 1.8— 2.1ns 1, 2 Clock High to Output Low-Z tKHQX10.5—0.5—0.5—0.5—ns 1 Clock High to Output Valid tKHQV — 1.7— 1.8 1.8— 2.1ns — Clock High to Output Invalid tKHQX 0.5—0.5—0.5—0.5—ns —Clock High to Output High-Z tKHQZ — 1.7— 1.8 1.8— 2.1ns 1Echo Clock High to Output Valid tCHQV —0.35—0.35—0.38—0.45ns 2Echo Clock High to Output Invalid tCHQX –0.35—–0.35—–0.38—–0.45—ns 2Address Valid to Clock High tAVKH 0.4—0.6—0.7—0.8—ns —Clock High to Address Don’t Care tKHAX 0.4—0.4—0.4—0.5—ns —Enable Valid to Clock High tEVKH 0.4—0.6—0.7—0.8—ns —Clock High to Enable Don’t Care tKHEX 0.4—0.4—0.4—0.5—ns —Write Valid to Clock High tWVKH 0.4—0.6—0.7—0.8—ns —Clock High to Write Don’t Care tKHWX 0.4—0.4—0.4—0.5—ns —Byte Write Valid to Clock High tBVKH 0.4—0.6—0.7—0.8—ns —Clock High to Byte Write Don’t CaretKHBX 0.4—0.4—0.4—0.5—ns —Data In Valid to Clock High tDVKH 0.4—0.5—0.5—0.5—ns —Clock High to Data In Don’t CaretKHDX 0.4—0.4—0.4—0.5—ns —ADV Valid to Clock High tadvVKH 0.4—0.6—0.7—0.8—ns —Clock High to ADV Don’t CaretKHadvX0.4—0.4—0.4—0.5—ns—Notes:1.Measured at 100 mV from steady state. Not 100% tested.2.Guaranteed by design. Not 100% tested.3.For any specific temperature and voltage tKHCZ < tKHCX1.GS8170DW36/72AC-350/333/300/250Timing Parameter Key—Pipelined Read Cycle TimingtKHQXtKHQZ tKHQX1tKHQV tAVKHtKHAXCKADQ (Data Out)tKHKHtKLKHtKHKLC DEQBCQtCHQVtKHCH tKHCX1tKHCZ= CQ High ZtCLCHtCHCLtCHQXGS8170DW36/72AC-350/333/300/250Timing Parameter Key—Double Late Write Mode Control and Data In TimingJTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.tKHnXtnVKHtAVKHtKHAXCKAA BCE1, E2, E3, W, Bx, ADVtKHDXtDVKHDADQ (Data In)Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.GS8170DW36/72AC-350/333/300/250JTAG Port Registers OverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCKTest ClockInClocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMS Test Mode Select InThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.Note:This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS8170DW36/72AC-350/333/300/250JTAG TAP Block DiagramIdentification (ID) RegisterThe ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put inCapture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.Instruction RegisterID Code RegisterBoundary Scan Register120····313029120Bypass RegisterTDITDOTMS TCKTest Access Port (TAP) Controller108·1·········Control Signals·。

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BTS724G中文资料

BTS724G中文资料

?providingembeddedprotectivefunctionsapplications??ccompatiblehighsidepowerswitchwithdiagnosticfeedbackfor12vand24vgroundedloads?alltypesofresistiveinductiveandcapacitveloads?mostsuitableforloadswithhighinrushcurrentssoaslamps?replaceselectromechanicalrelaysfusesanddiscretecircuitsbasicfunctions?verylowstandbycurrent?cmoscompatibleinput?improvedelectromagneticcompatibilityemc?fastdemagnetizationofinductiveloads?stablebehaviouratundervoltage?wideoperatingvoltagerange?logicgroundindependentfromloadgroundprotectionfunctionsblockdiagram?shortcircuitprotection?overloadprotection?currentlimitation?thermalshutdown?overvoltageprotectionincludingloaddumpwithexternalresistor?reversebatteryprotectionwithexternalresistor?lossofgroundandlossofvbbprotection?electrostaticdischargeprotectionesddiagnosticfunction?diagnosticfeedbackwithopendrainoutput?openloaddetectioninoffstate?feedbackofthermalshutdowninonstatepdso20vbblogicchannel3channel4gndload1load2logicchannel1channel2load4load3in1st12in2in3st34in4bts724ginfineontechnol
广州晟通光电有限公司 OP817B 光电转换器数据手册说明书

广州晟通光电有限公司 OP817B 光电转换器数据手册说明书

Dimensions: [mm]121Scale - 3:1Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg Germany140817140210Würth Elektronik eiSos GmbH & Co. KGEMC & Inductive Solutions140817140210 Max-Eyth-Str. 174638 WaldenburgGermanyTotal Power Dissipation vs. Ambient Temperature:20406080100120140160-55-35-15525456585105125IR-diode -I F(mA)Ambient Temperature (°C)Phototransistor-PO(mW)CollectorPowerDissipation(mW)ForwardCurrent(mA)Collector Dark Current vs. Ambient Temperature:11010010001000025456585105125CollectorDarkCurrent(nA)Ambient Temperature (°C)V CE= 20VV CE= 10VNote: measured with Bin BWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive SolutionsMax-Eyth-Str. 174638 WaldenburgGermanyCHECKED REVISION DATE (YYYY-MM-DD)GENERAL TOLERANCE PROJECTIONMETHODSaVo001.0052023-08-22DIN ISO 2768-1mDESCRIPTIONWL-OCPT OptocouplerPhototransistor ORDER CODE140817140210SIZE/TYPE BUSINESS UNIT STATUS PAGEAbsolute CTR vs. Ambient Temperature50100150200250300-60-40-20020406080100120AbsoluteCTRAmbient Temperature (°C)V CE= 5VV CE= 0,4VTestcondition: I F=5mA, T A=25°C, Bin BRelative CTR vs. Ambient Temperature:0,40,60,811,21,4-60-40-20020406080100120RelativeCTRAmbient Temperature (°C)V CE= 5VV CE= 0,4VTestcondition: I F=5mA, Normalized to T A=25°C, Bin BWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive SolutionsMax-Eyth-Str. 174638 WaldenburgGermanyCHECKED REVISION DATE (YYYY-MM-DD)GENERAL TOLERANCE PROJECTIONMETHODSaVo001.0052023-08-22DIN ISO 2768-1mDESCRIPTIONWL-OCPT OptocouplerPhototransistor ORDER CODE140817140210SIZE/TYPE BUSINESS UNIT STATUS PAGEWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive Solutions140817140210 Max-Eyth-Str. 174638 WaldenburgGermanyWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive Solutions140817140210 Max-Eyth-Str. 174638 WaldenburgGermany050100150200250300350400450A b s o l u t e C T R (%)Testcondition T A Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg Germany140817140210050100150200250300A b s o l u t e C T R (%)Testcondition T A Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg Germany1408171402100102030R e s p o n s e T i m e (µs )Testcondition I C Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg Germany140817140210Würth Elektronik eiSos GmbH & Co. KGEMC & Inductive Solutions140817140210 Max-Eyth-Str. 174638 WaldenburgGermanyWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive Solutions140817140210 Max-Eyth-Str. 174638 WaldenburgGermanyT e m p e r a t u r eT T T Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg Germany140817140210Cautions and Warnings:The following conditions apply to all goods within the product series of Optoelectronic Components of Würth Elektronik eiSos GmbH & Co. KG:General:•This optoelectronic component is designed and manufactured for use in general electronic equipment.•Würth Elektronik must be asked for written approval (following the PPAP procedure) before incorporating the components into any equipment in fields such as military, aerospace, aviation, nuclear control, submarine, transportation (automotive control, train control,ship control), transportation signal, disaster prevention, medical, public information network, etc. where higher safety and reliability are especially required and/or if there is the possibility of direct damage or human injury.•Optoelectronic components that will be used in safety-critical or high-reliability applications, should be pre-evaluated by the customer. •The optoelectronic component is designed and manufactured to be used within the datasheet specified values. If the usage and operation conditions specified in the datasheet are not met, the wire insulation may be damaged or dissolved. •Do not drop or impact the components, the component may be damaged•Würth Elektronik products are qualified according to international standards, which are listed in each product reliability report. Würth Elektronik does not warrant any customer qualified product characteristics beyond Würth Elektroniks’ specifications, for its validity and sustainability over time.•The responsibility for the applicability of the customer specific products and use in a particular customer design is always within the authority of the customer. All technical specifications for standard products also apply to customer specific products.•Unless Würth Elektroik has given its express consent, the customer is under no circumstances entitled to reverse engineer, disassemble or otherwise attempt to extract knowledge or design information from the optoelectronic component.Product specific:Soldering:•The solder profile must comply with the technical product specifications. All other profiles will void the warranty. •All other soldering methods are at the customers’ own risk•The soldering pad pattern shown above is a general recommendation for the easy assembly of optoelectronic components. If a high degree of precision is required for the selected application (i.e. high density assembly), the customer must ensure that the soldering pad pattern is optimized accordingly.Cleaning and Washing:•Washing agents used during the production to clean the customer application might damage or change the characteristics of the optoelectronic component body, marking or plating. Washing agents may have a negative effect on the long-term functionality of the product.• Using a brush during the cleaning process may break the optoelectronic component body. Therefore, we do not recommend using a brush during the PCB cleaning process.Potting:•If the product is potted in the customer application, the potting material might shrink or expand during and after hardening. Shrinking could lead to an incomplete seal, allowing contaminants into the optoelectronic component body, pins or termination. Expansion could damage the components. We recommend a manual inspection after potting to avoid these effects.Storage Conditions:• A storage of Würth Elektronik products for longer than 12 months is not recommended. Within other effects, the terminals may suffer degradation, resulting in bad solderability. Therefore, all products shall be used within the period of 12 months based on the day of shipment.•Do not expose the optoelectronic component to direct sunlight.•The storage conditions in the original packaging are defined according to DIN EN 61760-2.•For a moisture sensitive component, the storage condition in the original packaging is defined according to IPC/JEDEC-J-STD-033. It is also recommended to return the optoelectronic component to the original moisture proof bag and reseal the moisture proof bag again. •The storage conditions stated in the original packaging apply to the storage time and not to the transportation time of the components.Packaging:•The packaging specifications apply only to purchase orders comprising whole packaging units. If the ordered quantity exceeds or is lower than the specified packaging unit, packaging in accordance with the packaging specifications cannot be ensured.Handling:•Violation of the technical product specifications such as exceeding the nominal rated current, will void the warranty. •The product design may influence the automatic optical inspection.•Certain optoelectronic component surfaces consist of soft material. Pressure on the top surface has to be handled carefully to prevent negative influence to the function and reliability of the optoelectronic components.•ESD prevention methods need to be applied for manual handling and processing by machinery. •Resistors for protection are obligatory.•In addition to optoelectronic components testing, products incorporating these devices have to comply with the safety precautions given in IEC 60825-1, IEC 62471 and IEC 62778.Technical specification:•The typical and/or calculated values and graphics of technical parameters can only reflect statistical figures. The actual parameters ofeach single product, may differ from the typical and/or calculated values or the typical characteristic line.Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg GermanyCHECKED REVISION DATE (YYYY-MM-DD)GENERAL TOLERANCEPROJECTION METHODSaVo001.0052023-08-22DIN ISO 2768-1mDESCRIPTIONWL-OCPT Optocoupler PhototransistorORDER CODE140817140210SIZE/TYPEBUSINESS UNITSTATUSPAGE•In the characteristics curves, all values given in dotted lines may show a higher deviation than the paramters mentioned above. •On each reel, only one bin is sorted and taped. The bin is defined on the current transfer ratio.•In order to ensure highest availability, the reel binning of standard deliveries can vary. A single bin cannot be ordered. Please contact us in advance, if you need a particular bin sorting before placing your order.•These cautions and warnings comply with the state of the scientific and technical knowledge and are believed to be accurate and reliable. However, no responsibility is assumed for inaccuracies or incompleteness.The customer has the sole responsibility to ensure that he uses the latest version of this datasheet, which is available on Würth Elektronik’s homepage. Unless otherwise agreed in writing (i.e. customer specific specification), changes to the content of this datasheet may occurwithout notice, provided that the changes do not have a significant effect on the usability of the optoelectronic components.Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 174638 Waldenburg GermanyCHECKED REVISION DATE (YYYY-MM-DD)GENERAL TOLERANCEPROJECTION METHODSaVo001.0052023-08-22DIN ISO 2768-1mDESCRIPTIONWL-OCPT Optocoupler PhototransistorORDER CODE140817140210SIZE/TYPEBUSINESS UNITSTATUSPAGEImportant NotesThe following conditions apply to all goods within the product range of Würth Elektronik eiSos GmbH & Co. KG:1. General Customer ResponsibilitySome goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding general suitability for certain application areas. These statements about suitability are based on our knowledge and experience of typical requirements concerning the areas, serve as general guidance and cannot be estimated as binding statements about the suitability for a customer application. The responsibility for the applicability and use in a particular customer design is always solely within the authority of the customer. Due to this fact it is up to the customer to evaluate, where appropriate to investigate and decide whether the device with the specific product characteristics described in the product specification is valid and suitable for the respective customer application or not.2. Customer Responsibility related to Specific, in particular Safety-Relevant ApplicationsIt has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the usual lifetime cannot be completely eliminated in the current state of the art, even if the products are operated within the range of the specifications.In certain customer applications requiring a very high level of safety and especially in customer applications in which the malfunction or failure of an electronic component could endanger human life or health it must be ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is caused to third parties in the event of malfunction or failure of an electronic component. Therefore, customer is cautioned to verify that data sheets are current before placing orders. The current data sheets can be downloaded at .3. Best Care and AttentionAny product-specific notes, cautions and warnings must be strictly observed. Any disregard will result in the loss of warranty.4. Customer Support for Product SpecificationsSome products within the product range may contain substances which are subject to restrictions in certain jurisdictions in order to serve specific technical requirements. Necessary information is available on request. In this case the field sales engineer or the internal sales person in charge should be contacted who will be happy to support in this matter.5. Product R&DDue to constant product improvement product specifications may change from time to time. As a standard reporting procedure of the Product Change Notification (PCN) according to the JEDEC-Standard inform about minor and major changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge should be contacted. The basic responsibility of the customer as per Section 1 and 2 remains unaffected.6. Product Life CycleDue to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of products. As a standard reporting procedure of the Product Termination Notification (PTN) according to the JEDEC-Standard we will inform at an early stage about inevitable product discontinuance. According to this we cannot guarantee that all products within our product range will always be available. Therefore it needs to be verified with the field sales engineer or the internal sales person in charge about the current product availability expectancy before or when the product for application design-in disposal is considered. The approach named above does not apply in the case of individual agreements deviating from the foregoing for customer-specific products.7. Property RightsAll the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas, development contracts as well as models or templates that are subject to copyright, patent or commercial protection supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG. Würth Elektronik eiSos GmbH & Co. KG does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, application, or process in which Würth Elektronik eiSos GmbH & Co. KG components or services are used.8. General Terms and ConditionsUnless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms and Conditions of Würth Elektronik eiSos Group”, last version available at .Würth Elektronik eiSos GmbH & Co. KGEMC & Inductive SolutionsMax-Eyth-Str. 174638 WaldenburgGermanyCHECKED REVISION DATE (YYYY-MM-DD)GENERAL TOLERANCE PROJECTIONMETHODSaVo001.0052023-08-22DIN ISO 2768-1mDESCRIPTIONWL-OCPT OptocouplerPhototransistor ORDER CODE140817140210SIZE/TYPE BUSINESS UNIT STATUS PAGE。

PG0703P_C02A 等产品的编程手册说明书

PG0703P_C02A 等产品的编程手册说明书

目录1. 远程控制概述 (1)1.1 如何远程控制 (1)1.2 通信协议 (3)1.3 远程控制功能 (5)2. SCPI简介 (10)2.1 命令格式 (10)2.2 符号说明 (10)2.3 参数类型 (11)2.4 命令缩写 (12)3. 模式共用命令 (13)3.1 IEEE公用命令子系统 (13)3.2 系统命令 (15)3.3 存储命令 (20)3.4 显示控制 (21)3.5 模式命令 (22)3.6 扫描命令 (22)4. 频谱分析模式 (24)4.1 仪器模式命令 (24)4.2 Initiate命令子系统 (24)4.3 Sense命令子系统 (25)4.4 Calculate命令系统 (43)4.5 Measurement命令系统 (58)4.6 触发 (72)4.7 TG (73)4.8 调制解调 (75)5. 矢量网络分析模式 (77)5.1 频率控制 (77)5.2 幅度控制 (78)5.3 带宽控制 (80)5.4 扫描控制 (80)5.5 TG (81)5.6 迹线 (81)5.7 光标 (85)6. 故障定点分析模式 (98)6.1 频率控制 (98)6.2 幅度控制 (99)6.3 扫描控制 (100)6.4 迹线 (101)6.5 光标 (102)6.6 测量 (105)7. 调制分析模式 (110)7.1 频率控制 (110)7.2 幅度控制 (111)7.3 带宽控制 (112)7.4 扫描控制 (113)7.5 迹线 (114)7.6 光标 (117)7.7 测量 (119)7.8 触发 (124)8. 实时频谱分析模式 (126)8.1 频率控制 (126)8.2 幅度控制 (129)8.3 带宽控制 (131)8.4 扫描控制 (132)8.5 迹线 (134)8.6 光标 (137)8.7 触发 (139)8.8 测量 (142)9. EMI测量 (145)9.1 频率控制 (145)9.2 幅度控制 (147)9.3 带宽控制 (150)9.4 扫描控制 (151)9.5 迹线 (153)9.6 光标 (155)9.7 限制 (159)10. 编程示例 (168)10.1 使用VISA的编程示例 (168)10.2Sockets/Telnet示例 (182)SIGLENT 1. 远程控制概述分析仪支持通过USB、LAN、GPIB-USB接口与计算机进行通信。

ATT7022B用户手册中文版210-SD-109_V1.0

ATT7022B用户手册中文版210-SD-109_V1.0

ATT7022B 用户手册目 录第一部分 芯片介绍 (4)§ 1.1 芯片特性 (4)§ 1.2功能简介 (5)§ 1.3 内部框图 (5)§1.4 引脚定义 (6)§1.5 应用示意图 (9)第二部分 系统功能 (10)§2.1 电源监控电路 (10)§2.2 系统复位 (10)§2.3 模数转换 (11)§2.4 有功功率测量 (12)§2.5 有功能量测量 (12)§2.6 无功功率测量 (13)§2.7 无功能量测量 (14)§2.8 视在功率测量 (14)§2.9 视在能量测量 (15)§2.10 电压有效值测量 (16)§2.11 电流有效值测量 (16)§2.12 电压线频率测量 (16)§2.13 功率因数测量 (17)§2.15 电压夹角测量 (17)§2.16 电压相序检测 (17)§2.17 电流相序检测 (18)§2.18 起动潜动设置 (18)§2.19 功率方向判断 (18)§2.20 失压检测 (18)§2.21 硬件端口检测 (19)§2.22 片上温度检测 (19)§2.23 基波谐波测量功能 (19)§2.24 三相三线与三相四线应用 (22)§2.25 能量脉冲输出 (22)§2.26 参数输出寄存器定义 (23)§2.27 参数输出寄存器说明 (27)第三部分 校表方法 (33)§3.1 软件校表 (33)§3.2 校表寄存器定义 (34)§3.3 校表寄存器说明 (35)第四部分 SPI通讯接口 (45)§4.1 SPI通讯接口介绍 (45)§4.2 SPI读操作 (46)§4.3 SPI写操作 (47)§4.4 SPI写特殊命令操作 (48)第五部分 电气特性 (50)§5.1 电气参数 (50)§5.2 芯片封装 (51)第一部分 芯片介绍§ 1.1 芯片特性• 高精度在输入动态工作范围(1000:1)，内非线性测量误差小于0.1% • 有功测量满足0.2S、0.5S，支持IEC 62053-22，GB/T 17883-1998 • 无功测量满足2级、3级，支持IEC 62053-23，GB/T 17882-1999 • 提供基波、谐波电能以及总电能测量功能• 提供视在电能测量功能• 提供正向和反向有功/无功电能数据• 提供有功、无功、视在功率参数• 提供功率因数、相角、线频率参数• 提供电压和电流有效值参数,有效值精度优于0.5%• 提供电压相序检测功能• 提供电流相序检测功能• 提供三相电流矢量和之有效值输出• 提供三相电压矢量和之有效值输出• 提供电压夹角测量功能• 提供失压判断功能• 具有反向功率指示• 提供有功、无功、视在校表脉冲输出• 提供基波有功、基波无功校表脉冲输出• 合相能量绝对值相加与代数相加可选• 内置温度测量传感器• 电表常数可调• 起动电流可调• 可准确测量到含21次谐波的有功、无功和视在功率• 支持增益和相位补偿，小电流非线性补偿• 具有SPI接口，方便与外部MCU通讯• 适用于三相三线和三相四线模式• 采用QFP44封装• 单+5V供电ATT7022B是一颗高精度三相电能专用计量芯片，适用于三相三线和三相四线应用。