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17.5.1 GAL16V8 GAL I/O module End Title Equations Pin Istype Test_vectors Truth_table When then Else If then else End I/O A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 0 0 1 0 1 1 1 N 1 1 1 0 1 0 0 0 20 11 VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I9/OE GAL16V8 I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 GND 1 10 2-9 …… …… …… …… …… …… (17-62 Y N AB BC CA A B B C AC (17-63 Module majority_voter; A,B,C pin 1,2,3; Y,N, pin 11,12; Equations Y=A&B#B&C#C&A;N=A!&B!#B!&C!#C!&A!; Test_vectors ([A,B,C]>[Y,N] [0,0,0]->[0,1]; [0,0,1]->[0,1]; [0,1,0]->[0,1]; [0,1,1]->[1,0]; [1,0,0]->[0,1]; [1,0,1]->[1,0]; [1,1,0]->[1,0]; [1,1,1]->[1,1];End majority_voters 17.6 VHDL 17.6.1 VHDL VHDL (17-64 (17-65 1. Module < > < > Module < > < > • entity is [generic port [signal] [signal] …… ; end ; architecture begin end “[ ]” (17-66 VHDL work entity is std ;] : : ;] • IEEE VHDL[generic port [signal] : numeric_bit numeric_std [signal] : std_logic_1164 … VHDL … ; end entity ; is library architecture use . . All begin std_logic_1164 of library IEEE of is useIEEE.std_logic_1164.all • EDA end architecture (17-672. In Module < > < > Out Inout entity is [generic port [signal] [signal] …… ; end entity ; architecture begin end arc hitecture of3. • • ;] : : Buffer Linkage std_logic isstd_logic_vectors(m downto n time integer constant: …… (17-68 (17-69 Module < > < > • entity is [generic port [signal] VHDL [signal] …… ; end entity ; architecture begin end architecture of ;] : : is VHDL Module < > < > 17.6.2 VHDL entity is [generic ;] not and or nand nor xor xnor port [signal] : = /= < > <= >= [signal] : & …… ; end entity ; x(3 downto 2 <= architecture begin end architecture of is + * / ** mod rem abs • • • x(1 & x(0; (17-70 (17-71 17.4.1 1. := <= <= after 1 else 2 else n else VHDL <= 1 when 2 when …… n when with select <= 1 when 2 when 2, n when others; 1, …… library IEEE use IEEE.std_logic_1164.all --************************************ entity and2 is generic (rised : time : = 1ns falld : time : =1ns; port (a1 : in std_logic; a2 : in std_logic; f : out std_logic; end and2; --************************************ architecture behavior of and2 is begin f<=a1 and a2 after 5ns; end behavior; (17-72 (17-7317.4.2 VHDL 2. component port ( : …… : end component ; ; ; Library IEEE; use IEEE.std_logic_1164.all; --******************************************** entity majority_voter3 is port (SW : in std_logic_vector(3 downto 1; L: out std_logic_vector(2 downto 1; --*****L1:pass(green LED L2:fail(red LED end majority_voter3; --******************************************** architecture behavior ofmajority_voter3 is begin with SW select L <= "10" when "011", "10" when "101", "10" when "110", "10" when "111", "01" when others; end behavior; (17-74 17.5.3 a b c L1 L2 L3 carry sum (17-75 library IEEE use IEEE_std_logic_1164.all --***************************** --half_adder entity half_adder is port(a,b: instd_logic; s, c0: out std_logic; end half_adder; architecture h_adder of half_adder is signal c,d : std_logic; begin c<=a or b; d<=a nand b; c0<=not d; s<=c and d; end h_adder; --*************************** (17-76 --full_adder entity full_adder is port (x,y,cin : in std_logic; sum, carry : out std_logic; end entity full_adder; architecture struct offull_adder is component half_adder port ( a,b: in std_logic; s, c0 : out std_logic; end component half_adder; signal L1,L2,L3: std_logic; begin P1: half_adder portmap(x,y,L1,L2; P2: half_adder port map(L1,cin,sum,L3; carry<= L2 or L3; end architecture struct; (17-77 3. Process process process ( begin end process; if elsif …… elsif else n+1 end if; n then n If 1 then 1 2 then 2 case case is when 1 => when 2 => …… when others => end case; (17-78 (17-7917.4.4 if case if sel=’1’ then c<=b; else c<=a; end if; 17.4.5 VHDL D CLK Q a MUX b sel c case sel is when 0 => c<=a; when 1=> c<=b; end case; CLK CLK CLK=1 library IEEE; use IEEE.std_logic_1164.all; --****************************** entity ff is port (CLK: in std_logic; D: in std_logic; Q: out std_logic; end ff; --****************************** architechure bhv of ff is singal Q1 : std_logic; begin process(CLK begin if CLK’event and CLK=’1’ then Q1 <=D; end if; end process; Q<=Q1; end bhv; (17-81 (17-80 * for loop [ in :] for loop ; :]; [ while loop :] while :]; loop ; end loop [ end loop [ * wait wait until a=1; --a wait on a,b; -wait a b ‘1’ wait a wait for 10ns -10ns wait until a=’1’ for 10ns; --a a 10ns (17-82。
