0
0 0 0 1 1
0
0 1 1 0 0
0
1 0 1 0 1
0
0 0 0 0 0
0
0 0 0 1 1
0
0 0 1 0 1
0
0 1 0 0 0
0
0 0 0 0 0
0
1 0 1 0 1
0
1 4 9 16 25
1
1
1
1
0
1
1
1
0
1
0
0
1
0
0
0
0
1
36
49
输出B0等于输入A0,输出B1一直为0. 本例中有三个输入端和四个输出端。
ZDMC
example:
personality matrix product term AB B'C AC' B'C' A
数字系统设计
inputs A B 1 1 – 0 1 – – 0 1 –
C – 1 0 0 –
outputs F0 F1 0 1 0 0 0 1 1 0 1 0
output side: 1 = term connected to output 0 = no connection to output reuse of terms
16
ZDMC
数字系统设计
Logic Diagram of a Typical SRAM
A
N
WE_L OE_L
2 N “words” x M bit SRAM
M
D
Write Enable is usually active low (WE_L) Din and Dout are combined to save pins: A new control signal, Output Enable (OE_L)