TEA5711中文资料

Philips SemiconductorsApplication Note Low voltage FM stereo radio with TEA5767/68AN10133AbstractThis document describes an application in which the FM stereo radio TEA5767/68 is being used. This new generation single-chip stereo radio is alignment free. Because of its low power consumption, small size and small FM application, this tuner will lead to a breakthrough in the market of portable consumer products, as mobile phone, CD and MP3 players.The radio can tune into the European, Japan and US FM bands.© Philips Electronics N.V. 2003All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.Application Note Low voltage FM stereo radio with TEA5767/68AN10133APPLICATION NOTELow voltage FM stereo radiowith TEA5767/68AN10133Author(s):M Ait MoulayPhilips Semiconductors Strategic Partnership CatenaThe NetherlandsKeywordsTEA5767/68FM-stereo RadioLow voltageDate: 18-06-2002Application Note Low voltage FM stereo radio with TEA5767/68AN10133SummaryThe TEA5767/68 is a single chip stereo FM receiver. This new generation low voltage FM radio has a fully integrated IF-selectivity and demodulation. The IC does not require any alignment, which makes the use of bulky and expensive external components unnecessary.The digital tuning is based on the conventional PLL concept. Via software, the radio can be tuned into the European, Japan or US FM band.The power consumption of the tuner is low. The current is about 13mA and the supply voltage can be varied between 2.5 and 5V.The radio can find its application in many areas especially portable applications as mobile phones, CD and MP3 players.This application note describes this FM radio in a small size and low voltage application. To demonstrate the operation of the tuners a demoboard is developed, which can be extended with a software controllable amplifier and a RDS chip. The whole application can be controlled from a PC by means of demo software.Application Note Low voltage FM stereo radio with TEA5767/68AN10133 CONTENTS1INTRODUCTION (9)2SYSTEM GLOBAL VIEW (10)2.1The TEA5767 (10)2.2FM STEREO application (11)2.3TEA5767HN package (12)3THE TEA5767HN (14)3.1Low Noise Amplifier (14)3.2Mixer (15)3.3IF selectivity (15)3.4Limiter (15)3.5Demodulator (15)3.6The MPX decoder (16)3.6.1The PLL (16)3.6.2The pilot detector (16)3.6.3The SNC (16)3.6.4The matrix decoder (17)3.6.5HCC (17)3.7The softmute (18)4THE TUNING SYSTEM (20)4.1The PLL tuning system (20)4.2PLL word calculation (21)4.2.1High side injection tuning (21)4.2.2Low side injection tuning (23)4.3IF counter (23)4.4Level ADC (25)4.5Tuning Algorithm (27)4.5.1Preset mode (28)4.5.2Search mode (29)5COMMUNICATION (30)5.1I2C bus interface (31)5.23-Wire bus (32)6TEA5767HN APPLICATION (34)6.1RF input (34)6.2VCO tank circuit (36)6.3Reference frequency (37)6.3.1Internal clocking (37)6.3.2Pulling and compensation (38)6.3.3External referance (38)6.4Layout Hints (39)7RDS/RBDS (40)7.1RDS/RBDS with SAA6588 (40)Application Note Low voltage FM stereo radio with TEA5767/68AN101338AUDIO AMPLIFIER (41)9INSTALLATION GUIDE (42)9.1Hardware (42)9.2Software (43)10SPECIFICATIONS (46)10.1FM radio + RDS characteristics (46)APPENDIX A: TEA5767HN DEMO BOARD (HVQFN40 FM-ONLY STEREO) (48)APPENDIX A: TEA5767HN DEMO BOARD (49)APPENDIX A: TEA5767HN DEMO BOARD (50)APPENDIX A: TEA5767HN DEMO BOARD (51)APPENDIX B: TEA5768HL DEMO BOARD (52)APPENDIX B: TEA5767/68HL DEMO BOARD (53)APPENDIX B: TEA5767/68HL DEMO BOARD (54)APPENDIX B: TEA5767/68HL DEMO BOARD (55)APPENDIX C: PR37002 MOTHER BOARD (WITH TDA7053AT AND SAA6588T) (56)APPENDIX D: PR37156 DSM INTERFACE (57)APPENDIX E: COMMUNICATION: WRITE MODE (58)APPENDIX F: COMMUNICATION: READE MODE (59)Application Note AN10133Low voltage FM stereo radio with TEA5767/68T ABLE OF FIGURES F IGURE 1 B LOCK APPLICATION DIAGRAM OF THE TEA5767HN.............................................................................................10F IGURE 2 B ASIC APPLICATION DIAGRAM OF TEA5767/68 STEREO RADIO ..............................................................................12F IGURE 3 P INNING OF THE TEA5767HN (HVQFN40)...........................................................................................................12F IGURE 4: B LOCK DIAGRAM OF THE SIGNAL PATH OF THE TUNER ...........................................................................................14F IGURE 5: BLOCK DIAGRAM OF THE QUADRATURE MIXER ......................................................................................................15F IGURE 6 P ILOT DETECTOR OF THE MPX DECODER ................................................................................................................16F IGURE 7 E FFECT OF THE SNC ON THE SIGNAL AND NOISE .....................................................................................................17F IGURE 8 INFLUENCE OF THE HCC ON AUDIO SIGNAL AND NOISE ..........................................................................................18F IGURE 9 EFFECT OF THE SOFTMUTE ON THE SIGNAL AND NOISE AT THE AUDIO OUTPUT ........................................................19F IGURE 10: TUNING SYSTEM WITH A 13MH Z CRYSTAL CLOCK ...............................................................................................20F IGURE 11: PLL SYNTHESISER WITH 32768H Z CRYSTAL CLOCK ............................................................................................21F IGURE 12: E XAMPLE OF PLL FREQUENCY CALCULATION : HIGH SIDE INJECTION ..................................................................22F IGURE 13: E XAMPLE OF PLL FREQUENCY CALCULATION : LOW SIDE INJECTION ...................................................................23F IGURE 14: BLOCK DIAGRAM OF IF COUNTER .........................................................................................................................24F IGURE 15: L EVEL ADC INPUT MEASURED VIA THE BUS ........................................................................................................25F IGURE 16: LEVEL ADC AS FUNCTION OF THE RF INPUT LEVEL (V CC =2.7V)..........................................................................26F IGURE 17: EFFECT OF HIGH /L OW SIDE INJECTION WITH STRONG SIGNALS .............................................................................27F IGURE 18: FALSE STOP BY HIGH LEVEL SIGNALS ...................................................................................................................28F IGURE 19 TYPICAL SERIAL INTERFACE APPLICATION WITH I 2C BUS INTERFACE ....................................................................30F IGURE 20 TYPICAL SIERAL APPLICATION WITH 3-W IRE BUS INTERFACE ...............................................................................30F IGURE 21 DATA TRANSFER FROM AND TO TEA5767HN.......................................................................................................32F IGURE 22 WRITE ACTION IN 3-W IRE BUS INTERFACE ............................................................................................................32F IGURE 23 READ OPERATION IN 3-W IRE BUS INTERFACE ........................................................................................................33F IGURE 24 A NTENNA MATCHING CIRCUIT FOR 40Ω SOURCE IMPEDANCE ...............................................................................34F IGURE 25 F REQUENCY RESPONSE OF THE MATCHING CIRCUIT IN FIGURE 6.1........................................................................34F IGURE 26 A NTENNA MATCHING CIRCUIT FOR 75 Ω SOURCE IMPEDANCE ..............................................................................35F IGURE 27: FREQUENCY RESPONSE OF THE MATCHING CIRCUIT OF FIGURE 6.3.......................................................................35F IGURE 28 D IODE CAPACITANCE AS FUNCTION OF REVERSE VOLTAGE ; TYPICAL VALUES ......................................................36F IGURE 29 TYPICAL OSCILLATOR TUNING CURVE OF PROPOSED FM APPLICATION .................................................................37F IGURE 30 CONNECTION OF THE 13MH Z AND 32768H Z CRYSTAL TO THE TUNER ..................................................................37F IGURE 31 CONNECTION OF 13M HZ EXTERNAL SIGNAL ..........................................................................................................39F IGURE 32: CONNECTION OF 32768H Z EXTERNAL SIGNAL ......................................................................................................39F IGURE 33 CONNECTION DIAGRAM OF THE SAA6588............................................................................................................40F IGURE 34CONNECTION OF TEA5767/68 DEMO BOARD .........................................................................................................42F IGURE 35 CONNECTION OF THE DSM INTERFACE TO THE MOTHERBOARD ............................................................................43F IGURE 36 FM CHARACTERISTIC OF TEA57567HN DEMO BOARD ........................................................................................47LIST OF TABLEST ABLE 1 PINNING DESCRIPTION OF THE TEA5767HN............................................................................................................13T ABLE 2: VCO REFERENCE FREQUENCY VERSUS THE CRYSTAL FREQUENCY .........................................................................22T ABLE 3: COUNTER RESULT DEPENDING ON THE F XTAL FLAG ...................................................................................................24T ABLE 4: SEARCH STOP LEVEL ................................................................................................................................................29T ABLE 5: SPECIFICATION OF NX4025GA 13MH Z CRYSTAL ...................................................................................................38T ABLE 6 V OLUME CONTROL ...................................................................................................................................................41T ABLE 7: FM RADIO + RDS CHARACTERISTICS (46)<THIS PAGE IS LEFT EMPTY>Application Note Low voltage FM stereo radio with TEA5767/68AN101331 INTRODUCTIONThe consumer demand of more integrated and low power consumption IC’s has increased tremendously in the last decade. The IC’s must be smaller, cheaper and consume less power. Especially for portable equipment like mobile phone, CD, MP3 and cassette players, these requirements are very important. In order to integrate a radio function in this kind of equipment it’s also important that the total application is small sized and the overall power is low. The TEA5767/68 is a single chip digitally tuned FM stereo radio. Its application is small, has a very low current consumption and is completely adjustment free. This makes the PCB design easy and save design-in time. The tuner contains all the blocks necessary to build a complete digitally tuned radio function.The FM tuners consist of three IC’s in 32 pins or 40 pins package. The IC’s can be controlled via a 3-Wire, I2C or both bus interfaces.A small application PCB demo board has been designed on which either of the three IC’s can be mounted. These demo boards can be placed on a motherboard, which can be extended with an audio amplifier and a R adio D ata S ystem (RDS/RBDS) IC.The three tuners are:•TEA5767HN FM stereo radio, 40 leads with I2C and 3-Wire bus interface, Body 6*6*0.85 mm, SOT1618•TEA5767HL FM stereo radio, 32 leads with 3-Wire bus interface, Body: 7*7*1.4 mm, SOT358.•TEA5768HL FM stereo radio, 32 leads with I2C bus interface, Body: 7*7*1.4 mm, SOT358.In this application note only one IC, the TEA5767HN and one demo board will be described. However, this description can also be applied for the other boards.Application Note AN10133Low voltage FM stereo radio with TEA5767/682 SYSTEM GLOBAL VIEW2.1 The TEA5767A block diagram of the TEA5767HN is given in Figure 1. The block diagram consists of a number of blocks that will be described according to the signal path from the antenna to the audio output.The RF antenna signal is injected into a balanced low noise amplifier (LNA) via a RF matching circuit. In order not to overload the LNA and the mixer the LNA output signal is fed to an automatic gain control circuit (AGC).In a quadrature mixer the RF signal is converted down to an IF signal of 225KHz by multiplying it with a local oscillator signal (LO). The chosen mixer architecture provides inherent image rejection.The VCO generates a signal with double the frequency necessary for the I/Q mixer structure. In the N1 divider block, the required LO signal is created. The frequency of the VCO is controlled with a PLL synthesiser system.The I/Q signals out the mixer are fed to an integrated IF filter (RESAMP block). The IF frequency of this filter is controlled by the IF Centre Frequency adjust block.The IF signal is then passed to the limiter block, which removes the amplitude variation from the signal. The limiter is connected to the level ADC and the IF counter blocks. These two blocks provide the properinformation about the amplitude and frequency of the RF input signal, which will be used by the PLL as stop criterion.The IC has a quadrature demodulator with an integrated resonator. The demodulator is fully integrated which makes IF alignments or an external resonator unnecessary.Application Note Low voltage FM stereo radio with TEA5767/68AN10133The stereo decoder (MPX decoder) in its turn is adjustment free and can be put in mono mode from the bus interface.The stereo noise cancelling (SNC) function gradually turns the stereo decoder from ‘full stereo’ to mono under weak signal conditions. This function is very useful for portable equipment since it improves the audio perception quality under weak signal conditions.The softmute function suppresses the interstation noise and prevents excessive noise from being heard when the signal level drops to a low level.The tuning system is based on a conventional PLL technique. This is a simple method in which the phase and the frequency of the VCO are continuously corrected, with respect to a reference frequency, until frequency acquisition takes place.Communication between the tuning system and an external controller is possible via a 3-Wire or I2C bus interface.2.2FM STEREO applicationThe application is identical for the three IC’s as mentioned in chapter 1. This application comprises two major circuits: RF input circuit and a FM oscillator circuit.The communication with a µ-computer can be performed via an I2C or a 3-Wire serial interface bus, selectable with BUSMODE pin, for the TEA5767HN. TEA5768HL operates in I2C bus mode and TEA5757HL in 3-Wire bus mode.The receivers can work with 32.768KHz or 13MHz clock crystal, which can be programmed by the bus interface. The PLL can also be clocked with 6.5MHz clock signal.Three audio outputs are available: audio left, audio right and MPX (multiplex).Application NoteAN10133Low voltage FM stereo radio with TEA5767/682.3 TEA5767HN packageThe TEA5767HN FM stereo radio is a 40 pins HVQFN (SOT1618) package IC which can be operate with I 2C or 3-Wire bus interface. The fully integrated IF selectivity and demodulation make it possible to design a very small application board with a minimum of very small and low cost components. The outline of the Figure 3 shows the pinning of the TEA5767HN and Table 1 gives a description of each pin of the IC.Application Note Low voltage FM stereo radio with TEA5767/68AN10133SYMBOL PIN DESCRIPTION Voltage min.SYMBOL PIN DESCRIPTION Voltage min.NC11Not connected NC421Not connectedCPOUT2Charge pump output of the synthesiser PLL 1.64V VAFL22Audio left outputVCOTANK13VCO tuned circuit output 1 2.5V VAFR23Audio right outputVCOTANK24VCO tuned circuit output 2 2.5V TMUTE24Time constant for the softmute 1.5VVCCVCO5VCO supply voltage 2.5V MPXOUT25FM demodulator MPX outDGND6Digital ground0V VREF26Reference voltage 1.45VVDIG7Digital supply voltage 2.5V TIFCENTER27Time constant for IF centre adjust 1.34VDATA8Bus data line input/output LIMDEC128Decoupling IF limiter 1 1.86VCLOCK9Bus clock line input LIMDEC229Decoupling IF limiter 2 1.86VNC210Not connected NC530Not connectedWRITE/READ11Write/read control for the 3-Wire bus NC631Not connectedBUSMODE12Bus mode select input IGAIN32Gain control current for IF filter0.48VBUSENABLE13Bus enable input AGND33Analog ground0VSWPORT114 Software programmable port 1VCC34Analog supply voltage 2.5VSWPORT215Software programmable port 2RFIN135RF input 10.93VXTAL116Crystal oscillator input 1 1.64V RFGND36RF ground0VXTAL217Crystal oscillator input 2 1.64V RFIN237RF input 20.93VPHASEDET18Phase detector loop filter 1.0V CAGC38Time constant RF AGCPILDET19Pilot detector lowpass filter0.7V LOOPSW39Switch output of synthesiser PLL filterNC320Not connected NC740Not connectedTable 1 pinning description of the TEA5767HNApplication Note Low voltage FM stereo radio with TEA5767/68AN101333 THE TEA5767HNThe TEA5767HN consists of three major blocks: the signal channel, the tuning system and the bus interface. In this chapter the signal channel will be described briefly. The tuning system and the interface will be explained in chapter 4 receptively 5.In Figure 4, a block diagram of the signal path is given.3.1Low Noise AmplifierThe TEA5767HN has an integrated low noise amplifier (LNA). This is a balanced amplifier, which is less sensible for common mode noise.The input impedance of the LNA is (100Ω||4pF) each pin (referenced to ground).To handle high level input signals, the gain of the LNA is controlled by means of an automatic gain controller (AGC). The AGC will be started when the antenna input reaches a level of about 4mV with a given application of 40Ω antenna impedance. The AGC has a range of 40dB.Application NoteAN10133Low voltage FM stereo radio with TEA5767/683.2 MixerThe TEA5767HN has a complex mixer. This mixer receives two RF signals directly from the LNA and delivers two signals with an intermediate frequency of 225KHz. The mixer output signals comprise an in-phase component (00) and a quadrature component (90o ).A block diagram of the mixer is given in Figure 5.Figure 5: block diagram of the quadrature mixerTheoretically, complex mixers can create perfect image cancellation and do not need an image rejection filter.However, because of imperfection in the channel end or LO divider signals, the tuner will have a limited image rejection problem.3.3 IF selectivityThe selectivity is provided by a band pass filter with a low intermediate frequency (IF). This IF filter is fully integrated, which results in an alignment-free selectivity. The centre frequency of this filter is 225KHz and has a –3dB bandwidth of 90KHz.At 200KHz from the centre frequency, the IF filter selectivity is about 40dB.The centre frequency of the IF filter is internally adjusted in order to remove the influence of process spread.3.4 LimiterThe limiter is DC coupled with feedback capacitors on pin 28 and 29. These capacitors build a low pass filter.3.5 DemodulatorThe demodulator is also fully integrated. The advantage of this is that no alignment will be necessary.The demodulator has a conversion factor of 75mV at 22.5kHz.Local OscillatorApplication Note Low voltage FM stereo radio with TEA5767/68AN101333.6The MPX decoder3.6.1The PLLThe stereo decoder PLL runs at 228kHz (12*19KHz). When using a crystal of 13MHz, the VCO is internally preset to 227.5KHz. The frequency sensitive phase detector can only accelerate the VCO. After the PLL is locked on the proper frequency (228KHz), it will become inactive.When the crystal clock frequency is changed the principle stays the same. The PLL in a locked situation is still running at 228KHz. The preset frequency, however, is now 229.4KHz. In this situation, the phase detector can only slow down the VCO until the PLL is locked on 228kHz.A divider delivers a quadrature 19KHz signal, which will be multiplied with the 19KHz spectral component of the MPX signal. When there is a phase difference between the two signals, a dc current is generated that will adjust the VCO until synchronisation has taken place.Care should be taken with the capacitors used in the loop filter (pin 18 of TEA5767HN). Any leakage current due to these capacitors will affect the PLL VCO free running frequency and will reduce the capture range and channel separation. Therefore, capacitors with a stable temperature coefficient are recommended.3.6.2The pilot detectorVia a divider circuit, the PLL stereo decoder will deliver the 19kHz, 0o signal to the pilot detector. This signal will be multiplied with the pilot present in the MPX signal. This will give a DC signal that is proportional with the pilot amplitude.The pilot filter will remove the audio information and the 38kHz components. Figure 6 gives a block diagram of the pilot detector.Figure 6 Pilot detector of the MPX decoderBit 7 of byte 3 gives an indication of stereo reception. When this bit is high the reception is stereo otherwise mono. Leakage current due to the pilot filter will decrease the pilot sensitivity. This can lead to erroneous indication of the stereo reception3.6.3The SNCApplication Note Low voltage FM stereo radio with TEA5767/68AN10133When the Stereo Noise Cancelling -also named SDS (Signal dependant stereo)- is on, it will switch the stereo decoder from stereo to mono in case a weak signal is received. This will limit the output noise of the decoder. Also by the absence of the pilot or when the stereo control is switched to “force mono”, switching SNC on or off will not affect the audio reception so that only mono information will be passed to the audio outputThe SDS can be switched via the bus with bit 1 of data byte 4.Figure 7 gives a typical measurement of the audio signal and noise with SNC on and SNC off.Figure 7 Effect of the SNC on the signal and noise3.6.4The matrix decoderThe matrix decoder calculates the audio left and right signals and delivers them to the outside of the IC via pin 22 and 23.3.6.5HCCHigh Cut Control is an option, which gives the possibility to cut high frequencies from the audio signal when a weak signal is received.The HCC can be switched via the bus with bit 2 of data byte 4.Figure 8 illustrates the influence of the HCC op the audio signal and noise.Application Note Low voltage FM stereo radio with TEA5767/68AN10133Figure 8 influence of the HCC on audio signal and noise3.7The softmuteThe RF input signal can come under weak level input so that the total noise energy in the AF spectrum can be larger than the AF signal. This causes an unpleasant sound. When activated, the softmute will limit the amount of noise energy in the AF spectrum. The inter-station noise is then attenuated which will result in a better perception of the audio signal.The softmute is controllable via the bus interface. By setting bit 3 of data byte 4, the softmute is switched on. Otherwise it is off.Figure 9 illustrates the working of the softmute.Application Note Low voltage FM stereo radio with TEA5767/68AN10133Figure 9 effect of the softmute on the signal and noise at the audio outputApplication Note Low voltage FM stereo radio with TEA5767/68AN101334 THE TUNING SYSTEMThe TEA5767HN tuning system is based on a conventional PLL technique. The tuning system is controlled by means of state machine.In this chapter the tuning system, level ADC and IF counter will be described.4.1The PLL tuning systemThe tuning system is based on the conventional PLL technique. This is a very simple concept in which the programmable divider is stepwise increased or decreased until a signal is found.In a phase detector (PD) the output signal of the programmable divider is compared to a reference frequency. The PD steers a chargepump, which via a loop filter will deliver the necessary tune current to the VCO. The PLL uses two loop filters with different time constants. At the first stadium, the loop must be fast for quick response but later the loop should have a narrow bandwidth to limit noise contribution in order to achieve aFigure 10: tuning system with a 13MHz crystal clockThe PLL synthesiser can operate with either 32.768KHz or 13MHz crystal clocks. The choice for 13MHz is due to the fact that this frequency is utilised in mobile phones so that an extra crystal is not necessary in that kind of application. The 32768Hz clock signal makes it possible to use the cheap watch crystal.Further it is possible for the synthesiser to be clocked externally with 13MHz, 6.5MHz or 32768Hz clock signal (see pragraph 6.3.3, page 38).In Figure 10 and Figure 11, a block diagram of the tuning system is given when using a 13MHz crystal respectively 32768Hz.Application NoteAN10133Low voltage FM stereo radio with TEA5767/68Figure 11: PLL synthesiser with 32768Hz crystal clockIn contrast to most tuner systems that use an IF of 10.7MHz, the TEA5767/68 uses a low IF of 225KHz. With this low IF, integration of the IF filter becomes feasible. This aims to reduce the overall system costs and power.Further the tuner can work in two modes: high side injection or low side injection. The choice of one of these modes determines whether the local oscillator is placed above or below the wanted frequency (see Figure 12 and Figure 13), swapping the image with respect to the reception frequency. This feature is added due to the practical achievable image suppression that can be obtained (see paragraph 4.5).As the figures illustrate, the image frequency is situated at 450KHz (2*IF) distance below or above the wanted frequency. In software, the HILO bit can used to put the tuner in high side injection mode (HILO=1) or low side injection (HILO=0). The HILO bit is bit 4 of data byte 3.4.2 PLL word calculationTo tune the radio to a wanted frequency, the corresponding PLL word must first be calculated. This is a 14 bits word, which will be sent to the programmable divider.To do this a distinction will be made between high and low side injection.4.2.1 High side injection tuningIn high side injection mode the PLL word is calculated with the following formula:()REFSif RFDEC F F FN )(*4+≡with:N DEC = Decimal value of PLL wordF RF = the wanted tuning frequency [Hz}F if= the Intermediate Frequency [Hz]F REFS= the reference frequency [Hz}In the PC control software this is implemented in the following way:Application NoteAN10133Low voltage FM stereo radio with TEA5767/68PLL = N DEC = Decimal value of PLL wordTunedFrequency is the wanted tuning frequency in MHz ,F if is the Intermediate Frequency of 225 kHz,REF[XTAL] is the reference frequency in kHz , which depends on the selection of the oscillator frequency as shown in the table below:XTAL PLL REF Reference frequency Crystal frequency 0050000 Hz 13 MHz 0150000 Hz6.5 MHz 1032768 Hz 32.768 kHz 1132768 Hz32.768 kHzTable 2: VCO reference frequency versus the crystal frequencyNow that The PLL word has been calculated in decimal, it must be converted to Hex decimal before sending in to the tuning system.If the receiver has to be tuned to a FM frequency of 100MHz, the PLL word will be calculated as follow:Figure 12 gives an example of frequency tuning with high side injection.ùêêêëé+≡1000][)1000*(*4XTAL REF F ency TunedFrequ ROUND PLL if 5218018100050000)2251000*100(*4F PLL ROUND PLL HEXDEC ≡=ùêêêëé+≡。

TEA1716T中文资料免费版1. General descriptionTEA1716T集成了功率因数校正器(PFC)控制器和半桥谐振变换器的控制器(HBC)multi-chip IC。

它提供了离散MOSFET的驱动功能在一个上升变换器和两个离散功率场效应管谐振半桥配置。

高效PFC操作是通过实现准谐振软开关技术(QR)操作功能在高功率水平与QR操作谷跳跃在低功率水平。

过电流保护(OCP)、过电压保护装置(OVP)和退磁传感在所有条件下确保安全运行。

HBC模块是一个高压零开关LLC谐振变换器的控制器。

它包含一个高压电平转变电路和保护电路包括OCP,开环保护,电容模式保护和通用门锁保护输入。

高压芯片制作用的是专用高压Bipolar-CMOS-DMOS功率逻辑处理能够有效的从电源电压直接启动。

低压绝缘硅片(SOI)芯片用于准确、高速的保护功能和控制。

TEA1716T控制PFC电路和谐振转换器是非常灵活的。

它可以用于广泛的应用在一个宽的电源电压范围。

PFC和HBC控制器结合在一个单一的电源控制IC 使TEA1716T理想在液晶和等离子电视。

使用TEA1716T提供高效、可靠的电力供应从90 W到500 W可以轻松地使用TEA1716T设计,用最少的外部组件。

TEA1716T的集成突发模态和电源管理功能使共振的应用程序满足能源使用产品指令(EuP)很多6(< 0.5 W在待机模式)。

2.1 General features集成PFC和HBC控制器通用电源运行从70V-276V (AC)高水平的集成导致较低的外部组件数量和成本效益的设计集成突发模式感应符合能源使用产品指令(EuP)6使能输入只允许使能PFC或者PFC和HBC控制器芯片上的高压启动源独立运行或从DC源供应2.2 PFC controller features及时控制边界模式操作谷底和零电压开关以致最小损耗频率限制来减少开关损耗精确的增压调节用软启动和软停止的突发模式开关2.3 HBC controller features集成高压电平位移器可调节最大和最小频率半桥开关频率最大可达500KHz合适的非重叠时间突发模式开关2.4 Protection features安全系统故障条件下重启模式通用门锁保护输入对输出过电压保护或外部温度保护保护定时器超时并重启过温保护对两个控制器软启动欠电压保护给电源(断电),增压,IC供应和输出电压对两个控制器进行过流保护和调节对增高电压精确的过压保护对HBC控制器容性模式保护3. ApplicationsLCD电视等离子电视笔记本适配器台式机6.2 Pin descriptionCOMPPFC 1 PFC控制器频率补偿，外部链接到过滤器SNSMAINS 2 电源电压输入感应;外部连接分压电阻电源电压SNSAUXPFC 3 PFC消磁时间感应输入;外部连接到PFC的辅助绕组SNSCURPFC 4 PFC控制器为瞬时电流和软启动检测输入;外部连接到电流检测电阻和软启动过滤器SNSOUT 5 检测输入监测HBC输出电压;外部连接到辅助绕组SUPIC 6 SUPIC低压输入和输出的内部高压启动源;外部连接到辅助绕组HBC 或外部直流供电GATEPFC 7 PFC MOSFET 门极驱动输出PGND 8 电源地，HBC和PFC参考地SUPREG 9 管理SUPREG IC供应;内部调节器输出,输入驱动;外部连接到SUPREG缓冲电容器GATELS 10 HBC 低边MOSFET 门驱动输出n.c. 11 不连接SUPHV 12 内部高压启动源供应源高压输入;外部连接来提高电压GATEHS 13 HBC 高边MOSFET门驱动输出SUPHS 14 高端的驱动提供输入;外部连接到自举电容(CSUPHS)HB 15 参考高端驱动和半桥斜坡输入检测;外部连接到半桥节点HB的HBC mosfet之间(参见图17)n.c. 16 不连接SNSCURHBC 17 瞬时HBC检测输入;外部连接到谐振电流检测电阻SGND 18 信号地和IC参考地CFMIN 19 HBC最低频率设置;外部连接的电容器SNSBURST 20 突然停止激活检测输入;外部连接分压电阻SNSFB电压SNSFB 21 输出电压调节反馈检测输入;外部连接到光耦合器和上拉电阻SSHBC/EN 22 HBC软启动t时间和IC使能输入;使能PFC或PFC只或PFC和HBC控制器;外部连接到s软启动电容器,使下拉的信号RCPROT 23 保护定时器设置超时并重启;外部连接的电阻器和电容器SNSBOOST 24 检测输入增加电压调整;外部连接分压电阻提高电压7. Functional descriptionTEA1716T可以组合的功能如下:电源模块:IC供应管理。

TEA1752T; TEA1752LTGreenChip III SMPS control ICRev. 02 — 24 June 2010Product data sheet1. General descriptionThe GreenChip III is the third generation of green Switched Mode Power Supply (SMPS)controller ICs. The TEA1752T and TEA1752LT combine a controller for Power FactorCorrection (PFC) and a flyback controller. The high level of integration facilitates thedesign of a cost-effective power supply using a minimum number of external components.The special built-in green functions provide high efficiency at all power levels. This appliesto quasi-resonant operation at high power levels, quasi-resonant operation with valleyskipping and reduced frequency operation at lower power levels. At low power levels, thePFC switches off to maintain high efficiency.During low power conditions, the flyback controller switches to frequency reduction modeand limits the peak current to an adjustable minimum value. This will ensure highefficiency at low power and good standby power performance while minimizing audiblenoise from the transformer.The TEA1752(L)T is a MultiChip Module (MCM), containing two chips. The proprietaryhigh voltage BCD800 process which enables direct start-up from the rectified universalmains voltage in an effective and green way and a low voltage Silicon-On Insulator(SOI)which provides accurate, high speed protection functions and control.The TEA1752(L)T enables highly efficient and reliable supplies with power requirementsof up to 250W to be designed easily and with a minimum number of externalcomponents.2. Features and benefits2.1Distinctive featuresIntegrated PFC and flyback controllerUniversal mains supply operation (70V(AC) to276V(AC))Dual boost PFC with accurate maximum output voltage (NXP Semiconductorspatented, US patent number: US7575280)High level of integration, resulting in a very low external component count and acost-effective designAdjustable PFC switch-off delay2.2Green featuresOn-chip start-up current source2.3PFC green featuresValley/zero voltage switching for minimum switching losses(NXP Semiconductors patented, US patent number: US6256210)Frequency limitation to reduce switching lossesPFC is switched off when a low load is detected at the flyback output2.4Flyback green featuresValley switching for minimum switching losses(NXP Semiconductors patented,US patent number: US6256210)Frequency reduction with fixed minimum peak current at low power operation tomaintain high-efficiency at low output power levels2.5Protection featuresSafe restart mode for system fault conditionsContinuous mode protection by means of demagnetization detection for bothconverters (NXP Semiconductors patented, patent number: US5032967)UnderVoltage Protection (UVP) (foldback during overload)Accurate OverVoltage Protection (OVP) for PFCAccurate, adjustable OverVoltage Protection (OVP) for flyback converter(NXP Semiconductors patented,patent number: US6542386)Mains voltage independent OverPower Protection (OPP)(NXP Semiconductors patented, patent number: US6542386)Open control loop protection for both converters. The open-loop protection on theflyback converter is latched on the TEA1752LT and safe restart on the TEA1752T IC overtemperature protectionLow and adjustable OverCurrent Protection (OCP) trip level for both convertersGeneral purpose input for latched protection, e.g. to be used for systemOverTemperature Protection (OTP)3. ApplicationsAll applications requiring efficient and cost-effective power supply solutions to 250W.Notebook adapters in particular can benefit from the high level of integration4. Ordering informationTable 1.Ordering informationType number PackageName Description Version TEA1752T SO16plastic small outline package; 16leads; body width 3.9mm SOT109-1 TEA1752LT SO16plastic small outline package; 16leads; body width 3.9mm SOT109-15. Block diagram6. Pinning information6.1Pinning6.2Pin descriptionTable 2.Pin descriptionSymbol Pin DescriptionV CC1supply voltageGND2groundFBCTRL3control input for flybackFBAUX4input from auxiliary winding for demagnetization timing andovervoltage protection for flybackLATCH5general purpose protection inputPFCCOMP6frequency compensation pin for PFCVINSENSE7sense input for mains voltagePFCAUX8input from auxiliary winding for demagnetization timing for PFCand valley sensing of the PFC partVOSENSE9sense input for PFC output voltageFBSENSE10programmable current sense input for flybackPFCSENSE11programmable current sense input for PFCPFCDRIVER12gate driver output for PFCFBDRIVER13gate driver output for flybackPFCTIMER14delay timer pin for PFC on/off controlHVS15high voltage safety spacer, not connectedHV16high voltage start-up and valley sensing of flyback part7. Functional description7.1General controlThe TEA1752(L)T contains controllers for a power factor correction circuit and for aflyback circuit. A typical configuration is shown in Figure3.7.1.1Start-up and UnderVoltage LockOut (UVLO)Initially the capacitor on the V CC pin is charged from the high voltage mains via the HV pin.If V CC is lower than V trip, the charge current is low. This protects the IC if the V CC pin isshorted to ground. The charge current above V trip is increased until V CC reaches V th(UVLO)to achieve a short start-up time. If V CC is between V th(UVLO) and V startup, the charge currentis low again, ensuring a low duty cycle during fault conditions.The control logic activates the internal circuitry and switches off the HV charge currentwhen the voltage on pin V CC passes the V startup level. The LATCH pin current source isthen activated and the soft start capacitors on pins PFCSENSE and FBSENSE arecharged and the clamp circuit on pin PFCCOMP is activated. When the LATCH pinvoltage exceeds V en(LATCH), the PFCCOMP pin voltage exceeds V en(PFCCOMP) and the softstart capacitor on pin PFCSENSE pin is charged, the PFC circuit is activated. The flybackconverter is also activated (providing the soft start capacitor on the FBSENSE pin is charged). The flyback converter output voltage is then regulated to its nominal value. The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure4.If during start-up the LATCH pin does not reach the V en(LATCH) level before V CC reaches V th(UVLO), the LATCH pin output is deactivated and the charge current is switched on again.When the flyback converter is started, the voltage on pin FBCTRL is monitored. If the flyback converter output voltage does not reach its intended regulation level in a predefined time, the voltage on pin FBCTRL reaches the V to(FBCTRL) level and an error is assumed. The TEA1752T then initiates a safe restart, while in the TEA1752LT the protection is latched.When one of the protection functions is activated, both converters stop switching and the V CC voltage drops to V th(UVLO). A latched protection recharges the capacitor C VCC via the HV pin, but does not restart the converters. For a safe restart protection, the capacitor is recharged via the HV pin and the device restarts. See Figure1.In the event of an overvoltage protection of the PFC circuit whereV VOSENSE>V ovp(VOSENSE), the PFC controller stops switching until the VOSENSE pin voltage drops back below V ovp(VOSENSE). If a mains undervoltage is detected whereV VINSENSE<V stop(VINSENSE), the PFC controller stops switching untilV VINSENSE>V start(VINSENSE).When the voltage on pin V CC drops below the undervoltage lockout level, both controllers stop switching and reenter the safe restart mode. In this mode the driver outputs are disabled and the V CC pin voltage is recharged via the HV pin.7.1.2Supply managementAll internal control voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. Internal reference currents are derived from a temperaturecompensated and trimmed on-chip current reference circuit.7.1.3Latch inputPin LATCH is a general purpose input pin, which can be used to switch off bothconverters. The pin sources a current I O(LATCH) (80μA typical). Switching off bothconverters is stopped as soon as the voltage on this pin drops below 1.25V.At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged above 1.35V(typical). No internal filtering is carried out on this pin. An internal zenerclamp of 2.9V(typical) protects this pin from excessive voltages.7.1.4Fast latch resetIn a typical application the mains supply can be interrupted briefly to reset the latchedprotection. The PFC bus capacitor, C bus, does not need to discharge for this latchedprotection to reset.Typically the PFC bus capacitor, C bus, must discharge for the V CC to drop to this resetlevel. When the latched protection is set, the VINSENSE clamping circuit is disabled. See Section7.2.10. When the VINSENSE voltage drops below 0.75V(typical) then increases to 0.87V(typical), the latched protection is reset.The latched protection is also reset by removing the voltage on pins V CC and HV.7.1.5OverTemperature Protection (OTP)Integrated overtemperature protection ensures the IC stops switching if the junctiontemperature exceeds the thermal temperature shutdown limit.Capacitor C VCC will not recharge from the HV mains while OTP is active. The OTP circuit is supplied from the HV pin if the V CC supply voltage is insufficient.OTP is a latched protection that can be reset either by removing the voltage on pins V CC and HV or by the fast latch reset function. See Section7.1.4.7.2Power Factor Correction circuit (PFC)The power factor correction circuit operates in quasi-resonant or discontinuousconduction mode with valley switching. The next primary stroke only starts when theprevious secondary stroke has ended and the voltage across the PFC MOSFET hasreached a minimum value. The voltage on the PFCAUX pin is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch. 7.2.1t on controlThe power factor correction circuit is operated in t on control. The resulting mains harmonic reduction of a typical application is well within the class-D requirements.7.2.2Valley switching and demagnetization (PFCAUX pin)The PFC MOSFET is switched on after the transformer has been demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It alsodetects the voltage across the PFC MOSFET. The next stroke is started when the voltage across the PFC MOSFET is at its minimum in order to reduce switching losses andElectroMagnetic Interference(EMI) (valley switching).If no demagnetization signal is detected on the PFCAUX pin, the controller generates a Zero Current Signal (ZCS), 50μs(typical), after the last PFCGATE signal.If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal, 4μs (typical), after demagnetization was detected.It is advisable to add a 5k Ω series resistor to this pin to provide surge protection for the internal circuitry against events such as lightning surge. To prevent incorrect switching due to external disturbance, this resistor should be placed as close as possible to the IC on the printed-circuit board.7.2.3Frequency limitationTo optimize the transformer and minimize switching losses, the switching frequency is limited to f sw(PFC)max . If the frequency for quasi-resonant operation is above the f sw(PFC)max limit, the system switches over to discontinuous conduction mode. The PFC MOSFET is then only switched on at a minimum voltage across the switch (valley switching).7.2.4Mains voltage compensation (VINSENSE pin)The mathematical equation for the transfer function of a power factor corrector contains the square of the mains input voltage. In a typical application this results in a low bandwidth for low mains input voltages, while at high mains input voltages the Mains Harmonic Reduction (MHR) requirements may be hard to meet.The TEA1752(L)T incorporates a correction circuit to compensate for the mains input voltage influence. The average input voltage is measured via the VINSENSE pin and this information is fed to an internal compensation circuit. With this compensation it is possible to keep the regulation loop bandwidth constant over the full mains input range, yielding a fast transient response on load steps, while still complying with class-D MHR requirements.In a typical application, the regulation loop bandwidth is set by a resistor and two capacitors on the PFCCOMP pin.7.2.5Soft start-up (pin PFCSENSE)To prevent audible transformer noise at start-up or during hiccup, the transformer peak current is increased slowly by the soft start function. This can be achieved by inserting R SS1 and C SS1 between pin PFCSENSE and the current sense resistor, R SENSE1.An internal current source charges the capacitor to V PFCSENSE =I start(soft)PFC ×R SS1. The voltage is limited to V start(soft)PFC .The start level and time constant of the increasing primary current level can be adjusted externally by changing the values of R SS1 and C SS1.The charging current I start(soft)PFC flows if the voltage on pin PFCSENSE is lower than 0.5V (typical). If the voltage on pin PFCSENSE exceeds 0.5V, the soft start current source limits current I start(soft)PFC . When the PFC starts switching, the I start(soft)PFC current source is switched off (see Figure 5).Resistor R SS1 and capacitor C SS1 are also used to prevent audible noise, when the PFC is switched off by performing a soft stop.τsoftstart 3R SS1C SS1××=分销商库存信息:NXPTEA1752T/N1,518TEA1752LT/N1,518。

TEA1713T带PFC的谐振电源控制IC2011年2月9日，第2版产品数据手册1. 概述TEA1713在一个多芯片IC中集成了功率因数校正控制器(PFC)和半桥谐振变换器（HBC），可驱动升压转换器中的分立MOSFET和谐振半桥结构中的两个分立功率MOSFET。

PFC部分在高功率时工作在准谐振状态,低功率时工作在准谐振与跳谷底状态,从而实现高效率。

内置的过流保护（OCP），过压保护（OVP）以及退磁检测功能可确保控制器安全工作在所有条件下。

HBC部分是一个高压控制器，用于零电压开关LLC谐振变换器，该模块含有一个高压电平转换电路和多个保护电路，其中包括过流保护、开环保护、容性模式保护和通用的带闭锁保护的输入引脚。

该高压芯片采用专有高压双极性CMOS-DMOS功率逻辑工艺制造，确保从整流后的通用市电电压直接启动。

低压部分的硅绝缘芯片（SOI）用于精密、高速保护功能和控制。

TEA1713的PFC电路和谐振变换器的拓扑结构非常灵活，可用于宽市电电压内的各种应用。

TEA1713在单一芯片中集成PFC和HBC控制器，是LCD和等离子电视电源控制器的理想之选。

使用TEA1713可轻松设计功率大于100W的高功效和高可靠性电源，仅需很少的外部元器件。

带PFC的谐振电源控制IC 2. 特性和优势2.1 一般特性集成PFC和HBC控制器适合所有市电电压（交流70 V - 276 V )集成度高,外部元件数量少,性价比高带使能输入（使能单PFC控制器工作或PFC和HBC控制器一起工作）内置高压启动源系统自供电或外部直流电源给IC供电2.2 PFC控制器特性临界导通模式,Ton控制谷底/零电压开关可以最大限度减小开关损耗受限制的最高频率可使开关损耗减至最小升压后的电压可精确调整具有软启动和软停止功能的打嗝模式开关2.3 HBC控制器特性集成高压电平转换器可调的最小和最大频率最大500kHz半桥开关频率自适应非重叠时间打嗝模式开关2.4 保护特性系统故障时进入安全重启模式通用带闭锁功能保护的输入脚用于输出过压保护或外部过温保护用于故障超时和重启的保护定时器过温保护两种控制器均具有软（重）启动功能针对市电电源（掉电），升压电压，IC电源和输出电压的欠压保护两种控制器均有过流调节和保护功能精确的升压电压过压保护用于HBC控制器的容性模式保护3. 应用液晶电视等离子电视电源适配器4. 订购信息带PFC的谐振电源控制IC 表1订购信息5. 功能框图带PFC的谐振电源控制IC 6. 引脚信息6.1 引脚排列6.2 引脚描述表2 引脚描述带PFC的谐振电源控制IC表2 引脚描述（续）7. 功能描述7.1 IC模块概述TEA1713的功能可分为以下几类：电源模块：IC电源管理；包括重启和（锁存）关断状态保护和重启定时器：外部可调定时器，用于延迟保护和重启定时使能输入：使能和禁止控制器工作的控制信号输入；禁止时功耗极低PFC控制器：控制和保护功率因数转换器；从整流后交流市电输入，产生高功率因数400 V（直流）升压电压HBC控制器：控制和保护谐振转换器；用400 V（直流）升压电压产生可调节的（市电隔离）输出电压图1所示为TEA1713的功能框图。