EDA计数器实验
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计数器
一、实验目的
1、设计一个带使能输入、进位输出及同步清0的增1十进制计数器
2、设计一个带计数使能、同步清0、同步加载的4位计数器
3、设计一个带使能、同步清0控制和进位输出的增14位二进制计数器，计数结果由一位7段码管显示。
4、设计一个带使能和同步清0控制的增1减18位二进制计数器，计数结果由7段数码管显示。
二、实验内容
1、带使能、同步清0控制和进位输出的增14位二进制计数器
VHDL源代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter2 is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
en : in STD_LOGIC;
co : out STD_LOGIC;
y : out STD_LOGIC_VECTOR (6 downto 0));
end counter2;
architecture Behavioral of counter2 is
signal cnt:STD_LOGIC_VECTOR(3 downto 0);
signal led:STD_LOGIC_VECTOR(6 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
if clr='1' then
cnt<=(others=>'0');
elsif en='1' then
if cnt="1111" then
cnt<="0000";
else
cnt<=cnt+'1';
end if;
end if;
end if;
end process;
co<='1' when cnt="1111" else '0';
y<=not led;
with cnt select led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"when others;
end Behavioral;
激励文件源代码
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY counter_2_tbw_vhd IS
END counter_2_tbw_vhd;
ARCHITECTURE behavior OF counter_2_tbw_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter2
PORT(
clk : IN std_logic;
clr : IN std_logic;
en : IN std_logic;
co : OUT std_logic;
y : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL clr : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs
SIGNAL co : std_logic;
SIGNAL y : std_logic_vector(6 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT) uut: counter2 PORT MAP(
clk => clk,
clr => clr,
en => en,
co => co,
y => y
);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
clr<='1','0' after 30 ns;
en<='0','1' after 20 ns;
-- Wait 100 ns for global reset to finish
--wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;
功能仿真
时序仿真
管脚设置 NET "clk" LOC = "E10" ;
NET "clr" LOC = "L13" ;
NET "co" LOC = "F12" ;
NET "en" LOC = "L14" ;
NET "y<0>" LOC = "B4" ;
NET "y<1>" LOC = "A4" ;
NET "y<2>" LOC = "D5" ;
NET "y<3>" LOC = "C5" ;
NET "y<4>" LOC = "A6" ;
NET "y<5>" LOC = "B6" ;
NET "y<6>" LOC = "E7" ;
实验现象
七段数码管显示0、1、2、3、4、5、6、7、8、9、A、b、C、d、E、F，每次循环完成co所接led灯亮一下，表示进位。实验现象与设计相符，实验结果正确。
2、带使能输入、进位输出及同步清0的增1十进制计数器
VHDL源代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter3 is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
en : in STD_LOGIC;
co : out STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter3;
architecture Behavioral of counter3 is
SIGNAL cnt : STD_LOGIC_VECTOR(3 downto 0);
begin
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clr = '1' THEN
cnt <= (OTHERS => '0');
ELSIF en = '1' THEN IF cnt = "1001" THEN
cnt <= "0000";
co<='1';
ELSE
cnt <= cnt + '1';
co<='0';
END IF;
END IF;
END IF;
END PROCESS;
count <= cnt;
end Behavioral;
激励信号代码
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY counter_tbw_vhd IS
END counter_tbw_vhd;
ARCHITECTURE behavior OF counter_tbw_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter3
PORT(
clk : IN std_logic;
clr : IN std_logic;
en : IN std_logic;
co : OUT std_logic;
count : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL clr : std_logic := '0';
SIGNAL en : std_logic := '0';
--Outputs
SIGNAL co : std_logic;
SIGNAL count : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: counter3 PORT MAP(
clk => clk,
clr => clr,
en => en,
