QuartusII错误汇总

Error(10257):Verilog HDL error at dp4inNpa.v(13):unsized constants are not allowed in concatenations解决方法：拼接语句a_fout={0,exp_a_out,temp_a_out,12'd0};其中0应标注位宽，编辑器不会默认为1位，应为a_fout= {1'b0,exp_a_out,temp_a_out,12'd0};Error(10053):Verilog HDL error at dp4inNpa.v(12):can't index object"a" with zero packed or unpacked array dimensions解决方法：错：input a;对：input[12:0]a;Error:Net"acc[12]",which fans out to"accumulate:inst4|acc[12]", cannot be assigned more than one valueError:Net is fed by"time_get_sub:inst3|acc[12]"Error:Net is fed by"sample_en:inst6|acc_out[12]"解决方法：输入的某些引脚同时给了两个值，大概不是重复定义管脚就是重复赋值了。

Error:Top-level design entity"delta_t"is undefined解决方法：将.v文件名和module的名称改为一致Error:Inconsistent dimensions for element"tR"解决方法:"tR"在传递过程中可能丢失了"[12..0]"。

SDRAM的时钟超前控制器的时钟值取读超前或写超前中的较小值。
读超前：tCO_MIN（FPGA)-tDH（SDRAM）
写超前：tCLK-tHZ（SDRAM）-tSU_MAX（FPGA）
所以，相对于控制器的时钟，SDRAM的时钟相移值为：（-读滞后+读超前）/2
SDRAM的CAS延迟。
FPGA和SDRAM芯片的不同连接，其有效的窗口时序不同，即窗口依赖于Quartus 2 的布局布线结果和引脚分配。
2.计算方法如下：
SDRAM的时钟滞后控制器的时钟值读取滞后或滞后中的较小值。
读滞后：tOH（SDRAM）-tH_MAX（FPGA）
写滞后：tCLK（FPGA）-tDS（SDRAM）
Resetting and pausing target processor: FAILED
Leaving target processor paused
There are no Nios II CPUs with debug modules available which match the values
1.首先来说明一下影响SDRAM时序的因素都有那些
FPGA和SDRAM I/O引脚的时序参数——I/O时序参数随着FPGA器件的型号和速度而变化。
在FPGA上的引脚位置——与行布线链接的I/O引脚和与列布线连接的I/O引脚有不同的时序。
在Quartus 2 编译期间使用的逻辑选项——逻辑选项，录入快速输入寄存器和快速输出寄存器，影响设计的布局布线，逻辑电路的位置和FPGA内部的寄存器影响信号到I/O的传播延时。
答2：1、检查一下，是否加了Jtag debug module；
2、加给CPU的时钟是否正常；

Quartus常见错误警告分析Quartus常见错误分析ErrorWarning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list----没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-----可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode outcannot be read. Change object mode to buffer or inout.------信号类型设置不对，out当作buffer来定义4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"-------引用的例化元件未定义实体－－entity "clk_gen"5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s)analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as bufferInfo: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holdsits previous in every path with no new assignment, whichmay create a combinational loop in the currentdesign.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuckGND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" withclock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" withclock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated withformal port "class" of mode "out"------两者不能连接起来13 Warning: Ignored node in vector source file. Can't find corresponding node name"class_sig[2]" indesign.------没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component ---在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does nothold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source filenode.---"temp[19]"被优化掉了18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"------输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binaryoperator "or"22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared-------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。

14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的
21.Warning:Found xx output pins without output pin load capacitance assignment（网友：gucheng82提供）
原因：没有给输出管教指定负载电容
措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告
措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:经过综合器优化后，输出端口已经不起作用了
措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修改:Assignments>Timing analysis settings...>Individual clocks...>...
和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值>multicycle,如设为2和1。