HMD1M32M2EG-7中文资料

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Table 81: Output Driver DC Electrical Characteristics Without ZQ Calibration
RONnom Ω Ω Ω Ω Ω Ω
Resistor RON34PD RON34PU RON40PD RON40PU RON48PD RON48PU RON60PD RON60PU RON80PD RON80PU RON120PD RON120PU
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction.
The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge.
The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses.
Unit RZQ/7 RZQ/7 RZQ/6 RZQ/6 RZQ/5 RZQ/5 RZQ/4 RZQ/4 RZQ/3 RZQ/3 RZQ/2 RZQ/2
Preliminary
1Gb: x16, x32 Automotive Mobile LPDDR2 SDRAM Clock Specification
tJIT(cc) = max of
tCKi + 1 – tCKi

Table 31: MPR Readout Serial Format (Continued)MPR Readout Parallel FormatParallel format implies that the MPR data is returned in the first data UI and then repea-ted in the remaining UIs of the burst, as shown in the table below. Data pattern location0 is the only location used for the parallel format. RD/RDA from data pattern locations1, 2, and 3 are not allowed with parallel data return mode. In this example, the patternprogrammed in the data pattern location 0 is 0111 1111. The x4 configuration only out-puts the first four bits (0111 in this example). For the x16 configuration, the same pat-tern is repeated on both the upper and lower bytes.Table 32: MPR Readout – Parallel Format4Gb: x4, x8, x16 DDR4 SDRAM Multipurpose RegisterTable 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”Table 85: Command and Address Input Levels: DDR4-2666Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200Notes: 1.For input except RESET_n. V REF = V REFCA(DC).2.V REF = V REFCA(DC).3.Input signal must meet V IL /V IH(AC) to meet t IS timings and V IL /V IH(DC) to meet t IH timings.4.The AC peak noise on V REF may not allow V REF to deviate from V REFCA(DC) by more than±1% V DD (for reference: approximately ±12mV).5.Refer to “Overshoot and Undershoot Specifications.”4Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels。

HANBit HMD4M32M2EGGENERAL DESCRIPTIONThe HMD4M32M2E is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of two CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply. All inputs and outputs are TTL-compatible.FEATURESw Part IdentificationHMD4M32M2E----4K Cycles/64ms Ref. SolderHMD4M32M2EG- 4K Cycles/64ms Ref. Goldw Access times : 50, 60nsw High-density 16MByte designw Single +5V± 0.5V power supplyw JEDEC standard pinoutw EDO Mode operationw TTL compatible inputs and outputsw FR4-PCB designOPTIONS MARKINGw Timing50ns access -560ns access -6w Packages72-pin SIMM MPRESENCE DETECT PINSPin 50ns 60nsPD1 Vss VssPD2 NC NCPD3 Vss NCPD4 Vss NC PERFORMANCE RANGESpeed tRAC tCAC tRC tHPC5 50ns 13ns 90ns 26ns6 60ns 15ns 110ns 30ns PIN SYMBOL PIN SYMBOL PIN SYMBOL1 Vss 25 DQ22 49 DQ82 DQ0 26 DQ7 50 DQ243 DQ16 27 DQ23 51 DQ94 DQ1 28 A7 52 DQ255 DQ17 29 A11 53 DQ106 DQ2 30 Vcc 54 DQ267 DQ18 31 A8 55 DQ118 DQ3 32 A9 56 DQ279 DQ19 33 NC 57 DQ1210 Vcc 34 NC 58 DQ2811 NC 35 NC 59 Vcc12 A0 36 NC 60 DQ2913 A1 37 NC 61 DQ1314 A2 38 NC 62 DQ3015 A3 39 Vss 63 DQ1416 A4 40 /CAS0 64 DQ3117 A5 41 /CAS2 65 DQ1518 A6 42 /CAS3 66 NC19 A10 43 /CAS1 67 PD120 DQ4 44 /RAS0 68 PD221 DQ20 45 NC 69 PD322 DQ5 46 NC 70 PD423 DQ21 47 /WE 71 NC24 DQ6 48 NC 72 VssPIN ASSIGNMENTHANBit HMD4M32M2EGFUNCTIONAL BLOCK DIAGRAMTo all DRAMsDQ0-DQ7DQ8-DQ15DQ16-DQ23DQ24-DQ31/RAS0/CAS0/CAS1/CAS2/CAS3/WEA0-A11Vcc Vss0.1u F o r 0.22u F C a p a c i t o r f o r e a c h D R A MHANBit HMD4M32M2EG ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGVoltage on Any Pin Relative to Vss V IN ,OUT-1V to 7.0VVoltage on Vcc Supply Relative to Vss Vcc -1V to 7.0VPower Dissipation P D2WStorage Temperature T STG-55o C to 150o CShort Circuit Output Current I OS50mAw Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS( Voltage reference to V SS, T A=0 to 70 o C )PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage V IH 2.4 - Vcc+1 V Input Low Voltage V IL-1.0 - 0.8 VDC AND OPERATING CHARACTERISTICSSYMBOL SPEED MIN MAX UNITS-5 - 880 mAI CC1-6 - 800 mAI CC2- 16 mA-5 - 880 mAI CC3-6 - 800 mA-5 - 880 mAI CC4-6 - 800 mAI CC5- 8 mA-5 - 880 mAI CC6-6 - 800 mAI l(L)-40 40 µAI O(L)-5 5 µAV OH 2.4 - VV OL- 0.4 VI CC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)I CC2 : Standby Current ( /RAS=/CAS=V IH )HANBit HMD4M32M2EGI CC3 : /RAS Only Refresh Current * ( /CAS=V IH , /RAS, Address cycling @t RC =min ) I CC4 : EDO Mode Current * (/RAS=V IL , /CAS, Address cycling @t PC =min ) I CC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )I CC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC =min ) I IL : Input Leakage Current (Any input 0V ≤ V IN ≤ 6.5V, all other pins not under test = 0V) I OL : Output Leakage Current (Data out is disabled, 0V ≤ V OUT ≤ 5.5V V OH : Output High Voltage Level (I OH = -5mA ) V OL : Output Low Voltage Level (I OL = 4.2mA )* NOTE : I CC1, I CC3, I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. I CC is specified as an average current. In I CC1 and I CC3, address cad be changed maximum once while /RAS=V IL . In I CC4, address can be changed maximum once within one page mode cycle.CAPACITANCE ( T A =25oC, Vcc = 5V, f = 1Mz )DESCRIPTIONSYMBOL MIN MAX UNITS Input Capacitance (A0-A10) C IN1 - 64 pF Input Capacitance (/W) C IN2 - 70 pF Input Capacitance (/RAS0) C IN3 - 42 pF Input Capacitance (/CAS0-/CAS3) C IN4 - 30 pF Input/Output Capacitance (DQ0-31) C DQ1-17pFAC CHARACTERISTICS ( 0 oC ≤ T A ≤ 70o C , Vcc = 5V ±10%, See notes 1,2.)-5-6STANDARD OPERATION SYMBOL MINMAXMIN MAXUNITRandom read or write cycle time t RC 90 110 ns Access time from /RAS t RAC 50 60 ns Access time from /CASt CAC 13 15 ns Access time from column address t AA 25 30 ns /CAS to output in Low-Zt CLZ 3 3 ns Output buffer turn-off delay from /CAS t CEZ 3 13 3 15 ns Transition time (rise and fall) t T 2 50 2 50 ns /RAS precharge time t RP 30 40 ns /RAS pulse width t RAS 50 10K 60 10K ns /RAS hold time t RSH 13 15 ns /CAS hold time t CSH 38 45 ns /CAS pulse width t CAS 8 10K 10 10K ns /RAS to /CAS delay timet RCD 20 37 20 45 ns /RAS to column address delay time t RAD 15 25 15 30 ns /CAS to /RAS precharge timet CRP55nsHANBit HMD4M32M2EGRow address set-up time t ASR0 0 ns Row address hold time t RAH10 10 ns Column address set-up time t ASC0 0 ns Column address hold time t CAH8 10 ns Column address hold referenced to /RAS t AR40 45 ns Column Address to /RAS lead time t RAL25 30 ns Read command set-up time t RCS0 0 ns Read command hold referenced to /CAS t RCH0 0 ns Read command hold referenced to /RAS t RRH0 0 ns Write command hold time t WCH10 10 ns Write command hold referenced to /RAS t WCR40 45 ns Write command pulse width t WP10 10 ns Write command to /RAS lead time t RWL13 15 ns Write command to /CAS lead time t CWL8 10 ns Data-in set-up time t DS0 0 ns Data-in hold time t DH8 10 ns Data-in hold referenced to /RAS t DHR40 45 ns Refresh period t REF64 64 ns Write command set-up time t WCS0 0 ns /CAS to /W delay time t CWD36 40 ns /RAS to /W delay time t RWD73 85 ns /CAS precharge(C-B-R counter test) t CPT20 20 ns Column address to /W delay time t AWD48 55 ns Access time from /CAS precharge t CPA30 35 ns /CAS precharge time (Hyper Page cycle) t CP8 10 ns /RAS pulse width (Hyper Page cycle) t RASP50 200K 60 200K ns /W to /RAS precharge time (C-B-R refresh) t WRP10 10 ns /W to /RAS hold time (C-B-R refresh) t WRH10 10 nsNOTES1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved.2.V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs.3.Measured with a load equivalent to 1TTL loads and 100pF4.Operation within the t RCD(max) limit insures that t RAC(max) can be met. t RCD(max) is specified as a reference point only. If t RCD is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.5.Assumes that t RCD≥ t RCD(max)6. t AR, t WCR, t DHR are referenced to t RAD(max)7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OHHANBit HMD4M32M2EGor V OL.8. t WCS, t RWD, t CWD and t AWD are non restrictive operating parameter.They are included in the data sheet as electrical characteristic only. If t WCS≥tWCS(min) the cycle is an early writecycle and the data out pin will remain high impedance for the duration of the cycle.9. Either t RCH or t RRH must be satisfied for a read cycle.10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-write cycles.11. Operation within the t RAD(max) limit insures that t RAC(max) can be met. t RAD(max) is specified as a referencepoint only. If t RAD is greater than the specified t RAD(max) limit. then access time is controlled by t AA.TIMING DIAGRAMPlease refer to attached timing diagram chart (I)HANBit HMD4M32M2EG0.25 mm MAXPACKAGING INFORMATIONSIMM DesignORDERING INFORMATIONPart NumberDensityOrg.PackageRefresh Cycle VccSPEEDHMD4M32M2EG-5 16MByte 4MX 32bit 72 Pin-SIMM 4,096 Cycles 64ms Ref. 5.0V 50ns HMD4M32M2EG-616MByte4MX 32bit72 Pin-SIMM4,096 Cycles 64ms Ref.5.0V60ns6.2.19.00 m。