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HMD8M32M16EG中文资料

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SIMMTOP VIEWNote: A11 is not used for HMD8M32M16EGGENERAL DESCRIPTIONThe HMD8M32M16EG is a 8M x 32bit dynamic RAM high density memory module. The module consists of sixteen CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.FEATURESw Part IdentificationHMD8M32M16EG- 2048 Cycles/32ms Ref. Gold w Access times : 50, 60ns w High-density 32MByte design w Single + 5V ±0.5V power supply w JEDEC standard PDpin and pinout w EDO mode operationw TTL compatible inputs and outputs w FR4-PCB designOPTIONS MARKINGw Timing50ns access -5 60ns access -6 w Packages72-pin SIMM MPRESENCE DETECT PINSPin 50ns 60ns PD1 NC NC PD2 Vss Vss PD3 Vss NC PD4VssNCPERFORMANCE RANGESpeed tRAC tCAC tRC tHPC 5 50ns 13ns 90ns 26ns 6 60ns15ns110ns30nsPIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vss 25 DQ22 49 DQ8 2 DQ0 26 DQ7 50 DQ24 3 DQ16 27 DQ23 51 DQ9 4 DQ1 28 A7 52 DQ25 5 DQ17 29 NC 53 DQ10 6 DQ2 30 Vcc 54 DQ26 7 DQ18 31 A8 55 DQ11 8 DQ3 32 A9 56 DQ27 9 DQ19 33 NC 57 DQ12 10 Vcc 34 NC 58 DQ28 11 NC 35 NC 59 Vcc 12 A0 36 NC 60 DQ29 13 A1 37 NC 61 DQ13 14 A2 38 NC 62 DQ30 15 A3 39 Vss 63 DQ14 16 A4 40 /CAS0 64 DQ31 17 A5 41 /CAS2 65 DQ15 18 A6 42 /CAS3 66 NC 19 A10 43 /CAS1 67 PD1 20 DQ4 44 /RAS0 68 PD2 21 DQ20 45 /RAS1 69 PD3 22 DQ5 46 NC 70 PD4 23 DQ21 47 /WE 71 NC 24DQ648NC72VssPIN ASSIGNMENTFUNCTIONAL BLOCK DIAGRAM/RAS1ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGVoltage on Any Pin Relative to Vss V IN ,OUT-1V to 7.0VVoltage on Vcc Supply Relative to Vss Vcc -1V to 7.0VPower Dissipation P D16WStorage Temperature T STG-55o C to 150o CShort Circuit Output Current I OS50mAw Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS( Voltage reference to V SS, T A=0 to 70 o C )PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage V IH 2.4 - Vcc+1 V Input Low Voltage V IL-1.0 - 0.8 VDC AND OPERATING CHARACTERISTICSSYMBOL SPEED MIN MAX UNITS-5 - 816 MaI CC1-6 - 736 MAI CC2Don't care - 32 MA-5 - 816 MAI CC3-6 - 736 MA-5 - 896 MAI CC4-6 - 816 MAI CC5Don't care - 16 MA-5 - 816 MAI CC6-6 - 736 MAI l(L)-80 80 µAI O(L)-10 10 µAV OH 2.4 - VV OL- 0.4 VI CC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)I CC2 : Standby Current ( /RAS=/CAS=V IH )I CC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @t RC=min )I CC4 : Fast Page Mode Current * (/RAS=V IL, /CAS, Address cycling @t PC=min )I CC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )I CC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC =min ) I IL : Input Leakage Current (Any input 0V ≤ V IN ≤ 6.5V, all other pins not under test = 0V) I OL : Output Leakage Current (Data out is disabled, 0V ≤ V OUT ≤ 5.5V V OH : Output High Voltage Level (I OH = -5mA ) V OL : Output Low Voltage Level (I OL = 4.2mA )* NOTE : I CC1, I CC3, I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. I CC is specified as an average current. In I CC1 and I CC3, address cad be changed maximum once while /RAS=V IL . In I CC4, address can be changed maximum once within one page mode cycle.CAPACITANCE ( T A =25oC, Vcc = 5V, f = 1Mz )DESCRIPTIONSYMBOL MIN MAX UNITS Input Capacitance (A0-A11) C IN1 - 100 pF Input Capacitance (/W) C IN2 - 130 pF Input Capacitance (/RAS0) C IN3 - 40 pF Input Capacitance (/CAS0-/CAS3) C IN4 - 30 pF Input/Output Capacitance (DQ0-31) C DQ1-20pFAC CHARACTERISTICS ( 0 o C ≤ T A ≤ 70o C , Vcc = 5V ±10%, See notes 1,2.)-5-6 STANDARD OPERATION SYMBOL MINMAXMIN MAXUNITRandom read or write cycle time t RC 90 110ns Access time from /RAS t RAC 50 60 ns Access time from /CASt CAC 13 15 ns Access time from column address t AA 25 30 ns /CAS to output in Low-Z t CLZ 3 3 ns Output buffer turn-off delay t OFF 3 13 3 13 ns Transition time (rise and fall) t T 2 50 2 50 ns /RAS precharge time t RP 30 40 ns /RAS pulse width t RAS 50 10K 60 10K ns /RAS hold time t RSH 13 15 ns /CAS hold time t CSH 38 45 ns /CAS pulse width t CAS 8 10K 10 10K ns /RAS to /CAS delay timet RCD 20 37 20 45 ns /RAS to column address delay time t RAD 15 25 15 30 ns /CAS to /RAS precharge time t CRP 5 5 ns Row address set-up time t ASR 0 0 ns Row address hold time t RAH 10 10 ns Column address set-up timet ASCnsColumn address hold time t CAH8 10 ns Column Address to /RAS lead time t RAL25 30 ns Read command set-up time t RCS0 0 ns Read command hold referenced to /CAS t RCH0 0 ns Read command hold referenced to /RAS t RRH0 0 ns Write command hold time t WCH10 10 ns Write command hold referenced to /RAS t WCR50 55 ns Write command pulse width t WP10 10 ns Write command to /RAS lead time t RWL13 10 ns Write command to /CAS lead time t CWL8 10 ns Data-in set-up time t DS0 0 ns Data-in hold time t DH8 10 ns Refresh period t REF32 32 ns Write command set-up time t WCS0 0 ns/CAS setup time (C-B-R refresh) t CSR 5 5 ns/CAS hold time (C-B-R refresh) t CHR10 10 ns/RAS precharge to /CAS hold time t RPC 5 5 ns Access time from /CAS precharge t CPA30 35 ns/CAS precharge time (Fast page) t CP8 10 ns/RAS pulse width (Fast page ) t RASP50 200K 60 200K nst WRP10 10 ns/W to /RAS precharge time (C-B-Rrefresh)/W to /RAS hold time (C-B-R refresh) t WRH10 10 ns NOTES1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved.2.V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs.3.Measured with a load equivalent to 1TTL loads and 100pF4.Operation within the t RCD(max) limit insures that t RAC(max) can be met. t RCD(max) is specified as a reference point only. If t RCD is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.5.Assumes that t RCD≥ t RCD(max)6. t AR, t WCR, t DHR are referenced to t RAD(max)7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OHor V OL.8. t WCS, t RWD, t CWD and t AWD are non restrictive operating parameter.They are included in the data sheet as electrical characteristic only. If t WCS≥tWCS(min) the cycle is an early writecycle and the data out pin will remain high impedance for the duration of the cycle.9. Either t RCH or t RRH must be satisfied for a read cycle.10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-write cycles.11. Operation within the t RAD(max) limit insures that t RAC(max) can be met. t RAD(max) is specified as a reference point only. If t RAD is greater than the specified t RAD(max) limit. then access time is controlled by t AA .TIMING DIAGRAMSTIMING WAVEFORM OF READ CYCLENOTE/RAS/CASA/W/OE DQ0-DQ7 V V OL /RAS /CAS A /W /OE DQ0-DQ7 V IH- V IL-V IH- V IL- V IH- V IL - V IH- V IL- V IH- V IL-V V V IH- V IL-V IH- V IL- V V V V V IH- V0.25 mm MAXPACKAGING INFORMATIONSIMM DesignORDERING INFORMATIONPart NumberDensityOrg.PackageComponent Number VccAccess TimeHMD8M32M16EG-5 32MByte 8MX 32bit 72Pin-SIMM 16EA 5V 50ns HMD8M32M16EG-6 32MByte8MX 32bit72Pin-SIMM16EA5V60ns。

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MEMORY存储芯片MT48H16M32LFCM-8L中文规格书

MEMORY存储芯片MT48H16M32LFCM-8L中文规格书

Output Driver ImpedanceThe output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is per-formed. Output specifications refer to the default output driver unless specifically sta-ted otherwise. A functional representation of the output buffer is shown below. The out-put driver impedance R ON is defined by the value of the external reference resistor RZQ as follows:•R ON,x = RZQ /y (with RZQ = 240Ω ±1%; x = 34Ω or 40Ω with y = 7 or 6, respectively)The individual pull-up and pull-down resistors R ON(PU) and R ON(PD) are defined as fol-lows:•R ON(PU) = (V DDQ - V OUT )/|I OUT |, when R ON(PD) is turned off•R ON(PD) = (V OUT )/|I OUT |, when R ON(PU) is turned offFigure 24: Output DriverOutput driverChip in drive modeV DDQV SSQV OUTDQ 8Gb: x4, x8, x16 DDR3L SDRAM Output Driver ImpedanceFigure 21: t AON and t AOF DefinitionsCK CK#Begin point: Rising edge of CK - CK#defined by the end point of ODTLonBegin point: Rising edge of CK - CK# defined by the end point of ODTLoffRTT,nomt AONt AOFFigure 22: t AONPD and t AOFPD DefinitionsCK CK#Begin point: Rising edge of CK - CK#DDQ /2Begin point: Rising edge of CK - CK# RTT,nomV SSQ t AONPDt AOFPDFigure 23: t ADC DefinitionCK CK#Begin point: Rising edge of CK - CK# defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK# defined by the end point of ODTLcwn4 or ODTLcwn8。

HMFN16M16M8G中文资料

HMFN16M16M8G中文资料

72-PIN SIMM TOP VIEWGENERAL DESCRIPTIONThe HMFN16M16M8G is a high-speed NAND flash read only memory (FROM) module containing 16,777,216 words organized in a x16bit configuration. The module consists of eight 4M x 8 FROM mounted on a 72-pin, double-sided, FR4-printed circuit board.Data in the page can be read out at 50ns-cycle time per byte.HMFN16M16M8G extended reliability of 1,000,000 program/erase cycles by providing either ECC (Error Correction Code) or real time mapping out algorithm.HMF16M16M8G is has address multiplexed into 16 I/O's . Command, address and data are all written through I/O's bybringing /WE to low while /CE is low. Data is latched on th e rising edge of /WE. Command Latch Enable (CLE) and address Latch Enable (ALE) are used to multiplex comma nd and address respectively, via the I/O pins.FEATURESw High-density 32MByte design w Single + 5V ± 0.5V power supplyw Command/Address/Data Multiplexed I/O port w Organization- Memory Cell Array: (4M+128K)bit x 8bit - Data Register : (512+16)bit x 8bit w Automatic Program and Erase - Page Program: (512+16)Byte - Block Erase: (8K+256)Byte - Status Register w Fast Write Cycle Time - Program time : 250us(typ.) - Block Erase time : 2ms(typ.) w FR4-PCB design w Low profile 72-pin SIMMw Minimum 1,000,000 write/erase cycleOPTIONS MARKINGw Packages72-pin SIMM MPIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vss 25 RB3 49 /CE3 2 I / O0 26 NC 50 /CE3 3 I / O1 27 NC 51 NC 4 I / O2 28 NC 52 NC 5 I / O3 29 NC 53 /WEL 6 I / O4 30 Vcc 54 NC 7 I / O5 31 NC 55 ALE 8 I / O6 32 Vss 56 NC 9 I / O7 33 NC 57 NC 10 Vcc 34 NC 58 NC 11 /CE0 35 /RE 59 Vcc 12 /CE0 36 NC 60 NC 13 NC 37 NC 61 NC 14 /CE1 38 NC 62 NC 15 NC 39 Vss 63 I / O8 16 NC 40 /SE 64 I / O9 17 /WEH 41 NC 65 I / O10 18 NC 42 RB0 66 I / O11 19 CLE 43 RB1 67 I / O12 20 NC 44 NC 68 I / O13 21 NC 45 NC 69 I / O14 22 /WP 46 Vcc 70 I / O15 23 NC 47 NC 71 NC 24RB248/CE272VssPIN ASSIGNMENTFUNCTIONAL BLOCK DIAGRAMI/O(0-15)RB3RB2RB1RB0/SE /RECLE ALE/WP/CE0/CE1/CE2/CE3/WEL/WEHABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATING UNITVoltage on any pin relative to Vss V IN-0.6 to +7.0 V Temperature Under Bias T BIAS-10 to +125 O CStorage Temperature T STG-65 to +150 O CShort Circuit Output Current I OS 5 mAw Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.RECOMMENDED OPERATING CONDITIONS (Voltage reference to Vss, T A=0 to 70O C) PARAMETER SYMBOL MIN TYP. MAXSupply Voltage V CC 4.5V 5.0V 5.5VSupply Voltage V SS0 0 0DC AND OPERATING CHARACTERISTICSAC TEST CONDITON (T A=0 to +70O C, Vcc =5V±10%, unless otherwise noted.)PARAMETER VALUEInput Pulse Levels 0.4V to 2.6VInput Rise and Fall Times 5nsInput and Output Timinig Levels 0.8V and 2.0VOutput Load 1 TTL Gate and CL=100pFCAPACITANCE (TA=25O C, Vcc=5V, f=1.0M HZ)PARAMETER SYMBOL TEST CONDITION MIN MAX UNIT Input/Output Capacitance C I/O V IL=0V - 10 pF Input Capacitance C IN V IN=0V - 10 pF NOTE : Capacitance is periodically sampled and not 100% tested.Note : 1. X can be V IL or V IH2. /WP should be biased to CMOS high or CMOS low for standby3. When /SE is high, spare area is deselected.PROGRAM/ ERASE CHARACTERISTICSPARAMETER SYMBOL MIN TYP. MAX UNIT Program Time t PROG- 0.25 1.5 ms Number of Partial Program Cycles in the SameNop - - 10 Cycles PageBlock Erase Time t BERS- 2 10 msAC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT PARAMETER SYMBOL MIN MAX UNIT CLE Set-up Time t CLS0 - ns CLE Hold Time t CLH10 - ns /CE Setup Time t CS0 - ns /CE Hold Time t CH10 - ns /WE Pulse Width t WP25 - ns ALE Setup Time t ALS0 - ns ALE Hold Time t ALH10 - ns Data Setup Time t DS20 - ns Data Hold Time t DH10 - ns Write Cycle Time t WC50 - ns /WE High Hold Time t WH15 - ns/RE access time (Read ID) t READID- 35 ns Device Resetting Time t RST- 5/10/500/5 us Note: 1. If /CE goes high within 30ns after the rising edge of the last /RE, R//B Will not return to V OL2. The time to Ready depends on the value of the pull-up resistor tied R//B pin3. To break the sequential read cycle, /CE must be held high for longer than t CEH.u READ OPERATIONS TIMINGu RESET TIMINGu PROGRAM OPERATIONS TIMINGu CHIP/SECTOR ERASE OPERATION TIMINGSu DATA# POLLING TIMES(DURING EMBEDDED ALGORITHMS)u TOGGLE# BIT TIMINGS (DURING EMBEDDED ALGORITHMS)u SECTOR PROTECT UNPROTECT TIMEING DIAGRAMu ALTERNATE CE# CONTROLLED WRITE OPERATING TIMINGSHANBit HMFN16M16M8G URL: www.hbe.co.krHANBit Electronics Co., Ltd. REV.02(August,2002) 11PACKAGE DIMENSIONS-ORDERING INFORMATIONPart Number Density Org. Package ComponentNumberVccFunction HMFN16M16M8G32MByte 16MX 16bit 72 Pin-SIMM 8EA 5VNAND,PerfectSector(Solder & Gold Plating)元器件交易网。

美高立产品型号整理

美高立产品型号整理

目 录01 智能测控与保护M200系列电动机保护控制器M500系列电动机保护控制器M400系列智能电力测控仪表02无功补偿与谐波治理MJKW系列无功功率自动补偿控制器MG系列无功补偿滤波装置03智能数显仪表MI系列数显单相电流表MU系列数显单相电压表MI系列数显三相电流表MU系列数显三相电压表MDC系列数显直流表MC系列数显组合表04多功能监控仪表MD系列多功能电力仪表MFD系列多费率电能表MHD系列谐波多功能表MSD系列综合电力监控仪MPD系列电能质量分析仪05电量变送器MBI系列单相电流变送器MBU系列单相电压变送器MBI系列三相电流变送器MBU系列三相电压变送器MBC系列组合变送器MBD系列多功能变送器06电力计量MDL系列导轨式电能表MJD系列简易计量仪表07电气安全MFAS系列电气火灾监控器MFA系列电气火灾监控探测器08开关柜智能操控装置MSC系列开关柜智能操控装置MSC-N系列开关状态显示器09电流互感器过电压保护器MCTB系列电流互感器过电压保护器10微机保护测控装置M300系列数字式保护测控装置M300N系列数字式保护测控装置(经济型)11电力监控系统M8000电力综合监控系统M8100电气火灾监控系统M8200建筑能效管理系统01 智能测控与保护M200系列电动机保护控制器M500系列电动机保护控制器M400系列智能电力测控仪表02无功补偿与谐波治理03智能数显仪表MU系列数显单相电压表MI系列数显三相电流表MU系列数显三相电压表MC系列数显组合表04多功能监控仪表MFD系列多费率电能表05电量变送器06电力计量07电气安全MFAS系列电气火灾监控器MFA系列电气火灾监控探测器08开关柜智能操控装置MSC-N系列开关状态显示器09电流互感器过电压保护器MCTB系列电流互感器过电压保护器10微机保护测控装置M300系列数字式保护测控装置。

高密度八线式接触器说明书

高密度八线式接触器说明书

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