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HMD4M32M8AG-5中文资料

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HANBit HMD4M32M8GGENERAL DESCRIPTIONThe HMD4M32M8G is a 4M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.FEATURESw Part IdentificationHMD4M32M8G- -2,048 Cycles/32ms Ref . GoldHMD4M32M8AG- 4,096 Cycles/64ms Ref . Gold w Access times : 50, 60nsw High-density 16MByte designw Single + 5V ±0.5V power supplyw JEDEC standard pinoutw FP(Fast Page) mode operationw TTL compatible inputs and outputsw FR4-PCB designOPTIONS MARKINGw Timing50ns access -560ns access -6w Packages72-pin SIMM MPERFORMANCE RANGESpeed tRAC tCAC tRC5 50ns 13ns 90ns6 60ns 15ns 110nsPRESENCE DETECT PINSPin 50ns 60nsPD1 Vss VssPD2 NC NCPD3 Vss NCPD4 Vss NC PIN SYMBOL PIN SYMBOL PIN SYMBOL1 Vss 25 DQ22 49 DQ82 DQ0 26 DQ7 50 DQ243 DQ16 27 DQ23 51 DQ94 DQ1 28 A7 52 DQ255 DQ17 29 A11 53 DQ106 DQ2 30 Vcc 54 DQ267 DQ18 31 A8 55 DQ118 DQ3 32 A9 56 DQ279 DQ19 33 NC 57 DQ1210 Vcc 34 /RAS2 58 DQ2811 NC 35 NC 59 Vcc12 A0 36 NC 60 DQ2913 A1 37 NC 61 DQ1314 A2 38 NC 62 DQ3015 A3 39 Vss 63 DQ1416 A4 40 /CAS0 64 DQ3117 A5 41 /CAS2 65 DQ1518 A6 42 /CAS3 66 NC19 A10 43 /CAS1 67 Vss20 DQ4 44 /RAS0 68 PD221 DQ20 45 NC 69 PD322 DQ5 46 NC 70 PD423 DQ21 47 /WE 71 NC24 DQ6 48 NC 72 VssA0 – A11 : Address Input(4K Ref.)A0 – A10 : Address Input(2K Ref.)*Note : A11 is used for only HMD4M32M8AGPIN ASSIGNMENTHANBit HMD4M32M8G FUNCTIONAL BLOCK DIAGRAMVccVss 0.1u F o r0.22u F C a p a c i t o rf o r e a c h D R A MTo all DRAMsDQ0-DQ3DQ4-DQ7DQ8-DQ11DQ12-DQ15DQ16-DQ19DQ20-DQ23DQ24-DQ27DQ28-DQ31/CAS0/RAS0/CAS1/CAS2/CAS3/WE A0-A10(A11)/RAS2HANBit HMD4M32M8G ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGVoltage on Any Pin Relative to Vss V IN ,OUT-1V to 7.0VVoltage on Vcc Supply Relative to Vss Vcc -1V to 7.0VPower Dissipation P D8WStorage Temperature T STG-55o C to 150o CShort Circuit Output Current I OS50mAw Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS( Voltage reference to V SS, T A=0 to 70 o C )PARAMETER SYMBOL MIN TYP MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage V IH 2.4 - Vcc+1 V Input Low Voltage V IL-1.0 - 0.8 VDC AND OPERATING CHARACTERISTICSSYMBOL SPEED MIN MAX UNITSI CC1-5-6--880800mAmAI CC2- 16 mAI CC3-5-6--880800mAmAI CC4-5-6--720640mAmAI CC5- 8 mAI CC6-5-6--880800mAmAI l(L) I O(L)-40-5405µAµAV OH V OL 2.4--0.4VVI CC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.)I CC2 : Standby Current ( /RAS=/CAS=V IH )I CC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @t RC=min ) I CC4 : Fast Page Mode Current * (/RAS=V IL, /CAS, Address cycling @t PC=min )I CC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )I CC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )HANBit HMD4M32M8GI IL : Input Leakage Current (Any input 0V ≤ V IN ≤ 6.5V, all other pins not under test = 0V) I OL : Output Leakage Current (Data out is disabled, 0V ≤ V OUT ≤ 5.5V V OH : Output High Voltage Level (I OH = -5mA ) V OL : Output Low Voltage Level (I OL = 4.2mA )* NOTE : I CC1, I CC3, I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. I CC is specified as an average current. In I CC1 and I CC3, address cad be changed maximum once while /RAS=V IL . In I CC4, address can be changed maximum once within one page mode cycle.CAPACITANCE ( T A =25oC, Vcc = 5V, f = 1Mz )DESCRIPTIONSYMBOL MIN MAX UNITS Input Capacitance (A0-A10) C IN1 - 64 pF Input Capacitance (/W)C IN2 - 70 pF Input Capacitance (/RAS0,/RAS2) C IN3 - 70 pF Input Capacitance (/CAS0-/CAS3) C IN4 - 36 pF Input/Output Capacitance (DQ0-31) C DQ1-17pFAC CHARACTERISTICS ( 0 oC ≤ T A ≤ 70o C , Vcc = 5V ±10%, See notes 1,2.)-5 -6STANDARD OPERATIONSYMBOLMINMAX MIN MAX UNITRandom read or write cycle time t RC 90 110 ns Access time from /RAS t RAC 50 60 ns Access time from /CASt CAC 13 15 ns Access time from column address t AA 25 30ns /CAS to output in Low-Z t CLZ 0 0 ns Output buffer turn-off delay t OFF 0 13 0 15 ns Transition time (rise and fall) t T 3 50 3 50 ns /RAS precharge time t RP 30 40 ns /RAS pulse width t RAS 50 10K 60 10K ns /RAS hold time t RSH 13 15 ns /CAS hold time t CSH 50 60 ns /CAS pulse width t CAS 13 10K 15 10K ns /RAS to /CAS delay timet RCD 20 37 20 45 ns /RAS to column address delay time t RAD 15 25 15 30 ns /CAS to /RAS precharge time t CRP 5 5 ns Row address set-up time t ASR 0 0 ns Row address hold time t RAH 10 10 ns Column address set-up time t ASC 0 0 ns Column address hold timet CAH1010nsHANBit HMD4M32M8GColumn address hold referenced to /RAS t AR40 45 ns Column Address to /RAS lead time t RAL25 30 ns Read command set-up time t RCS0 0 ns Read command hold referenced to /CAS t RCH0 0 ns Read command hold referenced to /RAS t RRH0 0 ns Write command hold time t WCH10 10 ns Write command hold referenced to /RAS t WCR40 45 ns Write command pulse width t WP10 10 ns Write command to /RAS lead time t RWL15 15 ns Write command to /CAS lead time t CWL13 15 ns Data-in set-up time t DS0 0 ns Data-in hold time t DH10 15 ns Data-in hold referenced to /RAS t DHR40 45 ns Refresh period 2K Ref. t REF32 32 ns Write command set-up time t WCS0 0 ns/CAS setup time (C-B-R refresh) t CSR 5 5 ns/CAS hold time (C-B-R refresh) t CHR10 10 ns/RAS precharge to /CAS hold time t RPC 5 5 ns Access time from /CAS precharge t CPA30 35 ns Fast page mode cycle time t PC35 40 ns/CAS precharge time (Fast page) t CP10 10 ns/RAS pulse width (Fast page ) t RASP50 200K 60 200K ns/W to /RAS precharge time (C-B-R refresh) t WRP10 10 ns/W to /RAS hold time (C-B-R refresh) t WRH10 10 ns/CAS precharge(C-B-R counter test) t CPT20 20 ns NOTES1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved.2.V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs.3.Measured with a load equivalent to 2TTL loads and 100pF4.Operation within the t RCD(max) limit insures that t RAC(max) can be met. t RCD(max) is specified as a reference point only. If t RCD is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.5.Assumes that t RCD≥ t RCD(max)6. t AR, t WCR, t DHR are referenced to t RAD(max)7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or V OL.8. t WCS, t RWD, t CWD and t AWD are non restrictive operating parameter.They are included in the data sheet as electrical characteristic only. If t WCS≥tWCS(min) the cycle is an early writecycle and the data out pin will remain high impedance for the duration of the cycle.HANBit HMD4M32M8G9. Either t RCH or t RRH must be satisfied for a read cycle.10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read- write cycles.11. Operation within the t RAD(max) limit insures that t RAC(max) can be met. t RAD(max) is specified as a reference point only. If t RAD is greater than the specified t RAD(max) limit. then access time is controlled by t AA .TIMING DIAGRAMPlease refer to attached timing diagram chart (I)PACKAGING INFORMATIONSIMM Design ( Unit : mm)0.10mmHANBit HMD4M32M8G ORDERING INFORMATIONPart Number Density Org. Package RefreshCycleVcc SPEEDHMD4M32M8G-5 16MByte 4MX 32bit 72 Pin-SIMM 2,048 Cycles32ms Ref.5.0V 50nsHMD4M32M8AG-5 16MByte 4MX 32bit72 Pin-SIMM 4,096 Cycle64ms Ref.5.0V 50nsHMD4M32M8G-6 16MByte 4MX 32bit72 Pin-SIMM 2,048 Cycles32ms Ref.5.0V 60nsHMD4M32M8AG-6 16MByte 4MX 32bit72 Pin-SIMM 4,096 Cycle64ms Ref.5.0V 60ns。

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注塑机参数-海天天隆

注塑机参数-海天天隆

海天MA系列地址：中国宁波市北仑区小港江南中路32号ADD: No.32 Jiangnan Zhong Road, Xiaogang, Beilun, Ningbo , P.R, China.邮编 Zipcode:315821电话T el: +86-574-86177005 86177242HT71225-CV海天分公司：海天MA系列海天天隆MA系列伺服节能注塑机海天天隆系列-MA 1200/370海天天隆系列-MA 2800/1350共 创 卓 越：在传承了海天天翔SA系列所有优秀性能的基础上，海天天隆MA系列采用了自主创新研制的高性能伺服动力驱动系统，在提升精度、提高效率的同时，最大限度的满足了客户对节电、节水的要求。

海天天隆MA系列以其环保节能的有效品质得到了市场好评，被誉为“对传统液压注塑机进行了一次彻底的革命。

”填补了全液压注塑机与全电动注塑机之间的行业空白。

超效节能» 在同等工作状态下，相较传统液压注塑机能实现20%-80%的节能率超佳成型稳定性» 伺服驱动系统，闭环控制，相较传统液压注塑机，成型重复精度大幅提高超灵敏响应性» 灵敏伺服驱动系统响应迅速，快速启动时间仅需0.05S超性能环保» 整机运行低噪音，低速运行更宁静超可靠保压性能» 相较传统液压注塑机，保压时间调整范围更宽泛，保压性能更稳定超恒定油温» 伺服电机比例输出液压油，避免多余热量产生，低温升，液压油甚至不需冷却，实现大幅节水MA系列个性化选择海天天隆MA系列传承海天天翔SA系列的优秀性能，运用自主创新的伺服驱动系统，实现了革命性的突破，有效提升了成型精度，最大限度地降低了能耗。

锁模单元：优化设计的斜排五支点双曲肘式的锁模结构，有效传递强大动力，确保开关模时的高速响应。

快速关模平台更是缩短了成型周期，提高了生产效率。

注射单元：优化设计的注射单元提供更高的精度，确保了更高的稳定性。

浩美高功率无线电驱动器数据手册说明书

浩美高功率无线电驱动器数据手册说明书

Characteristic / Test ConditionsDrain-Source Breakdown Voltage (V GS = 0V, I D = 250µA)On State Drain Current 2 (V DS > I D(on) x R DS(on) Max, V GS = 10V)Drain-Source On-State Resistance 2 (V GS = 10V, 0.5 I D[Cont.])Zero Gate Voltage Drain Current (V DS = V DSS , V GS= 0V)Zero Gate Voltage Drain Current (VDS = 0.8 V DSS , V GS = 0V, T C = 125°C)Gate-Source Leakage Current (V GS = ±30V, V DS = 0V)Gate Threshold Voltage (V DS = V GS , I D = 1.0mA)050-5572 Re v CMAXIMUM RATINGSAll Ratings: T C = 25°C unless otherwise specified.Symbol V DSS I D I DM V GS V GSM P D T J ,T STGT L I AR E AR E ASParameterDrain-Source VoltageContinuous Drain Current @ T C = 25°C Pulsed Drain Current 1Gate-Source Voltage Continuous Gate-Source Voltage Transient Total Power Dissipation @ T C = 25°C Linear Derating FactorOperating and Storage Junction Temperature Range Lead Temperature: 0.063" from Case for 10 Sec.Avalanche Current 1 (Repetitive and Non-Repetitive)Repetitive Avalanche Energy 1Single Pulse Avalanche Energy 4UNIT Volts AmpsVolts Watts W/°C °C Amps mJSTATIC ELECTRICAL CHARACTERISTICSSymbol BV DSS I D(on)R DS(on)I DSS I GSS V GS(th)UNIT Volts AmpsOhms µA nA VoltsMIN TYP MAX 1000111.0025250±10024APT1001RBVR10001144±30±402802.24-55 to 15030011301210APT1001RBVR1000V11A 1.000ΩPower MOS V ® is a new generation of high voltage N-Channel enhancement mode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS V ®also achieves faster switching speeds through optimized gate layout.•Faster Switching •100% Avalanche Tested •Lower Leakage•Popular TO-247 PackagePOWER MOS V ®CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.USA405 S.W. Columbia StreetBend, Oregon 97702-1035Phone: (541) 382-8028FAX: (541) 388-0364EUROPEAvenue J.F. Kennedy Bât B4 Parc Cadéra NordF-33700 Merignac - FrancePhone: (33)557921515FAX: (33)556479761APT Website - Symbol I S I SM V SD t rr Q rrDYNAMIC CHARACTERISTICSSymbol C iss C oss C rss Q g Q gs Q gd t d(on)t r t d(off)t fTest ConditionsV GS = 0V V DS = 25V f = 1 MHz V GS = 10V V DD = 0.5 V DSS I D = I D[Cont.] @ 25°CV GS = 15V V DD = 0.5 V DSS I D = I D[Cont.] @ 25°CR G = 1.6ΩMINTYPMAX305036602803901352001502251624701051224112255851224UNITpFnC ns APT1001RBVRCharacteristic Input Capacitance Output CapacitanceReverse Transfer Capacitance Total Gate Charge 3Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise TimeTurn-off Delay Time Fall Time050-5572 R e v CCharacteristic / Test Conditions Continuous Source Current (Body Diode)Pulsed Source Current 1 (Body Diode)Diode Forward Voltage 2 (V GS = 0V, I S = -I D[Cont.])Reverse Recovery Time (I S = -I D[Cont.], dl S /dt = 100A/µs)Reverse Recovery Charge (I S = -I D[Cont.], dl S /dt = 100A/µs)SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICSUNIT Amps Volts ns µCMINTYPMAX11441.370091Repetitive Rating: Pulse width limited by maximum junction3See MIL-STD-750 Method 3471temperature.4Starting T j = +25°C, L = 20mH, R G = 25Ω, Peak I L= 11A2Pulse Test: Pulse width < 380 µS, Duty Cycle < 2%APT Reserves the right to change, without notice, the specifications and information contained herein.THERMAL CHARACTERISTICSSymbol R θJC R θJAMINTYPMAX0.4540UNIT °C/WCharacteristic Junction to Case Junction to AmbientZ θJ C , T H E R M A L I M P E D A N C E (°C /W )10-510-410-310-210-1 1.010RECTANGULAR PULSE DURATION (SECONDS)FIGURE 1, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION0.50.10.050.010.0050.001V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)FIGURE 2, TYPICAL OUTPUT CHARACTERISTICS FIGURE 3, TYPICAL OUTPUT CHARACTERISTICS V GS , GATE-TO-SOURCE VOLTAGE (VOLTS)I D , DRAIN CURRENT (AMPERES)FIGURE 4, TYPICAL TRANSFER CHARACTERISTICS FIGURE 5, R DS (ON) vs DRAIN CURRENTT C , CASE TEMPERATURE (°C)T J , JUNCTION TEMPERATURE (°C)FIGURE 6, MAXIMUM DRAIN CURRENT vs CASE TEMPERATURE FIGURE 7, BREAKDOWN VOLTAGE vs TEMPERATURE T J , JUNCTION TEMPERATURE (°C)T C , CASE TEMPERATURE (°C)FIGURE 8, ON-RESISTANCE vs. TEMPERATURE FIGURE 9, THRESHOLD VOLTAGE vs TEMPERATURER D S (O N ), D R A I N -T O -S O U R C E O N R E S I S T A N C E I D , D R A I N C U R R E N T (A M P E R E S )I D , D R A I N C U R R E N T (A M P E R E S )I D , D R A I N C U R R E N T (A M P E R E S )(N O R M A L I Z E D )V G S (T H ), T H R E S H O L D V O L T A G E B V D S S , D R A I N -T O -S O U R C E B R E A K D O W N R D S (O N ), D R A I N -T O -S O U R C E O N R E S I S T A N C EI D , D R A I N C U R R E N T (A M P E R E S )(N O R M A L I Z E D )V O L T A G E (N O R M A L I Z E D)255075100125150-50-250255075100125150-50-250255075100125150APT1001RBVR201612841.51.41.21.00.81.151.101.051.000.950.901.21.11.00.90.80.70.6201612840403020101210864202.52.01.51.00.50.0050-5572 R e v CV DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)FIGURE 10, MAXIMUM SAFE OPERATING AREAFIGURE 11, TYPICAL CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE Q g , TOTAL GATE CHARGE (nC)V SD , SOURCE-TO-DRAIN VOLTAGE (VOLTS)FIGURE 12, GATE CHARGES vs GATE-TO-SOURCE VOLTAGEFIGURE 13, TYPICAL SOURCE-DRAIN DIODE FORWARD VOLTAGEV G S , G A T E -T O -S O U R C E V O L T A G E (V O L T S )I D , D R A I N C U R R E N T (A M P E R E S )I D R , R E V E R S E D R A I N C U R R E N T (A M P E R E S )C , C A P A C I T A N C E (p F )Dimensions in Millimeters and (Inches)APT1001RBVR501051.5.12016128411,0005,0001,00050010050501051.5.1050-5572 R e v CAPT's devices are covered by one or more of the following U.S.patents:4,895,8105,045,9035,089,4345,182,2345,019,5225,262,3365,256,5834,748,1035,283,2025,231,4745,434,0955,528,058TO-247 Package Outline。

MEMORY存储芯片MT47R128M8CF-25 H中文规格书

MEMORY存储芯片MT47R128M8CF-25 H中文规格书

Temperature-Controlled Refresh ModeDuring normal operation, temperature-controlled refresh (TCR) mode disabled, the de-vice must have a REFRESH command issued once every t REFI, except for what is al-lowed by posting (see REFRESH Command section). This means a REFRESH command must be issued once every 7.8μs if T C is less than or equal to 85°C, once every 3.9μs if T C is greater than 85°C, once every 1.95μs if T C is greater than 95°C, regardless of which Temperature Mode is selected (MR4[2]). TCR mode is disabled by setting MR4[3] = 0while TCR mode is enabled by setting MR4[3] = 1. When TCR mode is enabled (MR4[3]= 1), the Temperature Mode must be selected where MR4[2] = 0 enables the Normal Temperature Mode while MR4[2] = 1 enables the Extended Temperature Mode.When TCR mode is enabled, the device will register the externally supplied REFRESH command and adjust the internal refresh period to be longer than t REFI of the normal temperature range, when allowed, by skipping REFRESH commands with the proper gear ratio. TCR mode has two Temperature Modes to select between the normal tem-perature range and the extended temperature range; the correct Temperature Mode must be selected so the internal control operates correctly. The DRAM must have the correct refresh rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature.Normal Temperature ModeREFRESH commands should be issued to the device with the refresh period equal to t REFI of normal temperature range (-40°C to 85°C). The system must guarantee that the T C does not exceed 85°C when t REFI of the normal temperature range is used. The de-vice may adjust the internal refresh period to be longer than t REFI of the normal tem-perature range by skipping external REFRESH commands with the proper gear ratio when T C is below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control.Extended Temperature ModeREFRESH commands should be issued to the device with the refresh period equal to t REFI of extended temperature range (85°C to 95°C, or 95°C to 105°C) . The system must guarantee that the T C does not exceed 95°C, or 105°C. Even though the external refresh supports the extended temperature range, the device may adjust its internal refresh pe-riod to be equal to or longer than t REFI of the normal temperature range (-40°C to 85°C)by skipping external REFRESH commands with the proper gear ratio when T C is equal to or below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control.Table 49: Normal t REFI Refresh (TCR Enabled)8Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh ModeRAS lockout circuit feature allows the PRECHARGE operation to be partially or com-pletely hidden during burst READ cycles when the auto precharge feature is engaged.The PRECHARGE operation will not begin until after the last data of the burst write se-quence is properly stored in the memory array.REFRESH CommandThe REFRESH command (REF) is used during normal operation of the device. This command is nonpersistent, so it must be issued each time a refresh is required. The de-vice requires REFRESH cycles at an average periodic interval of t REFI. When CS_n,RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be pre-charged and idle for a minimum of the precharge time, t RP (MIN), before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM re-fresh controller. This makes the address bits “Don’t Care” during a REFRESH command.An internal address counter supplies the addresses during the REFRESH cycle. No con-trol of the external address bus is required once this cycle has started. When the RE-FRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle)state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time t RFC (MIN),as shown in Figure 84 (page 147).Note: The t RFC timing parameter depends on memory density.In general, a REFRESH command needs to be issued to the device regularly every t REFI interval. To allow for improved efficiency in scheduling and switching between tasks,some flexibility in the absolute refresh interval is provided for postponing and pulling-in the REFRESH command. A limited number REFRESH commands can be postponed depending on refresh mode: a maximum of 8 REFRESH commands can be postponed when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH commands can be postponed when the device is in 4X refresh mode.When 8 consecutive REFRESH commands are postponed, the resulting maximum inter-val between the surrounding REFRESH commands is limited to 9 × t REFI (see Figure 85(page 147)). For both the 2X and 4X refresh modes, the maximum interval between sur-rounding REFRESH commands allowed is limited to 17 × t REFI2 and 33 × t REFI4, re-spectively.A limited number REFRESH commands can be pulled-in as well. A maximum of 8 addi-tional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode,a maximum of 16 additional REFRESH commands can be issued when in advance in 2X refresh mode, and a maximum of 32 additional REFRESH commands can be issued in advance when in 4X refresh mode. Each of these REFRESH commands reduces the number of regular REFRESH commands required later by one. The resulting maximum interval between two surrounding REFRESH commands is limited to 9 × t REFI (Fig-ure 86 (page 147)), 17 × t RFEI2, or 33 × t REFI4. At any given time, a maximum of 16 REF commands can be issued within 2 × t REFI, 32 REF2 commands can be issued within 4 ×t REFI2, and 64 REF4 commands can be issued within 8 × t REFI4 (larger densities are limited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met).8Gb: x4, x8, x16 DDR4 SDRAM REFRESH CommandFigure 84: REFRESH Command TimingCK_tCK_cCommand Don’t CareNotes: 1.Only DES commands are allowed after a REFRESH command is registered until t RFC(MIN) expires.2.Time interval between two REFRESH commands may be extended to a maximum of 9 ×t REFI.Figure 85: Postponing REFRESH Commands (Example)WFigure 86: Pulling In REFRESH Commands (Example)W8 REF-Commands pulled-in8Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command。

AD404M48RLA-5中文资料

AD404M48RLA-5中文资料

ASCEND Semiconductor 4Mx4 EDO Data sheetDescriptionThe device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features• Single 3.3V(%) only power supply • High speed t RAC acess time: 50/60ns • Low power dissipation- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)• Extended - data - out(EDO) page mode access • I/O level: CMOS level (Vcc = 3.3V)• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh- CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)10±Pin Name FunctionA0-A10Address inputs- Row address - Column address - Refresh address DQ1~DQ4Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V)VssGroundVCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7A6A5A4VSSAD404M42VSPin Description Pin Configuration21222324 2526151416 A1026/24-PIN 300mil Plastic SOJA9VCC 1DQ12DQ23DQ34DQ45VCC6891011 NC 12 WE 13A0 A117 A218 A319VSS RAS CAS OE A8A7 A6A5 A4VSSAD404M42VT212223242526151416 A1026/24-PIN 300mil Plastic TSOP (ll)A9A0-A10A0-A10A0-A10WECASNO. 2 CLOCK GENERATORCOLUMN ADDRESS BUFFERS (11)REFRESH CONTROLLERREFRESH COUNTERBUFFERS (11)ADDRESS ROW NO. 1 CLOCK GENERATORA0RASA1A2A3A4A5A6A7A8CONTROLLOGICDATA-IN BUFFERDATA-OUT BUFFEROEDQ1.DQ4.COLUMN DECODER2048SENSE AMPLIFIERSI/O GATING2048x42048x2048x4MEMORY ARRAY2048R O W D E C O D E RVcc VssBlock DiagramA9A10TRUTH TABLENotes: 1. EARLY WRITE only.FUNCTIONRASCAS WE OE ADDRESSESDQ SNotesROW COL STANDBY H X X X X High-Z READL L H L ROW COL Data-Out WRITE: (EARLY WRITE )L L L X ROW COL Data-lnREAD WRITE L L ROW COL Data-Out,Data-ln EDO-PAGE-MODE READ1st Cycle L H L ROW COL Data-Out 2nd CycleL H L n/a COL Data-Out EDO-PAGE MODE WRITE1st CycleL L X ROW COL Data-In 2nd Cycle L L Xn/a COL Data-InEDO-PAGE-MODEREAD-WRITE 1st Cycle L ROW COL Data-Out, Data-In 2nd Cycle L n/a COL Data-Out, Data-In HIDDEN REFRESHREAD L H L ROW COL Data-Out WRITEL L X ROW COL Data-In 1RAS-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESHLHXXXHigh-ZH X →H L →L H →H L →H L →H L →H L →H L →H L →L H →H L →H L →L H→L H L →→L H L→→H L→Absolute Maximum RatingsRecommended DC Operating ConditionsCapacitanceTa = 25°C, V CC = 3.3V%, f = 1MHz Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.ParameterSymbol Value Unit Voltage on any pin relative to Vss V T -0.5 to + 4.6V Supply voltage relative to Vss V CC -0.5 to + 4.6V Short circuit output current I OUT 50mA Power dissipation P D 1.0WOperating temperature T OPT 0 to + 70°C Storage temperatureT STG-55 to + 125°CParameter/Condition Symbol3.3 Volt VersionUnitMinTyp MaxSupply VoltageV CC 3.0 3.33.6V Input High Voltage, all inputs V IH 2.0-V CC + 0.3V Input Low Voltage, all inputsV IL-0.3-0.8VParameterSymbol Typ Max Unit Note Input capacitance (Address)C I1 -5pF 1Input capacitance (RAS, CAS, OE, WE)C I2-7pF 1Output capacitance(Data-in, Data-out)C I/O-7pF1, 210±DC Characteristics :(T a = 0 to 70°C, V CC = + 3.3V%, V SS = 0V)Parameter Symbol Test Conditions AD404M42V Unit Notes-5-6Min Max Min MaxOperating current I CC1RAS cyclingCAS, cyclingt RC = min-120-110mA1, 2Standby Current LowpowerS-versionI CC2LVTTL interfaceRAS, CAS = V IHDout = High-Z-0.5-0.5mACMOS interfaceRAS, -0.2VDout = High-Z-0.15-0.15mAStandardpowerversionLVTTL interfaceRAS, CAS = V IHDout = High-Z-2-2mACMOS interfaceRAS,-0.2VDout = High-Z-0.5-0.5mARAS- only refresh current I CC3RAS cycling, CAS = V IHt RC = min-120-110mA1, 2 EDO page mode current I CC4t PC = min-90-80mA1, 3CAS- before- RAS refresh current I CC5t RC = minRAS, CAS cycling-120-110mA1, 2Self- refresh current (S-Version)I CC8 - 550 - 55010±CAS V CC≥CAS V CC≥t RASS100µs≥µADC Characteristics :(T a = 0 to 70°C , V CC = +3.3V %, V SS = 0V)Notes:1. I CC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. I CC max is specified at the output open condition.2. Address can be changed once or less while RAS = V IL .3. For I CC4, address can be changed once or less within one EDO page mode cycle time.Parameter Symbol Test Conditions AD404M42VUnitNotes-5-6Min MaxMin MaxInput leakage current I LI + 0.3V -55-55Output leakage current I LO + 0.3V Dout = Disable -55-55Output high Voltage V OH I OH = -2mA 2.4- 2.4-V Output low voltage V OLI OL = +2mA-0.4-0.4V10±0V Vin V CC ≤≤µA 0V Vout V CC ≤≤µAAC Characteristics(T a = 0 to + 70°C , V cc = 3.3V %, V ss = 0V) *1, *2, *3, *4Test conditions• Output load: one TTL Load and 100pF (V CC = 3.3V %)• Input timing reference levels:V IH = 2.0V, V IL = 0.8V (V CC = 3.3V %)• Output timing reference levels:V OH = 2.0V, V OL = 0.8V10±10±10±Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters)ParameterSymbol AD404M42V UnitNotes-5-6Min MaxMin MaxRandom read or write cycle time t RC 84-104-ns RAS precharge timet RP 30-40-ns CAS precharge time in normal mode t CPN 10-10-ns RAS pulse width t RAS 50100006010000ns 5CAS pulse width t CAS 8100001010000ns 6Row address setup time t ASR 0-0-ns Row address hold time t RAH 8-10-ns Column address setup time t ASC 0-0-ns 7Column address hold time t CAH 8-10-ns RAS to CAS delay timet RCD 12371445ns 8RAS to column address delay time t RAD 10251230ns 9Column address to RAS lead time t RAL 25-30-ns RAS hold time t RSH 8-10-ns CAS hold timet CSH 38-40-ns CAS to RAS precharge time t CRP 5-5-ns 10OE to Din delay time t OED 12-15-ns Transition time (rise and fall)t T 150150ns 11Refresh periodt REF -32-32ms Refresh period (S- Version)t REF -128-128ms CAS to output in Low- Z t CLZ 0-0-ns CAS delay time from Din t DZC 0-0-ns OE delay time from Dint DZO-0-nsRead CycleWrite Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxAccess time from RAS t RAC-50-60ns12 Access time from CAS t CAC-14-15ns13, 14 Access time from column address t AA-25-30ns14, 15 Access time from OE t OEA-12-15nsRead command setup time t RCS0-0-ns7 Read command hold time to CAS t RCH0-0-ns10, 16 Read command hold time to RAS t RRH0-0-ns16 Output buffer turn-off time t OFF012015ns17 Output buffer turn-off time from OE t OEZ012015ns17Parameter SymbolAD404M42V Unit Notes -5-6Min Max Min MaxWrite command setup time t WCS0-0-ns7, 18 Write command hold time t WCH8-10-nsWrite command pulse width t WP8-10-nsWrite command to RAS lead time t RWL13-15-nsWrite command to CAS lead time t CWL8-10-nsData-in setup time t DS0-0-ns19 Data-in hold time t DH8-10-ns19 WE to Data-in delay t WED10-10-nsRead- Modify- Write CycleRefresh Cycle Parameter SymbolAD404M42V Unit Notes-5-6Min Max Min MaxRead-modify- write cycle time t RWC108-133-nsRAS to WE delay time t RWD64-77-ns18 CAS to WE dealy time t CWD26-32-ns18 Column address to WE delay time t AWD39-47-ns18 OE hold time from WE t OEH8-10-nsParameter SymbolAD404M42VUnit Notes -5-6Min Max Min MaxCAS setup time (CBR refresh) t CSR5-5-nsCAS hold time (CBR refresh)t CHR8-10-ns10 RAS precharge to CAS hold time t RPC5-5-ns7 RAS pulse width (self refresh)t RASS100-100-RAS precharge time (self refresh)t RPS90-110-nsCAS hold time (CBR self refresh)t CHS-50--50-nsWE setup time t WSR0-0-nsWE hold time t WHR10-10-nsµsEDO Page Mode CycleEDO Page Mode Read Modify Write CycleParameterSymbol AD404M42VUnit Notes-5-6Min MaxMin MaxEDO page mode cycle timet PC 20-25-ns EDO page mode CAS precharge time t CP 10-10-ns EDO page mode RAS pulse width t RASP 5010560105ns 20Access time from CAS precharge t CPA -30-35ns 10, 14RAS hold time from CAS precharge t CPRH 30-35-ns OE high hold time from CAS high t OEHC 5-5-ns OE high pulse widtht OEP 10-10-ns Data output hold time after CAS low t COH 5-5-ns Output disable delay from WEt WHZ 310310ns WE pulse width for output disable whenCAS hight WPZ7-7-nsParameterSymbol AD404M42V Unit Notes -5-6Min MaxMin MaxEDO page mode read- modify- write cycle CAS precharge to WE delay timet CPW 45-55-ns 10EDO page mode read- modify- write cycle timet PRWC56-68-nsNotes :1. AC measurements assume t T = 2ns.2. An initial pause of 100 is required after power up, and it followed by a minimum of eightinitialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device.4. All the V CC and V SS pins shall be supplied with the same voltages.5. t RAS (min) = t RWD (min)+t RWL (min)+t T in read-modify-write cycle.6. t CAS (min) = t CWD (min)+t CWL (min)+t T in read-modify-write cycle.7. t ASC (min), t RCS (min), t WCS (min), and t RPC are determined by the falling edge of CAS .8. t RCD (max) is specified as a reference point only, and t RAC (max) can be met with the t RCD (max) limit.Otherwise, t RAC is controlled exclusively by t CAC if t RCD is greater than the specified t RCD (max) limit. 9. t RAD (max) is specified as a reference point only, and t RAC (max) can be met with the t RAD (max) limit.Otherwise, t RAC is controlled exclusively by t AA if t RAD is greater than the specified t RAD (max) limit. 10. t CRP , t CHR , t RCH , t CPA and t CPW are determined by the rising edge of CAS .11. V IH (min) and V IL (max) are reference levels for measuring timing or input signals. Therefore, transitiontime is measured between V IH and V IL .12. Assumes that t RCD tRCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 13. Assumes that (max) and (max).14. Access time is determined by the maximum of t AA , t CAC , t CPA . 15. Assumes that (max) and (max). 16. Either t RCH or t RRH must be satisfied for a read cycle.17. t OFF (max) and t OEZ (max) define the time at which the output achieves the open circuit condition (highimpedance). t OFF is determined by the later rising edge of RAS or CAS.18. t WCS , t RWD , t CWD , and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If (min),(min), (min) and (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate.19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in adelayed write or a read-modify-write cycle.20. t RASP defines RAS pulse width in EDO page mode cycles.µs ≤≤t RCD t RCD ≥t RADt RAD ≤t RCD t RCD ≤t RAD t RAD ≥t WCS t WCS ≥t RWD t RWD ≥t CWDt CWD ≥t AWD t AWD ≥t CPW t CPW≥Timing Waveforms• Read Cyclet RC t RASt RPtCRPtCPNtRRHtRCHt OEZ t OFF tOEA tCACt AAtRACt CLZD OUTtRCS t ASR tRAH tASC tCAH tRAD t RALtCAStRSH tRCDt TtCSHRASCASADDRESSWEDQ1~DQ4Note : = don’t care OEt OFFRowColumn= Invalid Dout•Early Write CycletRC t RASt RPt WCHt DSt DHt WCS t RALtCAStRSH tRCDt TtCSHRASCASWEDQ1~DQ4tCRPtASRtRAH tASCtCAH ADDRESSColumnRowtCPND INtRADt RAL• Delayed Write CycletRC t RASt RPt RWL t RCSt CAStRSH tRCDt TtCSHRASCAStASR tRAH tCAHADDRESSColumnRow tASC D INDQ1~DQ4WEtCRPtCPNt DHt DSt OEHt OEDOEt DSOPENt WPt CWL• Read - Modify - Write CycletRWC t RASt RPtRWDt WPtRADtRWL tCAStCWL tRCDt TtCPNRASCASWEtCRP t ASRtRAHtASCtCAHADDRESS Column RowDQ1~DQ4t DHt DSOEtRCStAWD tCWD D INt OEDt OEHt OEZt OEA t CAC t RACt AADQ1~DQ4D OUTOPENtDZCtDZO• EDO Page Mode Read CycletRASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtOEPD OUT 1t PCt CPtCAStCPNtCRPtRADtCAHtASCt ASCtCAHt ASCt RAL Row Column 1t OEAt OEHCtRRH tRCHt RACt AAt AAt AA t CPA t CPA t OEZt OFFt OFFt CACt OEZt CAC t CACt COHD OUT NWE OE Column 2Column N Rowt RPD OUT 2• EDO Page Mode Early Write CycletRASPtRPt WCSt CAStRSH tRCDRASCAStASRtRAHtCAHADDRESStCASWEt CPDQ1~DQ4t PCt CPt CAStCPNtCRP tCAH tASCtASC tCAH tASC Row Column 1t DS WE Column 2Column Nt WCH t WCS t WCH t WCS t WCHt DH t DS t DH t DS t DHD IN 1D IN 2D IN Nt TtCSH• EDO Page Mode Read-Early-Write Cyclet RASPtCPRHt RCStCAStRSH tRCDt OEAtCSHRASCAStASRtRAHtCAHADDRESStCASWEtCRPt CPOEDQ1~DQ4OPENtWEDt PCt CPtCAStCPNtCRPtRADtRAHtASCt ASCtCAHt ASCt RAL Row Column 1tWCStRCHt RACt AAt AAt CPA t DHt WHZt CACt CACt COHWE OE Column 2Column N Rowt RPt CAL tWCHDataDoutput 2Data Input NDataDoutput 1t DStCSH• EDO Page Mode Read-Modify-Write Cyclet RASPt CPRHt RCStCASt WP RASCASt ASRtRAHtCAHADDRESSt CASWEtRCDCPDQ1~DQ4tPRWCt CPtCAStCRPtRADtCAHtASCt ASCtCAH tASC Row Column 1tRWLtRCSt OEDt DZOt CAC WE OEt RPt RAL D OUT 2D OUT ND OUT 1tTt Column NColumn 2Column 1tRWD tAWD tCWDtCWLtRCStCWDtAWD tCPW tCWL tCPW tAWD tCWDtCWL t OEDt OEDt OEHt OEHt OEHt CAC t CAC t OEA t AAt RACt OEZt OEAt AA t CPAt OEZt OEAt AA t CPAt OEZ t DSt DHt WP t DSt DHt WP t DSt DHOPENOPENOPEN D IN 1D IN ND IN 2DQ1~DQ4t DZCt DZOt DZCt DZCt DZO• Read Cycle with WE Controlled Disablet WPZt RCStCAStRCDt TtCSHRASCASt ASRtRAHtCAHADDRESSColumnRow tASCD DQ1~DQ4WEt OEZt DSt WHZOEt RCH t OEA t CACt AAt RACt CLZOUTtRADRASADDRESSt RC t CRPt ASRt RAHt Tt RPCROWt OFFCAS t RASt RPOPENt CRPDQ1~DQ4RASt CSRt WSRt RPt T t RPCt OFFCAS t RASt RPOPENt CRPDQ1~DQ4t RPCt CHRt RASt RPt RCt RCt CHRt CSRt WHRt WSRt WHRWECAS-Before-RAS Refresh CycleRASWEt RPCt OFFt CSRt CHSt WSRCASt RASS t RPSOPENDQ1~DQ4t WHRHigh lmpedance• Hidden Refresh Cyclet RPt RASRASt RCDt CRPADDRESSWEt CHRt CASt RSHt RAHt ASRt ASCt CAHt RAL ROW t RCHt OEZCASDQ1~DQ4t Tt RCSD t RASt RASt RPt RPt RC t RCt RCt RADt RRHt OFF t OFFt OEA t CACt AAt RACCOlumnOUTOE(READ)(REFRESH)(REFRESH)Ordering informationAD404M42VSA-5• AD• Ascend Memory Product • 40 • Device Type• 4M4 • Density and Organization • 2• Refresh Rate, 2: 2K Refresh • V• T: 5V, V: 3.3V• S • Package Type (S : SOJ, T : TSOP II)• A• Version• 5• Speed (5: 50 ns, 6: 60 ns)Part Number Access time PackageAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-650 ns 60 ns 50 ns 60 ns300mil 26/24-Pin Plastic SOJTSOP IIPackaging information • 300 mil, 26/24-Pin Plastic SOJ• 300 mil, 26/24-Pin TSOP II。