DS3695中文资料

General DescriptionThe DS7505 low-voltage (1.7V to 3.7V) digital ther-mometer and thermostat provides 9-, 10-, 11-, or 12-bit digital temperature readings over a -55°C to +125°C range with ±0.5°C accuracy over a -0°C to +70°C range.A 9-bit resolution mode is software compatible with the LM75. Communication with the DS7505 is achieved through a simple 2-wire serial interface. Three address pins allow up to eight DS7505 devices to operate on the same 2-wire bus, which greatly simplifies distributed temperature-sensing applications.The DS7505 thermostat has a dedicated open-drain out-put (O.S.) and programmable fault tolerance, which allows the user to define the number of consecutive error conditions that must occur before O.S. is activated.There are two thermostatic operating modes that control thermostat operation based on user-defined trip points (T OS and T HYST ) that are stored in EEPROM registers.ApplicationsNetworking Equipment Cellular Base Stations Office Equipment Medical EquipmentAny Thermally Sensitive SystemFeatures♦Operating Range from 1.7V to 3.7V♦Temperature Measurements Require No External Components ♦Measures Temperatures from -55°C to +125°C (-67°F to +257°F)♦±0.5°C Accuracy Over a 0°C to +70°C Range ♦Thermometer Resolution is User-Configurable from 9 (Default) to 12 Bits (0.5°C to 0.0625°C Resolution)♦9-Bit Conversion Time is 25ms (max)♦Thermostatic Settings are User-Definable and Nonvolatile (NV)♦Stand-Alone Thermostat Capability♦Data Read/Write Occurs Through a 2-Wire Serial Interface (SDA and SCL Pins)♦Data Lines Filtered Internally for Noise Immunity (50ns Deglitch)♦Optional Bus Timeout Feature Prevents Lockup Problems on 2-Wire Interface ♦Multidrop Capability Simplifies Distributed Temperature-Sensing Applications ♦Pin/Software Compatible with the LM75♦Available in 8-Pin SO and µMAX ®PackagesDS7505Digital Thermometer and Thermostat________________________________________________________________Maxim Integrated Products 1Pin ConfigurationsOrdering InformationRev 1; 3/08For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .+Denotes a lead-free package.T&R = Tape and reel.µMAX is a registered trademark of Maxim Integrated Products, Inc.Commands are capitalized for clarity.D S 7505Digital Thermometer and Thermostat 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Voltage Range on VDD Relative to Ground ..........-0.3V to +4.0V Voltage Range on Any Other PinRelative to Ground.............................................-0.3V to +6.0VOperating Temperature Range .........................-55°C to +125°C Storage Temperature Range.............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDECJ-STD-020 Specification.AC ELECTRICAL CHARACTERISTICSDS7505Digital Thermometer and Thermostat_______________________________________________________________________________________3max-rated current.Note 3:Specified in 12-bit conversion mode. Quantization error must be considered when converting in lower resolutions.Note 4:I DD specified with O.S. pin open.Note 5:I DD specified with V DD at 3.0V and SDA, SCL = 3.0V, T A = -55°C to +85°C.Note 6:I DD specified with A0, A1, A2 = 0V or V DD .Note 7:V DD must be > 2.0V.Note 8:E 2Copy occurs at +25°C.Note 9:See the timing diagram (Figure 1). All timing is referenced to 0.9 x V DD and 0.1 x V DD .Note 10:After this period, the first clock pulse is generated.Note 11:The DS7505 provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL’s falling edge.Note 12:For example, if C B = 300pF, then t R(MIN)= t F(MIN)= 50ns.Note 13:This timeout applies only when the DS7505 is holding SDA low. Other devices can hold SDA low indefinitely and the DS7505 does not reset.AC ELECTRICAL CHARACTERISTICS (continued)D S 7505Digital Thermometer and Thermostat 4_______________________________________________________________________________________Figure 1. Timing DiagramFigure 2. Block DiagramDS7505Digital Thermometer and Thermostat_______________________________________________________________________________________5OS HYSTOperation ⎯MeasuringTemperatureThe DS7505 measures temperature using a bandgap temperature-sensing architecture. An on-board delta-sigma analog-to-digital converter (ADC) converts the measured temperature to a digital value that is calibrat-ed in degrees Celsius; for Fahrenheit applications a lookup table or conversion routine must be used. The DS7505 is factory-calibrated and requires no external components to measure temperature.The DS7505 can be configured to power up either automatically converting temperature or in a low-power standby state. The preferred power-up mode can be set using the SD bit in the configuration register as explained in the Configuration Register section. The resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits, corresponding to temperature increments of 0.5°C, 0.25°C, 0.125°C, and 0.0625°C,respectively. The factory default resolution at power-up is 9 bits (R1 = 0, R0 = 0), however this can be pro-grammed to 10, 11, or 12 bits using the R0 and R1 bits in the configuration register as explained in the Configuration Register section. Note that the conver-sion time doubles for each additional bit of resolution.After each temperature measurement and analog-to-digital (A/D) conversion, the DS7505 stores the temper-ature as a 16-bit two’s complement number in the 2-byte temperature register (see Figure 3). The sign bit (S) indicates if the temperature is positive or negative:for positive numbers S = 0 and for negative numbers S = 1. The most recently converted digital measurement can be read from the temperature register at any time.Since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress.Bits 3 through 0 of the temperature register are hard-wired to 0. When the DS7505 is configured for 12-bit resolution, the 12 MSBs (bits 15 through 4) of the tem-perature register contain temperature data. For 11-bit resolution, the 11 MSBs (bits 15 through 5) of the tem-perature register contain data, and bit 4 reads out as 0.Likewise, for 10-bit resolution, the 10 MSBs (bits 15through 6) contain data, and for 9-bit the 9 MSBs (bits 15 through 7) contain data and all unused LSBs con-tains 0s. Table 1 gives examples of 12-bit resolution dig-ital output data and the corresponding temperatures.D S 7505Shutdown ModeFor power-sensitive applications, the DS7505 offers a low-power shutdown mode. The SD bit in the configura-tion register controls shutdown mode. When SD is pro-grammed to 1, the conversion in progress is completed and the result stored in the temperature register, after which the DS7505 goes into a low-power standby state.The O.S. output is cleared if the thermostat is operating in interrupt mode and O.S remains unchanged in com-parator mode. The 2-wire interface remains operational in shutdown mode, and writing a 0 to the SD bit returns the DS7505 to normal operation. Upon power-up in shutdown mode, the DS7505 executes one tempera-ture measurement. The result is stored in the tempera-ture register, after which the DS7505 enters the shutdown state.Operation ⎯ThermostatThe DS7505 thermostat can be programmed to power up in either comparator mode or interrupt mode, which activate and deactivate the open-drain thermostat out-put (O.S.) based on user-programmable trip points (T OS and T HYST ). The T HYST and T OS registers contain Celsius temperature values in two’s complement format and consist of EEPROM that is shadowed by SRAM.Once written to the shadow SRAM, values can be stored in EEPROM by issuance of a Copy Data com-mand from the master (see the Command Set section for more details). The device can operate using the shadow SRAM only or using the EEPROM. If the EEPROM is used, the values are NV and can be pro-grammed prior to installation of the DS7505 for stand-alone operation. The factory power-up settings for the DS7505 are with the thermostat in comparator mode,active-low O.S. polarity, overtemperature trip-point (T OS ) register set to 80°C, the hysteresis trip-point (T HYST ) register set to +75°C, and the number of con-secutive conversion to trigger O.S. set to 1. If these power-up settings are compatible with the application,the DS7505 can be used as a stand-alone thermostat (i.e., no 2-wire communication required) with no pro-gramming required prior to installation. If interrupt mode operation, active-high O.S. polarity, different T OS and T HYST values, or a different number of conversions to trigger O.S. are desired, they must be programmedinto the EEPROM either after initial power-up or prior to IC installation. The programmed values then become the new power-up defaults.In both operating modes, the user can program the thermostat-fault tolerance, which sets how many con-secutive temperature readings (1, 2, 4, or 6) must fall outside the thermostat limits before the thermostat out-put is triggered. The fault tolerance is set by the F1 and F0 bits in the configuration register. The default factory power-up setting for fault tolerance is 1 (F1 = 0, F0 = 0).The data format of the T OS and T HYST registers is iden-tical to that of the temperature register (see Figure 3),i.e., a 2-byte two’s complement representation of the trip-point temperature in degrees Celsius with bits 3through 0 hardwired to 0. After every temperature con-version, the measurement is compared to the values stored in the T OS and T HYST registers. The O.S. output is updated based on the result of the comparison and the operating mode of the IC. The number of T OS and T HYST bits used during the thermostat comparison is equal to the conversion resolution set by the R1 and R0bits in the configuration register. For example, if the resolution is 9 bits, only the 9 MSBs of T OS and T HYST are used by the thermostat comparator.The active state of the O.S. output can be programmed by the POL bit in the configuration register. The power-up factory default is active low (POL = 0).If the user does not wish to use the thermostat capabili-ties of the DS7505, the O.S. output should be left unconnected. Note that if the thermostat is not used,the T OS and T HYST registers can be used for general storage of system data.Comparator ModeWhen the thermostat is in comparator mode, O.S. can be programmed to operate with any amount of hystere-sis. The O.S. output becomes active when the mea-sured temperature exceeds the T OS value a consecutive number of times as defined by the F1 and F0 fault tolerance (FT) bits in the configuration register.O.S. then stays active until the first time the tempera-ture falls below the value stored in T HYST . Putting the device into shutdown mode does not clear O.S. in com-parator mode. Thermostat comparator mode operation with FT = 2 is illustrated in Figure 4.Digital Thermometer and Thermostat 6_______________________________________________________________________________________DS7505Digital Thermometer and Thermostat_______________________________________________________________________________________7Interrupt ModeIn interrupt mode, the O.S. output first becomes active when the measured temperature exceeds the T OS value a consecutive number of times equal to the FT value in the configuration register. Once activated, O.S.can only be cleared by either putting the DS7505 into shutdown mode or by reading from any register (tem-perature, configuration, T OS , or T HYST ) on the device.Once O.S. has been deactivated, it is only reactivatedwhen the measured temperature falls below the T HYST value a consecutive number of times equal to the FT value. Again, O.S can only be cleared by putting the device into shutdown mode or reading any register.Thus, this interrupt/clear process is cyclical between T OS and T HYST events (i.e, T OS , clear, T HYST , clear,T OS , clear, T HYST , clear, etc.). Thermostat interrupt mode operation with FT = 2 is illustrated in Figure 4.D S 7505Configuration RegisterThe configuration register allows the user to program various DS7505 options such as conversion resolution,thermostat fault tolerance, thermostat polarity, thermo-stat operating mode, and shutdown mode. The configu-ration register is arranged as shown in Figure 5 and detailed descriptions of each bit are provided in Table 2. The user has read/write access to all bits in the con-figuration register except the MSB (NVB bit), which is aread-only bit. All bits in the register but the NVB bit are NV EEPROM backed by shadow SRAM, and thus power-up in their programmed state. Once written to the shadow SRAM, values can be stored in EEPROM by issuance of a Copy Data command from the master (see the Command Set section for more details). If the values are not copied to the EEPROM, the device pow-ers up with the factory default settings or the last values that were copied to the EEPROM. The NVB bit is SRAM and powers up in the state shown in Table 2.Digital Thermometer and Thermostat 8_______________________________________________________________________________________Figure 5. Configuration RegisterRegister Pointer The four DS7505 registers each have a unique 2-bit pointer designation, which is defined in Table 5. When reading from or writing to the DS7505, the user must “point” the DS7505 to the register that is to be accessed. When reading from the DS7505, once the pointer is set, it remains pointed at the same register until it is changed. For example, if the user desires to perform consecutive reads from the temperature regis-ter, then the pointer only has to be set to the tempera-ture register one time, after which all reads are automatically from the temperature register until the pointer value is changed. When writing to the DS7505, the pointer value must be refreshed each time a write is performed, even if the same register is being written to twice in a row.At power-up, the pointer defaults to the temperature register location. The temperature register can be read immediately without resetting the pointer.Changes to the pointer setting are accomplished as described in the 2-Wire Serial Data Bus section.2-Wire Serial Data Bus The DS7505 communicates over a standard bidirection-al 2-wire serial data bus that consists of a serial clock (SCL) signal and serial data (SDA) signal. The DS7505 interfaces to the bus through the SCL input pin and open-drain SDA I/O pin. All communication is MSB first. The following terminology is used to describe 2-wire communication:M aster Device:Microprocessor/microcontroller thatcontrols the slave devices on the bus. The masterdevice generates the SCL signal and START and STOPconditions.Slave:All devices on the bus other than the master.The DS7505 always functions as a slave.Bus Idle or Not Busy:Both SDA and SCL remain high.SDA is held high by a pullup resistor when the bus isidle, and SCL must either be forced high by the master(if the SCL output is push-pull) or pulled high by apullup resistor (if the SCL output is open drain).Transmitter:A device (master or slave) that is sendingdata on the bus.Receiver:A device (master or slave) that is receivingdata from the bus.START Condition:Signal generated by the master toindicate the beginning of a data transfer on the bus.The master generates a START condition by pullingSDA from high to low while SCL is high (see Figure 6).A “repeated” START is sometimes used at the end of adata transfer (instead of a STOP) to indicate that themaster performs another operation.STOP Condition:Signal generated by the master toindicate the end of a data transfer on the bus. The mas-ter generates a STOP condition by transitioning SDAfrom low to high while SCL is high (see Figure 6). Afterthe STOP is issued, the master releases the bus to itsidle state.Acknowledge (ACK):When a device (either master orslave) is acting as a receiver, it must generate anacknowledge (ACK) on the SDA line after receivingevery byte of data. The receiving device performs anACK by pulling the SDA line low for an entire SCL peri-od (see Figure 6). During the ACK clock cycle, thetransmitting device must release SDA. A variation onthe ACK signal is the “not acknowledge” (NACK). Whenthe master device is acting as a receiver, it uses aNACK instead of an ACK after the last data byte to indi-cate that it is finished receiving data. The master indi-cates a NACK by leaving the SDA line high during theACK clock cycle.DS7505 Digital Thermometer and Thermostat9D S 7505Slave Address:Every slave device on the bus has a unique 7-bit address that allows the master to access that device. The DS7505’s 7-bit bus address is 1 0 0 1A 2A 1A 0, where A 2, A 1, and A 0 are user-selectable through the corresponding input pins. The three address pins allow up to eight DS7505s to be mul-tidropped on the same bus.Address Byte:The control byte is transmitted by the master and consists of the 7-bit slave address plus aread/write (R/W ) bit (see Figure 7). If the master is going to read data from the slave device then R/W = 1,and if the master is going to write data to the slave device then R/W = 0.Pointer Byte:The pointer byte is used by the master to tell the DS7505 which register is going to be accessed during communication. The six MSBs of the pointer byte (see Figure 8) are always 0 and the two LSBs cor-respond to the desired register as shown in Figure 8.Digital Thermometer and Thermostat10______________________________________________________________________________________General 2-Wire Information •All data is transmitted MSB first over the 2-wire bus.•One bit of data is transmitted on the 2-wire bus each SCL period.•A pullup resistor is required on the SDA line, and, when the bus is idle, both SDA and SCL must remain in a logic-high state.•All bus communication must be initiated with a START condition and terminated with a STOP condi-tion. During a START or STOP is the only time SDA is allowed to change states while SCL is high. At all other times, changes on the SDA line can only occur when SCL is low; SDA must remain stable when SCL is high.•After every 8-bit (1-byte) transfer, the receiving device must answer with an ACK (or NACK), which takes one SCL period. Therefore, nine clocks are required for every 1-byte data transfer.Writing to the DS7505:To write to the DS7505, the master must generate a START followed by an address byte containing the DS7505 bus address. The value of the R/W bit must be a 0, which indicates that a write is about to take place. The DS7505 responds with an ACK after receiving the address byte. The master then sends a pointer byte which tells the DS7505 which reg-ister is being written to. The DS7505 again responds with an ACK after receiving the pointer byte. Following this ACK the master device must immediately begin transmitting data to the DS7505. When writing to the configuration register, the master must send one byte of data (see Figure 9B), and when writing to the T OS or T HYST registers the master must send two bytes of data (see Figure 9C). After receiving each data byte, the DS7505 responds with an ACK, and the transaction is finished with a STOP from the master. All writes to the DS7505 are made to shadow SRAM. Once data is writ-ten to the shadow SRAM, it is only stored to EEPROM by issuance of a Copy Data command from the master. At that time, all registers are copied to EEPROM except the Temperature register which is SRAM only.Reading from the DS7505:When reading from the DS7505, if the pointer was already pointed to the desired register during a previous transaction, the read can be performed immediately without changing the pointer setting. In this case the master sends a START followed by an address byte containing the DS7505 bus address. The R/W bit must be a 1, which tells the DS7505 that a read is being performed. After the DS7505 sends an ACK in response to the address byte, the DS7505 begins transmitting the requesteddata on the next clock cycle. When reading from the configuration register, the DS7505 transmits one byte of data, after which the master must respond with a NACK followed by a STOP (see Figure 9E). For two-byte reads(i.e., from the temperature, T OS or T HYST register), theDS7505 transmits two bytes of data, and the mastermust respond to the first data byte with an ACK and tothe second byte with a NACK followed by a STOP (see Figure 9A). If only the most significant byte of data is needed, the master can issue a NACK followed by a STOP after reading the first data byte in which case the transaction is the same as for a read from the configu-ration register.If the pointer is not already pointing to the desired reg-ister, the pointer must first be updated as shown in Figure 9D, which shows a pointer update followed by asingle-byte read. The value of the R/W bit in the initial address byte is a 0 (“write”) since the master is goingto write a pointer byte to the DS7505. After the DS7505 responds to the address byte with an ACK, the mastersends a pointer byte that corresponds to the desired register. The master must then perform a repeated start followed by a standard one or two byte read sequence(with R/W=1) as described in the previous paragraph.The Recall Data command should be issued before aread if assurance is needed that the contents of the EEPROM in the Shadow SRAM when read.Bus Timeout:The DS7505 has a bus timeout featurethat prevents communication errors from leaving the ICin a state where SDA is held low disrupting other devices on the bus. If the DS7505 holds the SDA linelow for a period of t TIMEOUT, its bus interface automati-cally resets and release the SDA line. Bus communica-tion frequency must be fast enough to prevent a reset during normal operation. The bus timeout feature only applies to when the DS7505 is holding SDA low. Other devices can hold SDA low for an undefined period with-out causing the interface to reset.Command SetRecall Data [B8h]1011 1000Refreshes SRAM shadow register with EEPROM data. Itis recommended that a Recall command be performed before reading EEPROM-backed memory locations.The master sends a START followed by an addressbyte containing the DS7505 bus address. The R/W bitmust be a 0. The DS7505 responds with an ACK. If thenext byte is a 0xB8, the DS7505 recalls all EEPROMdata into shadow RAM locations.DS7505Digital Thermometer and Thermostat ______________________________________________________________________________________11D S 7505Copy Data [48h]0100 1000Copies data from all SRAM shadow registers to EEPROM. It is recommended that a Copy Data com-mand be performed after writing EEPROM-backed memory locations to guarantee data integrity in the event of a power loss. The master sends a START fol-lowed by an address byte containing the DS7505 bus address. The R/W bit must be a 0. The DS7505responds with an ACK. If the next byte is a 0x48, the DS7505 copies all Shadow RAM locations in EEPROM memory.Software POR [54h]0101 0100The master sends a START followed by an address byte containing the DS7505 bus address. The R/W bit must be a 0. The DS7505 responds with an ACK. If the next byte is a 0x54, the DS7505 resets as if power had been cycled, which stops temperature conversions and resets all registers to their power-up states. No ACK is sent by the IC after the POR command is received.Afterwards, the DS7505 makes a single temperature conversion or continuous temperature conversions,depending on the state of the SD bit.Digital Thermometer and Thermostat 12______________________________________________________________________________________Figure 9. 2-Wire Interface TimingDS7505Digital Thermometer and Thermostat______________________________________________________________________________________13Package Information(For the latest package outline information, go to /DallasPackInfo .)21-0036PACKAGE TYPE DOCUMENT NO.8 SO (150 mils)56-G2008-0018 µMAXD S 7505Digital Thermometer and Thermostat Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.14____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2008 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc.I。

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2. Storage
2.1 Do not open moisture proof bag before the products are ready to use. 2.2 Before opening the package, the LEDs should be kept at 30℃ or less and 90%RH or less. 2.3 The LEDs should be used within a year. 2.4 After opening the package, the LEDs should be kept at 30℃ or less and 70%RH or less.
2. The dominant wavelength (λd) is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device.

DS36C279Low Power EIA-RS-485Transceiver with Sleep ModeGeneral DescriptionThe DS36C279is a low power differential bus/line trans-ceiver designed to meet the requirements of RS-485Stan-dard for multipoint data transmission.In addition it is compat-ible with TIA/EIA-422-B.The sleep mode feature automatically puts the device in a power saving mode when both the driver and receiver are disabled.††The device is ideal for use in power conscious applications where the device may be disabled for extended periods of time.The driver and receiver outputs feature TRI-STATE ®capabil-ity.The driver outputs operate over the entire common mode range of −7V to +12V.Bus contention or fault situations that cause excessive power dissipation within the device are handled by a thermal shutdown circuit,which forces the driver outputs into a high impedance state.The receiver incorporates a fail safe circuit which guarantees a high output state when the inputs are left open.†The DS36C279T is fully specified over the industrial tem-perature range (−40˚C to +85˚C).Featuresn 100%RS-485compliant—Guaranteed RS-485device interoperation n Low power CMOS design:I CC 500µA max n Automatic sensing sleep mode—Reduces I CC to 10µA maximumn Built-in power up/down glitch-free circuitry—Permits live transceiver intersection/displacement n DIP and SOIC packages availablen Industrial temperature range:−40˚C to +85˚C n On-board thermal shutdown circuitry—Prevents damage to the device in the event of excessive power dissipationn Wide common mode range:−7V to +12V n Receive open input fail-safe (Note 1)n 1⁄4unit load (DS36C279):≥128nodes n 1⁄2unit load (DS36C279T):≥64nodes n ESD (Human Body Model):≥2kV n Drop-in replacement for:—LTC485MAX485DS75176DS3695Connection and Logic Diagram Truth TableDRIVER SECTION RE*DE DI DO/RI DO*/RI*X H H H L X H L L H X L XZZ RECEIVER SECTIONRE*DE RI-RI*RO L L ≥+0.2V H L L ≤−0.2V L H L XZ (Note 2)LLOPEN (Note 1)HNote 1:Non-terminated,open input onlyNote 2:Device enters sleep mode if enable conditions are held 600nsTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS012053-1Order Number DS36C279M,DS36C279N,DS36C279TM or DS36C279TNSee NS Package Number M08A or N08EJuly 1998DS36C279Low Power EIA-RS-485Transceiver with Sleep Mode©1999National Semiconductor Corporation Absolute Maximum Ratings(Note3)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)+12V Input Voltage(DE,RE*,&DI)−0.5V to(V CC+0.5V) Common Mode(V CM)Driver Output/Receiver Input±15V Input Voltage(DO/RI,DO*/RI*)±14V Receiver Output Voltage−0.5V to(V CC+0.5V) Maximum Package Power Dissipation@+25˚CM Package1190mW,derate9.5mW/˚C above+25˚C N Package744mW,derate 6.0mW/˚C above+25˚C Storage Temperature Range−65˚C to+150˚C Lead Temperature(Soldering4sec)+260˚C Recommended Operating ConditionsMin Typ Max Units Supply Voltage(V CC)+4.75+5.0+5.25V Bus Voltage−7+12V Operating Free Air Temperature(T A)DS36C279T−40+25+85˚C DS36C2790+25+70˚CElectrical Characteristics(Notes4,5)Over Supply Voltage and Operating Temperature ranges,unless otherwise specifiedSymbol Parameter Conditions Reference Min Typ Max Units DIFFERENTIAL DRIVER CHARACTERISTICSV OD1Differential Output Voltage I O=0mA(No Load)(422)(485)1.5 5.0VV OD0Output Voltage I O=0mA0 5.0V V OD0*Output Voltage(Output to GND)0 5.0V V OD2Differential Output Voltage R L=50Ω(422)Figure1 2.0 2.8V (Termination Load)R L=27Ω(485) 1.5 2.3 5.0V ∆V OD2Balance of V OD2R L=27Ωor50Ω(Note6)−0.20.1+0.2V |V OD2−V OD2*|(422,485)V OD3Differential Output Voltage R1=54Ω,R2=375ΩFigure2 1.5 2.0 5.0V (Full Load)V TEST=−7V to+12VV OC Driver Common Mode R L=27Ω(485)Figure10 3.0V Output Voltage R L=50Ω(422)0 3.0V ∆V OC Balance of V OC R L=27Ωor(Note6)−0.2+0.2V |V OC−V OC*|R L=50Ω(422,485)I OSD Driver Output Short-Circuit V O=+12V(485)Figure4200+250mACurrent V O=−7V(485)−190−250mA RECEIVER CHARACTERISTICSV TH Differential Input HighThreshold Voltage V O=V OH,I O=−0.4mA(Note7)(422,485)+0.035+0.2V −7V≤V CM≤+12VV TL Differential Input LowThreshold Voltage V O=V OL,I O=0.4mA−0.2−0.035V −7V≤V CM≤+12VV HST Hysteresis V CM=0V(Note8)70mV R IN Input Resistance−7V≤V CM≤+12V DS36C279T2468kΩDS36C2794868kΩI IN Line Input Current Other Input=0V,DS36C279V IN=+12V00.190.25mA(Note9)DE=V IL,RE*=V IL,V IN=−7V0−0.1−0.2mAV CC=4.75to5.25DS36C279T V IN=+12V00.190.5mAor0V V IN=−7V0−0.1−0.4mAI ING Line Input Current Glitch Other Input=0V,DE=V IL,RE*=V IL,DS36C279V IN=+12V00.190.25mA(Note9)V IN=−7V0−0.1−0.2mAV CC=+3.0V or0V, T A=25˚C DS36C279T V IN=+12V00.190.5mAV IN=−7V0−0.1−0.4mAI B Input Balance Test RS=500Ω(422)(Note12)±400mVV OH High Level Output Voltage I OH=−4mA,V ID=+0.2V ROFigure113.5 4.6VV OL Low Level Output Voltage I OL=+4mA,V ID=−0.2V0.30.5V 2Electrical Characteristics(Notes4,5)(Continued)Over Supply Voltage and Operating Temperature ranges,unless otherwise specifiedSymbol Parameter Conditions Reference Min Typ Max Units RECEIVER CHARACTERISTICSI OSR Short Circuit Current V O=GND RO73585mA I OZR TRI-STATE LeakageCurrentV O=0.4V to2.4V±1µA DEVICE CHARACTERISTICSV IH High Level Input Voltage DE,RE*,DI 2.0V CC VV IL Low Level Input Voltage GND0.8V I IH High Level Input Current V IH=V CC2µA I IL Low Level Input Current V CC=5V V IL=0V−2µAV CC=+3.0V−2µAI CC Power Supply Current(No Load)Driver and Receiver ONV CC200500µAI CCR Driver OFF,Receiver ON200500µA I CCD Driver ON,Receiver OFF200500µA I CCX Sleep Mode0.210µASwitching Characteristics(Notes5,10)Over Supply Voltage and Operating Temperature ranges,unless otherwise specifiedSymbol Parameter Conditions Reference Min Typ Max Units DRIVER CHARACTERISTICSt PHLD Differential PropagationDelay High to LowR L=54Ω,C L=100pFFigures5,6103980nst PLHD Differential PropagationDelay Low to High104080nst SKD Differential Skew0110ns |t PHLD−t PLHD|t r Rise Time32550ns t f Fall Time32550nst PHZ Disable Time High to Z C L=15pFRE*=L Figures7,880200nst PLZ Disable Time Low to Z Figures9,1080200nst PZH Enable Time Z to High C L=100pFRE*=L Figures7,850200nst PZL Enable Time Z to Low Figures9,1065200ns t PSH Driver Enable from Sleep C L=100pF Figures7,87098250ns Mode to Output High(Note11)t PSL Driver Enble from Sleep C L=100pF Figures9,107098250ns Mode to Output Low(Note11)RECEIVER CHARACTERISTICSt PHL Propagation Delay C L=15pF Figures12,1330210400ns High to Lowt PLH Propagation Delay30190400ns Low to Hight SK Skew,|t PHL−t PLH|02050nst PLZ Output Disable Time C L=15pFFigures14,15,1650150nst PHZ DE=H55150nst PZL Output Enable Time40150nst PZH45150nst PSH Receiver Enable from Sleep C L=15pF Figures14,167097250ns Mode to Output High(Note11)t PSL Receiver Enable from Sleep C L=15pF Figures14,157095250ns3Switching Characteristics (Notes 5,10)(Continued)Over Supply Voltage and Operating Temperature ranges,unless otherwise specifiedSymbolParameterConditions ReferenceMinTypMaxUnitsRECEIVER CHARACTERISTICSMode to Output Low(Note 11)Note 3:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the devices should be operated at these limits.The table of “Electrical Characteristics”specifies conditions of device operation.Note 4:Current into device pins is defined as positive.Current out of device pins is defined as negative.All voltages are referenced to ground except V OD1and V OD2.Note 5:All typicals are given for:V CC =+5.0V,T A =+25˚C.Note 6:Delta |V OD2|and Delta |V OC |are changes in magnitude of V OD2and V OC ,respectively,that occur when input changes state.Note 7:Threshold parameter limits specified as an algebraic value rather than by magnitude.Note 8:Hysteresis defined as V HST =V TH −V TL .Note 9:I IN includes the receiver input current and driver TRI-STATE leakage current.Note 10:C L includes probe and jig capacitance.Note 11:For enable from sleep mode delays DE =L and RE*=H for greater than 600ns prior to test (device is in sleep mode).Note 12:For complete details of test,see RS-485.Parameter Measurement InformationDS012053-2FIGURE 1.Driver V OD2and V OCDS012053-17FIGURE 2.Driver V OD3DS012053-3FIGURE 3.Driver V OH and V OLDS012053-4Vtest =−7V to +12VFIGURE 4.Driver I OSDDS012053-5FIGURE 5.Driver Differential Propagation Delay Test Circuit 4Parameter Measurement Information(Continued)DS012053-6FIGURE6.Driver Differential Propagation Delays and Differential Rise and Fall TimesDS012053-7FIGURE7.TRI-STATE and Sleep Mode Test Circuit(t PZH,(t PSH),t PHZ)DS012053-8FIGURE8.TRI-STATE and Sleep Mode Waveforms(t PZH,(t PSH),t PHZ)DS012053-9FIGURE9.TRI-STATE and Sleep Mode Test Circuit(t PZL,(t PSL),t PLZ)DS012053-10FIGURE10.TRI-STATE and Sleep Mode Waveforms(t PZL,(t PSL),t PLZ)DS012053-11FIGURE11.Receiver V OH and V OLDS012053-12FIGURE12.Receiver Differential Propagation DelayTest Circuit5Parameter Measurement Information(Continued)DS012053-13FIGURE13.Receiver Differential Propagation Delay WaveformsDS012053-14FIGURE14.Receiver TRI-STATE and Sleep Mode Test CircuitDS012053-15FIGURE15.Receiver Enable and Disable Waveforms(t PLZ,t PZL,(t PSL))DS012053-16FIGURE16.Receiver Enable and Disable Waveforms(t PHZ,t PZH,(t PSH)) 6Parameter Measurement Information(Continued)Typical Application InformationTABLE 1.Device Pin DescriptionsPin Description1ROReceiver Output:When RE (Receiver Enable)is LOW,the receiver is enabled (ON),if DO/RI ≥DO*/RI*by 200mV,RO will be HIGH.If DO/RI ≤DO*/RI*by 200mV,RO will be LOW.Additionally RO will be HIGH for OPEN (Non-terminated)Inputs.2RE*Receiver Output Enable:When RE*is LOW the receiver output is enabled.When RE*is HIGH,the receiver output is in TRI-STATE (OFF).When RE*is HIGH and DE is LOW,the device will enter a low-current sleep mode after 600ns.3DEDriver Output Enable:When DE is HIGH,the driver outputs are enabled.When DE is LOW,the driver outputs are in TRI-STATE (OFF).When RE*is HIGH and DE is LOW,the device will enter a low-current sleep mode after 600ns.4DI Driver Input:When DE (Driver Enable)is HIGH,the driver is enabled,if DI is LOW,then DO/RI will be LOW and DO*/RI*will be HIGH.If DI is HIGH,then DO/RI is HIGH and DO*/RI*is LOW.5GND Ground Connection.6DO/RI Driver Output/Receiver Input,485Bus Pin.7DO*/RI*Driver Output/Receiver Input,485Bus Pin.8V CCPositive Power Supply Connection:Recommended operating range for V CC is +4.75V to +5.25V.Unit LoadA unit load for an RS-485receiver is defined by the input cur-rent versus the input voltage curve.The gray shaded region is the defined operating range from −7V to +12V.The top border extending from −3V at 0mA to +12V at +1mA is de-fined as one unit load.Likewise,the bottom border extending from +5V at 0mA to −7V at −0.8mA is also defined as oneunit load (see Figure 19).An RS-485driver is capable of driving up to 32unit loads.This allows up to 32nodes on a single bus.Although sufficient for many applications,it is sometimes desirable to have even more nodes.For ex-ample,an aircraft that has 32rows with 4seats per row would benefit from having 128nodes on one bus.This wouldDS012053-19FIGURE 17.Entering Sleep Mode ConditionsDS012053-18FIGURE 18.Typical RS-485Bus Interface7Unit Load(Continued)allow signals to be transferred to and from each individual seat to1main ually there is one or two less seats in the last row of the aircraft near the restrooms and food storage area.This frees the node for the main station.The DS36C278,the DS36C279,and the DS36C280all have 1⁄2unit load and1⁄4unit load(UL)options available.These devices will allow up to64nodes or128nodes guaranteed over temperature depending upon which option is selected. The1⁄2UL option is available in industrial temperature and the1⁄4UL is available in commercial temperature.First,for a1⁄2UL device the top and bottom borders shown in Figure19are scaled.Both0mA reference points at+5V and −3V stay the same.The other reference points are+12V at +0.5mA for the top border and−7V at−0.4mA for the bot-tom border(see Figure19).Second,for a1⁄4UL device the top and bottom borders shown in Figure19are scaled also. Again,both0mA reference points at+5V and−3V stay the same.The other reference points are+12V at+0.25mA for the top border and−7V at−0.2mA for the bottom border (see Figure19).The advantage of the1⁄2UL and1⁄4UL devices is the in-creased number of nodes on one bus.In a single master multi-slave type of application where the number of slaves exceeds32,the DS36C278/279/280may save in the cost of extra devices like repeaters,extra media like cable,and/or extra components like resistors.The DS36C279and DS36C280have an additional feature which offers more advantages.The DS36C279has an auto-matic sleep mode function for power conscious applications. The DS36C280has a slew rate control for EMI conscious applications.Refer to the sleep mode and slew rate control portion of the application information section in the corre-sponding datasheet for more information on these features. Sleep ModeThe DS36C279features an automatic shutdown mode that allows the device to save power when not transmitting data. Since the shutdown mode is automatic,no external compo-nents are required.It may be used as little or as much as the application requires.The more the feature is utilized,the more power it saves.The sleep mode is automatically entered when both the driver and receiver are disabled.This occurs when both the DE pin is asserted to a logic low and the RE*pin is asserted to a logic high.Once both pins are asserted the device will enter sleep mode typically in50ns.The DS36C279is guar-anteed to go into sleep mode within600ns after both pins are asserted.The device wakes up(comes out of sleep mode)when either the DE pin is asserted to a logic high and/or the RE*pin is asserted to a logic low.After the device enters sleep mode it will take longer for the device to wake up than it does for the device to enable from TRI-STATE.Re-fer to datasheet specifications t PSL and t PSH and compare with t PZL and t PZH for timing differences.The benefit of the DS36C279is definitely its power savings. When active the device has a maximum I CC of500µA. When in sleep mode the device has a maximum I CC of only 10µA,which is50times less power than when active.The I CC when the device is active is already very low but when in sleep mode the I CC is ultra low.DS012053-20 FIGURE19.Input Current vs Input VoltageOperating Range8Physical Dimensions inches(millimeters)unless otherwise noted8-Lead(0.150"Wide)Molded Small Outline Package,JEDECOrder Number DS36C279M or DS36C279TMNS Package Number M08A8-Lead(0.300"Wide)Molded Dual-In-Line PackageOrder Number DS36C279N or DS36C279TNNS Package Number N08E9LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or (b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National Semiconductor EuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:sea.support@National Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507D S 36C 279L o w P o w e rE I A -R S -485T r a n s c e i v e r w i t h S l e e p M o d eNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

UTS3000A系列信号分析仪数据手册V1.02024.7产品特性⏹频率范围从9kHz至最高8.4GHz⏹显示平均噪声电平DANL可达-165dBm（典型值）⏹相位噪声<-102dBc/Hz（偏移10kHz，典型值）⏹全幅度精度<0.7dB⏹扫描点数最高到40001点⏹最小分辨率带宽（RBW）1Hz⏹标配跟踪源输出功能以及矢量网络分析功能⏹标配实时频谱分析模式，提供概率密度谱、光谱等多种显示方式，呈现实时测量结果⏹多种触发模式与触发模板⏹最大实时带宽40MHz（选件）⏹支持高级一键测量（选件）⏹支持EMI预扫分析功能（选件）⏹支持模拟解调分析（选件）⏹支持矢量信号分析（选件）⏹配置10.1英寸1280x800高清电容触摸显示屏⏹支持SCPI可编程仪器标准命令实时频谱模式组合显示，使用密度光谱图来进行无间隙的频谱显示，可直观的显示频率信号出现的频次；在有大信号的情况下捕捉到小信号。

频率模板触发通过频率模板触发对偶发或者瞬变信号进行触发测量。

矢量网络分析VNA 模式可以通过元器件、电路网络的S11、S21参数测量，通过史密斯图、极坐标等多种显示方式更精确地表征被测件的网络特性。

基于触摸界面，帮助用户简化测量流程，在更短的时间内获得更好的结果。

信号调制分析功能提供AM/FM/PM 模拟信号分析；ASK/FSK/PSKQAM/MSK/DPSK 数字信号分析和EVM 计算。

EMI 预兼容和一致性测试尽早通过抗电磁干扰(EMI)性能测试，可以避免延误产品上市。

为确保最终的EMI 一致性测试获得成功，应在产品开发过程中进行预兼容测试。

在设计周期中尽早发现EMI 问题，可以在内部进行传导和辐射发射测试，从而缩短测试周期。

优秀的选择性具有更强的邻近不等幅度的信号分辨能力。

出色的灵敏度可测试更微弱信号微弱信号的测试容易受到频谱仪本身的本底噪声影响。

UTS3000A 系列显示平均噪声电平低至-165dBm，出色的灵敏度可以有效对微弱信号进行测试扫描40001点数UTS3000A系列提供最高到40001个扫描点数，提供更高的频率分辨率，更易捕捉不易被发现的信号。