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第1章PLL工作原理与电路构成1(PLL与频率合成技术简介) 电路的基本工作原理111PLL 电路的三大组成部分1111PLL 的应用与频率合成器3112PLL 电路各部分工作波形3113PLL 电路以及频率合成器的构成412PLL 输出为输入N倍频的方法4121 输出为输入N/M倍频的方法(输入部分接入分频电路)5 122 输出为输入N/M倍频的方法(输出部分接入分频电路)5 123 输出为输入N×M倍频的方法(增设前置频率倍减器)6 124 电路与外差电路的组合方式(输出为(fin×N)+fL)7 125PLL 电路与DDS的组合方式7126PLL13PLL 频率合成器的信号纯正度9 理想频率合成器的输出频谱(1根谱线)9131132 振幅调制的噪声(AM噪声)10 频率调制的噪声(FM噪声)12133 噪声的影响14134FM 的其他应用1614PLL 数字数据恢复为时钟的情况16141【专栏】dBc18 频率电压转换电路(FM解调电路)19142 电动机的转速控制电路19143【专栏】PLL电路的发明者Bellescize20附录APLL电路中负反馈的应用21 电路与运算放大器电路的异同21A1PLL 放大电路中学习的负反馈方式与特性23A2第2章PLL电路的传输特性31(PLL电路的特性由环路滤波器决定) 电路传输特性的理解3121PLL211PLL 电路各部分的传输特性31 简单例题(时钟的50倍频电路)33212 传输特性的求法(除环路滤波器特性以外)35213【专栏】仿真使用SPICE非常方便36 使用的环路滤波器的特性与PLL电路的传输特性37214 PLL电路中施加负反馈的效果39215 环路滤波器设计的基础知识4122 低通滤波器的特性41221RC 具有阶跃特性的RC低通滤波器43222 多级RC滤波器中增益与相位之间关系44223 普通的RC低通滤波器(使用滞后滤波器时环路特性不稳定)46 224 使PLL特性稳定的滞后超前滤波器47225第3章PLL电路中环路滤波器的设计方法51(无源/有源环路滤波器的设计实例与验证) 无源环路滤波器的设计5131 滞后超前滤波器的伯德图51311312PLL 电路与滞后超前滤波器组合的特性53 分频系数的改变情况56313 根据规格化曲线图求出环路滤波器的常数(参照附录B)57 3143210 ～100kHz PLL频率合成器中环路滤波器的设计59 作为实验用频率合成器的概况59321 频率合成器传输特性的求法322(除环路滤波器以外)61 时间常数小、M=-10dB、相位裕量为60°的设计61323324 时间常数中等、M=-20dB、相位裕量为50°的设计64 时间常数大、M=-30dB、相位裕量为50°的设计66325 试做的频率合成器的输出波形68326 试做的频率合成器的输出频谱70327 锁相速度72328 有源环路滤波器7533331 有源环路滤波器75 次有源环路滤波器的伯德图753322 次有源环路滤波器773333 有源环路滤波器的噪声79334 根据规格化曲线图求出有源环路滤波器常数的方法80 335 ～50MHz PLL频率合成器中环路滤波器的设计80 3425 实际电路中设计的有源环路滤波器80341 使用规格化曲线图求出环路滤波器的常数81342 时间常数小、M=0dB、相位裕量为50°的设计85343 时间常数中等、M=-10dB、相位裕量为34450°的设计86 时间常数大、M=-20dB、相位裕量为50°的设计88 345 试做的频率合成器的输出波形89346 试做的频率合成器的输出频谱90347 锁相速度92348 锁相速度的仿真94349【专栏】用于测量频率变化形式的调制磁畴分析仪97 相位裕量不同时PLL电路的特性9735 用作实验的50倍频电路98351 环路滤波器的设计99352 相位裕量为40°的设计99353354 相位裕量为50°的设计100 相位裕量为60°的设计100355356 频率特性的仿真101 输出波形的频谱103357 锁相速度104358 电路最适用的相位裕量(40°～50°)105359PLL第4章4046与各种鉴相器109(PLL电路中使用的重要器件的基础知识) 的重要器件404610941PLL411PLL 的入门器件109 的三种类型1104124046 片内三种鉴相器11041374HC40464144046 片内VCO的特性113 鉴相器的工作要点11542 模拟鉴相器115421 数字鉴相器118422 相位频率型鉴相器120423 中PC2型鉴相器1234244046 死区124425 电流输出型鉴相器126426 高速鉴相器AD 9901127427第5章电压控制振荡器VCO的电路131(VCO要求的特性及各种振荡电路方式) 要求的性能13151VCO 的概况131511VCO 频率可变范围133512 频率控制的线性133513 输出噪声133514 输出波形的失真134515 电源电压变化时的稳定度134516 环境温度变化时的稳定度134517 外界磁场与振动的影响135518 由弛张振荡器构成的VCO13552 函数发生器的基本工作原理135521 由函数发生器构成的VCO138522 函数发生器IC MAX038的应用139523 反馈振荡器14253 反馈振荡器的基本工作原理142531 反馈振荡器振荡稳定的方法142532 由RC构成的反馈振荡器143533 状态可变VCO147534 高频用LC振荡电路及其在VCO中的应用15154 基本的哈脱莱/科耳皮兹振荡电路151541 科耳皮兹的改进型克拉普振荡电路152542 反耦合振荡电路153543 由LC振荡器构成VCO时采用的变容二极管154 544545 市售的LC振荡式VCO电路157 其他的VCO电路15855 由振子构成的反馈振荡器158551 延迟振荡器162552第6章可编程分频器的种类与工作原理163(构成PLL频率合成器的数字电路) 可编程分频器的基本器件(减计数器)1636161174HC19116361274HC40102/40103164613TC919816562 前置频率倍减器168 前置频率倍减器IC168621 脉冲吞没(Pulse Swallow)方式170622 分数(Fractional)-N方式171623 用LSI17263PLL 专用LSI的构成172631PLL632ADF4110/4111/4112/4113173第7章PLL电路的测试与评价方法177(无源/有源环路滤波器的环路增益) 负反馈电路中环路增益的测试17771 难以测试的环路增益177711 施加负反馈时原环路增益的测试178712 负反馈环路测试的仿真180713714 实际注入的信号181 使用频率响应分析仪的测试方法18372 负反馈环路特性的测试183721722FRA 与FFT分析仪的不同之处185 与网络分析仪的不同之处185723FRA 电路中环路增益的测试18673PLL 使用无源环路滤波器的PLL186731 使用有源环路滤波器的PLL188732第8章PLL特性改善技术191(信号纯正度与锁相速度的提高技术) 优质的电源19181 使用CMOS反相器电路进行的实验191811 使用晶体振荡电路进行的实验193812 串联稳压器噪声特性的比较196813 控制电压特性的改善20082VCO 内VCO线性的改善200821CD74HC4046 片内VCO的频率变化范围的扩大204822CD74HC4046 与鉴相器之间的干扰20683VCO 中VCO与鉴相器同在的情况20683174HC4046832 用1个74HC4046进行的实验207 使用2个74HC4046进行的实验(VCO和鉴相器在不同的封装中)209 83384 鉴相器的死区210 用74HC4046进行死区影响的实验211841 与巴厘枚嘎模块VCO的组合使用213842PC28434046 中PC1与巴厘枚嘎模块VCO的组合使用217 与巴厘枚嘎模块VCO的组合使用220 84474HCT9046 锁相速度的改善22185 用二极管切换环路滤波器常数的方法222851 用模拟开关切换环路滤波器常数的方法224852 转换器进行预置电压相加的方法226 用D A853第9章实用的PLL频率合成器的设计与制作229(环路滤波器的详细设计与实测特性) 使用74HC4046的时钟频率合成器22991 替代1Hz～10MHz晶体的频率合成器229911 全部使用CMOS IC构成的频率合成器230912 环路滤波器的设计233913 输出波形235914 频谱235915 锁相速度238916 使用TLC2933构成的脉冲频率合成器23992 系列的概况239921TLC29xx 时钟频率合成器电路239922 环路滤波器的设计241923 输出波形频谱的测试243924 频率合成器24593HF 频率合成器电路245931HF 2环路滤波器常数的计算24893 频谱250933 锁相速度252934 频率基准信号用PLL2559440MHz 频率基准信号用PLL电路25594140MHz 环路滤波器的设计258942 输出波形260943 低失真的低频PLL电路26195951 低失真的低频PLL电路261 环路滤波器的设计264952 输出波形的合成267953附录B环路滤波器设计用规格化曲线图270附图:各公司4046的振荡频率控制电压特性270参考文献282。
PLL详解什么是锁相环呢？MCU的支撑电路一般需要外部时钟来给MCU提供时钟信号，而外部时钟的频率可能偏低，为了使系统更加快速稳定运行，需要提升系统所需要的时钟频率。
这就得用到锁相环了。
例如MCU用的外部晶振是16M的无源晶振，则可以通过锁相环PLL把系统时钟倍频到24M，从而给系统提供更高的时钟信号，提高程序的运行速度。
51单片机，AVR单片机内部没有锁相环电路，其系统时钟直接由外部晶振提供。
而XS128内部集成了锁相环电路，其系统时钟既可由外部晶振直接提供，也可以通过锁相环倍频后提供，当然，还有由XS128内部的时钟电路来提供（当其它来源提供的系统时钟不稳定时，内部时钟电路就起作用了，也就是自时钟模式）。
锁相环作为一个提供系统时钟的模块，是一个基本的模块，几乎每次编程序都得用到。
下面记一下怎样配置锁相环来设定想要的系统时钟。
锁相环PLL、自时钟模式和前面说的实时中断RTI、看门狗COP 都属于系统时钟与复位CRG中的模块，固前面用到的寄存器，这里有些会再用到。
在程序中配置锁相环的步骤如下：第一、禁止总中断；第二、寄存器CLKSEL的第七位置0，即CLKSEL_PLLSEL=0。
选择时钟源为外部晶振OSCCLK，在PLL程序执行前，内部总线频率为OSCCLK/2。
CLKSEL_PLLSEL=0时，系统时钟由外部晶振直接提供，系统内部总线频率=OSCCLK/2（OSCCLK为外部晶振频率）。
CLKSEL_PLLSEL=1时，系统时钟由锁相环提供，此时系统内部总线频率=PLLCLK/2 （PLLCLK为锁相环倍频后的频率）。
第三、禁止锁相环PLL，即PLLCTL_PLLON=0。
当PLLCTL_PLLON=0时，关闭PLL电路。
当PLLCTL_PLLON=1时，打开PLL电路。
第四、根据想要的时钟频率设置SYNR和REFDV两个寄存器。
SYNR和REFDV两个寄存器专用于锁相环时钟PLLCLK的频率计算，计算公式是：PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)其中，PLLCLK为PLL模块输出的时钟频率；OSCCLK为晶振频率；SYNR、REFDV分别为寄存器SYNR、REFDV中的值。
PLL(锁相环)电路原理及设计[收藏]PLL(锁相环)电路原理及设计在通信机等所使用的振荡电路，其所要求的频率范围要广，且频率的稳定度要高。
无论多好的LC振荡电路，其频率的稳定度，都无法与晶体振荡电路比较。
但是，晶体振荡器除了可以使用数字电路分频以外，其频率几乎无法改变。
如果采用PLL(锁相环)(相位锁栓回路，PhaseLockedLoop)技术，除了可以得到较广的振荡频率范围以外，其频率的稳定度也很高。
此一技术常使用于收音机，电视机的调谐电路上，以及CD唱盘上的电路。
一PLL(锁相环)电路的基本构成PLL(锁相环)电路的概要图1所示的为PLL(锁相环)电路的基本方块图。
此所使用的基准信号为稳定度很高的晶体振荡电路信号。
此一电路的中心为相位此较器。
相位比较器可以将基准信号与VCO (Voltage Controlled Oscillator……电压控制振荡器)的相位比较。
如果此两个信号之间有相位差存在时，便会产生相位误差信号输出。
(将VCO的振荡频率与基准频率比较，利用反馈电路的控制，使两者的频率为一致。
)利用此一误差信号，可以控制VCO的振荡频率，使VCO的相位与基准信号的相位(也即是频率)成为一致。
PLL(锁相环)可以使高频率振荡器的频率与基准频率的整数倍的频率相一致。
由于，基准振荡器大多为使用晶体振荡器，因此，高频率振荡器的频率稳定度可以与晶体振荡器相比美。
只要是基准频率的整数倍，便可以得到各种频率的输出。
从图1的PLL(锁相环)基本构成中，可以知道其是由VCO，相位比较器，基准频率振荡器，回路滤波器所构成。
在此，假设基准振荡器的频率为fr，VCO的频率为fo。
在此一电路中，假设frgt;fo时，也即是VC0的振荡频率fo比fr低时。
此时的相位比较器的输出PD 会如图2所示，产生正脉波信号，使VCO的振荡器频率提高。
相反地，如果frlt;fo时，会产生负脉波信号。
(此为利用脉波的边缘做二个信号的比较。
Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 12)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityTerm Project• Design 645MHz fractional-N PLL circuit: - fref = 40MHz, fout = 645MHz with 50% duty cycle - Due date: June 24th40MHzfref(1) (2)645MHzPFD(3)CP(4)VCO(5)2(6)foutPLL BW: ~500kHz16/17 k-bit ACCUM2W. Rhee, Institute of Microelectronics, Tsinghua UniversityTerm Project (continued)• Do followings: 1. Design loop filter for ~500kHz PLL bandwidth. 2. Draw open-loop gain Bode plot based on LPF design from (a). 3. Plot node 3, 4 and check the lock time. 4. Plot node 1, 2 after PLL is fully settled. What is the amount of static phase offset? 5. Plot node 5, 6 for 10 VCO cycles (i.e. zoom-in plot). 6. Estimate the spur level based on VCO gain and waveform at node 3. 7. Verify (f) result by having FFT and measure spur level at VCO output in dBc. E1. Plot eye diagram of VCO output and measure jitter in time domain. (extra) E2. Run phase noise simulation of open-loop VCO and calculate closed-loop RJ. (extra) E3. Calculate closed-loop RJ by defining approximated noise bandwidth. (extra) E4. Tell whether DJ or RJ is dominant. (extra) • Note: Ideal blocks allowed for PFD & LPF design3W. Rhee, Institute of Microelectronics, Tsinghua UniversityV. Applications 3. Clock Multiplier Unit (CMU)4W. Rhee, Institute of Microelectronics, Tsinghua UniversityCMU Design Considerations• Similar to RF frequency synthesizer - Use of frequency divider and PFD/CP - Trade-off between noise and spur • Different from RF frequency synthesizer - Less stringent lock-in time - Ultimately interested in pk-pk jitter. - Noisier supply voltage - Noisier reference clock - Lower supply voltage - Mostly in digital CMOS process - Ring VCO and on-chip LPF preferred.5W. Rhee, Institute of Microelectronics, Tsinghua UniversityJitter• Absolute jitter (long-term jitter) - Phase error w.r.t. ideal referenceΔTabs ,rms = lim1 2 ΔT12 + ΔT22 + ⋅ ⋅ ⋅ + ΔTN N →∞ N• Cycle-to-cycle jitter (short-term jitter) - No need for referenceΔTcc ,rms ≈ lim1 (T2 − T1 )2 + (T3 − T2 )2 + ⋅ ⋅ ⋅ + (TN − TN −1 )2 N →∞ N• Period jitter - For PLL, period jitter = absolute jitter.ΔTp ,rms = lim1 (T − T1 )2 + (T − T2 )2 + ⋅ ⋅ ⋅ + (T − TN −1 )2 N →∞ N*Note:Periodic jitter (PJ) is often considered DJ by sinusoidal modulation, which is different from period jitter.W. Rhee, Institute of Microelectronics, Tsinghua University6Total Jitter (TJ)RJpk-pk (14*σ)• Total jitter (TJpp) - RJpp + DJpp = 14 x RJrms + DJpp • Random jitter (RJ) - Non-systematic jitter - Gaussian distribution • Deterministic jitter (DJ) - Systematic jitter - Coupling and ISI - Duty cycle distortionDJDJ dominant (modulation)RJ dominant (noise)Pspurfo7W. Rhee, Institute of Microelectronics, Tsinghua UniversityRandom Jitter (RJ)Bathtub Curve• For BER = 10-12, RJpp = 14 x RJrmsRef: “Jitter Fundamentals,” Wavecrest Company8W. Rhee, Institute of Microelectronics, Tsinghua UniversityRJ and Noise Integration BandwidthfoCDR tracking BWPDLPFCDRN• CDR tracking BW should be considered for TXPLL design. - SONET: 50kHz – 80MHz - Typically (Baud Rate) / 1667 – (Baud Rate) / 29W. Rhee, Institute of Microelectronics, Tsinghua UniversitySupply Noise EffectfoCDR tracking BWPDLPFCDRN10W. Rhee, Institute of Microelectronics, Tsinghua UniversityJSSC’96, von Kaenel et al. Supply Noise ConsiderationSupply w/o NoiseSupply w/t Noise(f 3dBLess power but needs more careful design for 50% duty cycle.Cascaded PLLsParallel PLLsISSCC’03, Wong et al.Cascaded PLLsV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionInside PCCurrent ComingFB-DIMM•DDR2 DRAM + high-speed serial linkÆPoint-to-point serial link communication •Overcomes trade-off between speed and capacity.[Li, ITC’04], [PCI-SIG]s o 123H s H s e H s H s −Δτ=−⋅()[()()]()H 1(s)H 3(s)H 2(s)ΔτLC VCORing VCO[Noguchi, ISSCC’02][Herzel, JSSC’03][Moon, JSSC’04][Williams, CICC’04]Dual-Path VCOsTimeTimeVarious Coarse-Tuning Gains(with BW FINE = 1)Various Coarse-Tuning Bandwidths(with BW FINE = 1)(CppSim tool from M.I.T. used for simulation)PLL Behavioral Simulation(<80kHz)(10MHz)VDDINBINBIASOUT OUTBR1R2Narrowbanding (for coarse tuning)4th -pole of PLL (for fine tuning)Resistor noise contribution to PLLH(f)fF RCF BWLinear Amplifier and Noise ConsiderationPhase Noise PerformancesMeasured RJ VariationMeasured VCO Tuning CurvePSRR PerformanceV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionFractional-N PLL for Wireline Applications?Flexible Frequency Planning with ΔΣPLL•Conventional PLL makes it difficult to accommodate various reference clock frequencies.Digital Clock Generation with <1ppm Resolution•PLL with ring VCO needs wide bandwidth to suppress VCO noise.ÆLow f ref /f bw ratio makes it difficult to implement ΔΣfractional-N PLL.ÆSuffer from cycle-to-cycle jitter problem due to quantization noise.Fractional-N PLL for Digital SystemL f ) d B c /H z )Basic ConceptsEquivalent Discrete-Time Model Frequency ResponseL ) B c H zBehavioral Simulation Results500MHz Output Spectrum(Fref= 14.318MHz, N=37.15603)VCO Control Voltage•FIR-embedded frequency divider reduces output cycle-to-cycle jitter.ISCAS’07, Chi et al.Measured Output SpectraV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionElectromagnetic Interference (EMI)•Radiation emission is strictly regulated by FCC.•Can be reduced by shielded cables but expensive and bulky.ÆHow about modulating clock to reduce peak power?Modulation Profile Clock SpectrumCarrier(w/o modulation)Spread Spectrum ClockingJSSC’03, Chang et al.By Voltage ModulationBy Divider Modulation By ΔΣModulation ISSCC’99, Li et al.ISSCC’05, Lee et al.。
Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 9)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityHW #3• Design PFD and Charge Pump: - Goal: Determine the minimum pulse width ΔtDLY to avoid dead-zone. -- Show U, D, IU, ID, and IU – ID waveforms for 2 cycle slipping periods. -- First run w/o DLY and then run w/t DLY to demonstrate dead-zone effect. - Simplest functional design is ok. No high performance is necessary. -- Use of ideal gates is acceptable for PFD. -- Simple single-ended charge pump design is ok. - Due date: May 20thVDDDQ10MHzUΔtDLY?AVDDCLRICPDLY DQ9.98MHzD1μF (set Vinit = 1V)BCLR2W. Rhee, Institute of Microelectronics, Tsinghua UniversityCircuit Design – VCODeadzone Speed Differential? … Mismatch Vout compliance Noise Linearity Differential? Programmable? … On-chip? Leakage Area Coupling MIM cap? Differential? … LC or ring? Tuning range Noise PSRR Power Differential? …frefPFDCPLPFVCOfout/NSpeed Power Noise Differential? …3W. Rhee, Institute of Microelectronics, Tsinghua UniversityVCO Design Considerations• Architecture - LC or ring? - Differential or single-ended? • Tuning Range - Fundamental trade-off between tuning range and noise - Input control voltage range and CP output voltage compliance • Noise - Random noise - VCO gain, Q, … - Deterministic noise - PSRR, substrate noise coupling, … • Power consumption - LC for high frequency • Output amplitude - Check driving capability for frequency divider. • Oscillation condition - Carefully check over PVT variations4W. Rhee, Institute of Microelectronics, Tsinghua UniversityOscillator and VCOPhase Noise (Small Signal) Tuning Range (Large Signal)KVCOfofo• Fundamental tradeoff between noise and tuning range. • Best oscillator design does not necessarily guarantee best VCO!!5W. Rhee, Institute of Microelectronics, Tsinghua UniversityVCO Figure-of-Merit (FOM)FOM + ⎛ fo ⎞ 1 ⎜ ⎟ foffset ⎠ L(foffset ) ⋅ Pdc ⎝⎛ f PNfoffset − 20log ⎜ o ⎝ foffset ⎞ ⎛ Pdc ⎞ ⎟ + 10log ⎜ ⎟ ⎝ 1mW ⎠ ⎠2TraditionalFOM –With normalized power (RFIC’00, Plouchart et al.) Including tuning range & temperature (JSSC’01, Ham et al.) Including tuning range FTR [%] with normalized power (ISSCC’05, Kim et al.)FOM +2 ⎧ kT ⎛ f − fo ,min ⎞ ⎫ ⎪ ⎪ o ,max 10log ⎨ ⎜ ⎟ ⎬ − PNfoffset Pdc ⎝ foffset ⎠ ⎪ ⎪ ⎩ ⎭FOM –PNfoffset⎛ f FTR ⎞ ⎛ P ⎞ − 20log ⎜ o × + 10log ⎜ dc ⎟ ⎟ 10 ⎠ ⎝ 1mW ⎠ ⎝ foffset*Reference shown here may not be the first one for each FOM definition.6W. Rhee, Institute of Microelectronics, Tsinghua UniversityIII. PLL Design 2. Circuit Design AspectsE. VCO – LC VCORef: Razavi, “Design of Analog CMOS Integrated Circuits”, “RF Microelectronics”, and “Design of Integrated Circuits for Optical Communications”7W. Rhee, Institute of Microelectronics, Tsinghua UniversityLC VCORpωo =1 LC1 1 1 = + Qres Qind Qvar-Rp=1 1 1 + ≈ 5 30 4.3Active CircuitExample at 2.5GHz• Use variable capacitance to tune output frequency. • Noise performance is mostly determined by inductor Q.8W. Rhee, Institute of Microelectronics, Tsinghua UniversityMOS VaractorsSimple MOS Capacitor Accumulation-Mode Varactor• NFET in n-Well Accumulation-mode varactor • Offers monotonic capacitance variance.9W. Rhee, Institute of Microelectronics, Tsinghua UniversityDynamic Range and QCMAX = Cox ⋅ W ⋅ LCMIN ≈ Cgdo ⋅ WQvar ≈12k p (VGS − VT )ωoCox L2• Varactor design trade-off - To maximize Q, short channel length is needed. - To maximize tuning range, longer channel length is needed.10W. Rhee, Institute of Microelectronics, Tsinghua UniversityLoss Mechanism•(a) Series resistance-Wire resistance (low f) + skin effect (high f)•(b) Capacitive coupling to substrate •(c) Magnetic coupling to substrateNarrowband Lumped Model•RS : Low-frequency series resistance and skin resistance•C1,2: Capacitive coupling to substrate•C3,4: Substrate capacitance between different nodes•RS1,S2: Substrate resistanceLimited by RSLimited by RS1,2Asymmetric Inductor Symmetric InductorInductor Geometry•Moderate Q (~5 to 6 at 5GHz)•Small potential differencein adjacent turnsÆMinimum line spacing•Easier routing in cascaded stages.•Higher Q (~7 to 10 at 5GHz)•Large voltage difference in adjacent turns Æ2 to 3 times the min. spacing •Often faces routing difficulties.Band-Switching LC VCO with AFCJSSC’04, Lee et al.LC VCO with Pseudo-Differential InputCICCC’06, Soltanian et al.•PMOS/NMOS back-to-back varactorsÆPseudo-differential control input•Still sensitive to common mode voltage.ÆCommon mode set by inductorLC VCO with Quadrature Outputs•Quadrature generation with antiphase coupling.•VCO tuning can be also done by varying coupling factor.JSSC’03, Shin et al.III. PLL Design2. Circuit Design AspectsE. VCO–Ring VCORing VCO Jitter AnalysisISCAS’94, Weigandt et al.•Low jitter design needs high output swingÆHigh slew rate with high power consumptionVariable Delay LinesCurrent-Starved Variable LoadVariable Supply [Ref] K. Yang, “Delay-locked loops –An overview,”Phase-Locking in High Performance Systems, IEEE Press, 2003.•Low speed operation and very compact•Generates switching noiseCML Variable Delay LinesLoad Diode Load Active Load Negative-gm•Differential swing with current biasing.•More immune to supply noise.VCD with Phase Interpolation•VCD based on phase interpolation-Wideband operation-Can have differential inputVCD with Positive Feedback•VCD based on phase interpolation-Wideband operation-Can have differential inputV-to-I Converter with On-Chip Loop FilterSchematic ExampleMeasured Jitter vs. PLL Bandwidth•Jitter decreases as bandwidth increases.ÆOverall noise is dominated by VCO.III. PLL Design2. Circuit Design AspectsE. VCO–Relaxation VCORing VCO at Low Frequencies•Ring VCO for very low frequency operation-Increase number of stages-Reduce bias current-Increase transistor area (Increase both L & W)Relaxation VCOWith Grounded Capacitor With Floating Capacitor•Single-stage operation•Timing capacitor is well defined.Relaxation Oscillator with Grounded Capacitor•Frequency is defined by capacitor, current, and threshold.•Comparator and current switch limit speed performance.•Difficult to get 50% duty with UP/DN current mismatch.Relaxation Oscillator with Floating Capacitor•Single stage and symmetric structure.•Performance limited by nonlinear load.ÆNot popular in CMOS.A B X YRelaxation Oscillator with Constant Amplitude•Frequency defined by capacitor, current, and voltage swing.•Low power and low noise with single stage differential operation.•Wide tuning with multiple timing capacitors.ISCAS’98, RheeSchematic ExampleSimulation ResultsV-F Transfer Characteristic VCO GainFurther Variation •Differential control by PLL•Coarse tuning by bias current •Additional fine tuning by changing VSWIII. PLL Design2. Circuit Design AspectsE. VCO–Distributed-gain oscillators [Ref] R. Aparacio and A. Hajimir, “Circular-geometry oscillators,”IEEE Press, 2003.Frequency Range for Different VCOsISSCC’04, Aparacio et al.dc currentdc currentdcdcLLvirtualground pointpick up loopCenterpoint connection+-+++---V DDV DDV DDLL 'L'L'。
