非常经典 清华大学 李宇根 PLL讲义

Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 12)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityTerm Project• Design 645MHz fractional-N PLL circuit: - fref = 40MHz, fout = 645MHz with 50% duty cycle - Due date: June 24th40MHzfref(1) (2)645MHzPFD(3)CP(4)VCO(5)2(6)foutPLL BW: ~500kHz16/17 k-bit ACCUM2W. Rhee, Institute of Microelectronics, Tsinghua UniversityTerm Project (continued)• Do followings: 1. Design loop filter for ~500kHz PLL bandwidth. 2. Draw open-loop gain Bode plot based on LPF design from (a). 3. Plot node 3, 4 and check the lock time. 4. Plot node 1, 2 after PLL is fully settled. What is the amount of static phase offset? 5. Plot node 5, 6 for 10 VCO cycles (i.e. zoom-in plot). 6. Estimate the spur level based on VCO gain and waveform at node 3. 7. Verify (f) result by having FFT and measure spur level at VCO output in dBc. E1. Plot eye diagram of VCO output and measure jitter in time domain. (extra) E2. Run phase noise simulation of open-loop VCO and calculate closed-loop RJ. (extra) E3. Calculate closed-loop RJ by defining approximated noise bandwidth. (extra) E4. Tell whether DJ or RJ is dominant. (extra) • Note: Ideal blocks allowed for PFD & LPF design3W. Rhee, Institute of Microelectronics, Tsinghua UniversityV. Applications 3. Clock Multiplier Unit (CMU)4W. Rhee, Institute of Microelectronics, Tsinghua UniversityCMU Design Considerations• Similar to RF frequency synthesizer - Use of frequency divider and PFD/CP - Trade-off between noise and spur • Different from RF frequency synthesizer - Less stringent lock-in time - Ultimately interested in pk-pk jitter. - Noisier supply voltage - Noisier reference clock - Lower supply voltage - Mostly in digital CMOS process - Ring VCO and on-chip LPF preferred.5W. Rhee, Institute of Microelectronics, Tsinghua UniversityJitter• Absolute jitter (long-term jitter) - Phase error w.r.t. ideal referenceΔTabs ,rms = lim1 2 ΔT12 + ΔT22 + ⋅ ⋅ ⋅ + ΔTN N →∞ N• Cycle-to-cycle jitter (short-term jitter) - No need for referenceΔTcc ,rms ≈ lim1 (T2 − T1 )2 + (T3 − T2 )2 + ⋅ ⋅ ⋅ + (TN − TN −1 )2 N →∞ N• Period jitter - For PLL, period jitter = absolute jitter.ΔTp ,rms = lim1 (T − T1 )2 + (T − T2 )2 + ⋅ ⋅ ⋅ + (T − TN −1 )2 N →∞ N*Note:Periodic jitter (PJ) is often considered DJ by sinusoidal modulation, which is different from period jitter.W. Rhee, Institute of Microelectronics, Tsinghua University6Total Jitter (TJ)RJpk-pk (14*σ)• Total jitter (TJpp) - RJpp + DJpp = 14 x RJrms + DJpp • Random jitter (RJ) - Non-systematic jitter - Gaussian distribution • Deterministic jitter (DJ) - Systematic jitter - Coupling and ISI - Duty cycle distortionDJDJ dominant (modulation)RJ dominant (noise)Pspurfo7W. Rhee, Institute of Microelectronics, Tsinghua UniversityRandom Jitter (RJ)Bathtub Curve• For BER = 10-12, RJpp = 14 x RJrmsRef: “Jitter Fundamentals,” Wavecrest Company8W. Rhee, Institute of Microelectronics, Tsinghua UniversityRJ and Noise Integration BandwidthfoCDR tracking BWPDLPFCDRN• CDR tracking BW should be considered for TXPLL design. - SONET: 50kHz – 80MHz - Typically (Baud Rate) / 1667 – (Baud Rate) / 29W. Rhee, Institute of Microelectronics, Tsinghua UniversitySupply Noise EffectfoCDR tracking BWPDLPFCDRN10W. Rhee, Institute of Microelectronics, Tsinghua UniversityJSSC’96, von Kaenel et al. Supply Noise ConsiderationSupply w/o NoiseSupply w/t Noise(f 3dBLess power but needs more careful design for 50% duty cycle.Cascaded PLLsParallel PLLsISSCC’03, Wong et al.Cascaded PLLsV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionInside PCCurrent ComingFB-DIMM•DDR2 DRAM + high-speed serial linkÆPoint-to-point serial link communication •Overcomes trade-off between speed and capacity.[Li, ITC’04], [PCI-SIG]s o 123H s H s e H s H s −Δτ=−⋅()[()()]()H 1(s)H 3(s)H 2(s)ΔτLC VCORing VCO[Noguchi, ISSCC’02][Herzel, JSSC’03][Moon, JSSC’04][Williams, CICC’04]Dual-Path VCOsTimeTimeVarious Coarse-Tuning Gains(with BW FINE = 1)Various Coarse-Tuning Bandwidths(with BW FINE = 1)(CppSim tool from M.I.T. used for simulation)PLL Behavioral Simulation(<80kHz)(10MHz)VDDINBINBIASOUT OUTBR1R2Narrowbanding (for coarse tuning)4th -pole of PLL (for fine tuning)Resistor noise contribution to PLLH(f)fF RCF BWLinear Amplifier and Noise ConsiderationPhase Noise PerformancesMeasured RJ VariationMeasured VCO Tuning CurvePSRR PerformanceV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionFractional-N PLL for Wireline Applications?Flexible Frequency Planning with ΔΣPLL•Conventional PLL makes it difficult to accommodate various reference clock frequencies.Digital Clock Generation with <1ppm Resolution•PLL with ring VCO needs wide bandwidth to suppress VCO noise.ÆLow f ref /f bw ratio makes it difficult to implement ΔΣfractional-N PLL.ÆSuffer from cycle-to-cycle jitter problem due to quantization noise.Fractional-N PLL for Digital SystemL f ) d B c /H z )Basic ConceptsEquivalent Discrete-Time Model Frequency ResponseL ) B c H zBehavioral Simulation Results500MHz Output Spectrum(Fref= 14.318MHz, N=37.15603)VCO Control Voltage•FIR-embedded frequency divider reduces output cycle-to-cycle jitter.ISCAS’07, Chi et al.Measured Output SpectraV. Applications3. Clock Multiplier Unit (CMU)A. Uniform BW control for PCIe2B. ΔΣPLL for digital clock generationC. S-S clocking for EMI reductionElectromagnetic Interference (EMI)•Radiation emission is strictly regulated by FCC.•Can be reduced by shielded cables but expensive and bulky.ÆHow about modulating clock to reduce peak power?Modulation Profile Clock SpectrumCarrier(w/o modulation)Spread Spectrum ClockingJSSC’03, Chang et al.By Voltage ModulationBy Divider Modulation By ΔΣModulation ISSCC’99, Li et al.ISSCC’05, Lee et al.。

Spring Semester, 2008PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 9)Woogeun Rhee Institute of Microelectronics Tsinghua UniversityHW #3• Design PFD and Charge Pump: - Goal: Determine the minimum pulse width ΔtDLY to avoid dead-zone. -- Show U, D, IU, ID, and IU – ID waveforms for 2 cycle slipping periods. -- First run w/o DLY and then run w/t DLY to demonstrate dead-zone effect. - Simplest functional design is ok. No high performance is necessary. -- Use of ideal gates is acceptable for PFD. -- Simple single-ended charge pump design is ok. - Due date: May 20thVDDDQ10MHzUΔtDLY?AVDDCLRICPDLY DQ9.98MHzD1μF (set Vinit = 1V)BCLR2W. Rhee, Institute of Microelectronics, Tsinghua UniversityCircuit Design – VCODeadzone Speed Differential? … Mismatch Vout compliance Noise Linearity Differential? Programmable? … On-chip? Leakage Area Coupling MIM cap? Differential? … LC or ring? Tuning range Noise PSRR Power Differential? …frefPFDCPLPFVCOfout/NSpeed Power Noise Differential? …3W. Rhee, Institute of Microelectronics, Tsinghua UniversityVCO Design Considerations• Architecture - LC or ring? - Differential or single-ended? • Tuning Range - Fundamental trade-off between tuning range and noise - Input control voltage range and CP output voltage compliance • Noise - Random noise - VCO gain, Q, … - Deterministic noise - PSRR, substrate noise coupling, … • Power consumption - LC for high frequency • Output amplitude - Check driving capability for frequency divider. • Oscillation condition - Carefully check over PVT variations4W. Rhee, Institute of Microelectronics, Tsinghua UniversityOscillator and VCOPhase Noise (Small Signal) Tuning Range (Large Signal)KVCOfofo• Fundamental tradeoff between noise and tuning range. • Best oscillator design does not necessarily guarantee best VCO!!5W. Rhee, Institute of Microelectronics, Tsinghua UniversityVCO Figure-of-Merit (FOM)FOM + ⎛ fo ⎞ 1 ⎜ ⎟ foffset ⎠ L(foffset ) ⋅ Pdc ⎝⎛ f PNfoffset − 20log ⎜ o ⎝ foffset ⎞ ⎛ Pdc ⎞ ⎟ + 10log ⎜ ⎟ ⎝ 1mW ⎠ ⎠2TraditionalFOM –With normalized power (RFIC’00, Plouchart et al.) Including tuning range & temperature (JSSC’01, Ham et al.) Including tuning range FTR [%] with normalized power (ISSCC’05, Kim et al.)FOM +2 ⎧ kT ⎛ f − fo ,min ⎞ ⎫ ⎪ ⎪ o ,max 10log ⎨ ⎜ ⎟ ⎬ − PNfoffset Pdc ⎝ foffset ⎠ ⎪ ⎪ ⎩ ⎭FOM –PNfoffset⎛ f FTR ⎞ ⎛ P ⎞ − 20log ⎜ o × + 10log ⎜ dc ⎟ ⎟ 10 ⎠ ⎝ 1mW ⎠ ⎝ foffset*Reference shown here may not be the first one for each FOM definition.6W. Rhee, Institute of Microelectronics, Tsinghua UniversityIII. PLL Design 2. Circuit Design AspectsE. VCO – LC VCORef: Razavi, “Design of Analog CMOS Integrated Circuits”, “RF Microelectronics”, and “Design of Integrated Circuits for Optical Communications”7W. Rhee, Institute of Microelectronics, Tsinghua UniversityLC VCORpωo =1 LC1 1 1 = + Qres Qind Qvar-Rp=1 1 1 + ≈ 5 30 4.3Active CircuitExample at 2.5GHz• Use variable capacitance to tune output frequency. • Noise performance is mostly determined by inductor Q.8W. Rhee, Institute of Microelectronics, Tsinghua UniversityMOS VaractorsSimple MOS Capacitor Accumulation-Mode Varactor• NFET in n-Well Accumulation-mode varactor • Offers monotonic capacitance variance.9W. Rhee, Institute of Microelectronics, Tsinghua UniversityDynamic Range and QCMAX = Cox ⋅ W ⋅ LCMIN ≈ Cgdo ⋅ WQvar ≈12k p (VGS − VT )ωoCox L2• Varactor design trade-off - To maximize Q, short channel length is needed. - To maximize tuning range, longer channel length is needed.10W. Rhee, Institute of Microelectronics, Tsinghua UniversityLoss Mechanism•(a) Series resistance-Wire resistance (low f) + skin effect (high f)•(b) Capacitive coupling to substrate •(c) Magnetic coupling to substrateNarrowband Lumped Model•RS : Low-frequency series resistance and skin resistance•C1,2: Capacitive coupling to substrate•C3,4: Substrate capacitance between different nodes•RS1,S2: Substrate resistanceLimited by RSLimited by RS1,2Asymmetric Inductor Symmetric InductorInductor Geometry•Moderate Q (~5 to 6 at 5GHz)•Small potential differencein adjacent turnsÆMinimum line spacing•Easier routing in cascaded stages.•Higher Q (~7 to 10 at 5GHz)•Large voltage difference in adjacent turns Æ2 to 3 times the min. spacing •Often faces routing difficulties.Band-Switching LC VCO with AFCJSSC’04, Lee et al.LC VCO with Pseudo-Differential InputCICCC’06, Soltanian et al.•PMOS/NMOS back-to-back varactorsÆPseudo-differential control input•Still sensitive to common mode voltage.ÆCommon mode set by inductorLC VCO with Quadrature Outputs•Quadrature generation with antiphase coupling.•VCO tuning can be also done by varying coupling factor.JSSC’03, Shin et al.III. PLL Design2. Circuit Design AspectsE. VCO–Ring VCORing VCO Jitter AnalysisISCAS’94, Weigandt et al.•Low jitter design needs high output swingÆHigh slew rate with high power consumptionVariable Delay LinesCurrent-Starved Variable LoadVariable Supply [Ref] K. Yang, “Delay-locked loops –An overview,”Phase-Locking in High Performance Systems, IEEE Press, 2003.•Low speed operation and very compact•Generates switching noiseCML Variable Delay LinesLoad Diode Load Active Load Negative-gm•Differential swing with current biasing.•More immune to supply noise.VCD with Phase Interpolation•VCD based on phase interpolation-Wideband operation-Can have differential inputVCD with Positive Feedback•VCD based on phase interpolation-Wideband operation-Can have differential inputV-to-I Converter with On-Chip Loop FilterSchematic ExampleMeasured Jitter vs. PLL Bandwidth•Jitter decreases as bandwidth increases.ÆOverall noise is dominated by VCO.III. PLL Design2. Circuit Design AspectsE. VCO–Relaxation VCORing VCO at Low Frequencies•Ring VCO for very low frequency operation-Increase number of stages-Reduce bias current-Increase transistor area (Increase both L & W)Relaxation VCOWith Grounded Capacitor With Floating Capacitor•Single-stage operation•Timing capacitor is well defined.Relaxation Oscillator with Grounded Capacitor•Frequency is defined by capacitor, current, and threshold.•Comparator and current switch limit speed performance.•Difficult to get 50% duty with UP/DN current mismatch.Relaxation Oscillator with Floating Capacitor•Single stage and symmetric structure.•Performance limited by nonlinear load.ÆNot popular in CMOS.A B X YRelaxation Oscillator with Constant Amplitude•Frequency defined by capacitor, current, and voltage swing.•Low power and low noise with single stage differential operation.•Wide tuning with multiple timing capacitors.ISCAS’98, RheeSchematic ExampleSimulation ResultsV-F Transfer Characteristic VCO GainFurther Variation •Differential control by PLL•Coarse tuning by bias current •Additional fine tuning by changing VSWIII. PLL Design2. Circuit Design AspectsE. VCO–Distributed-gain oscillators [Ref] R. Aparacio and A. Hajimir, “Circular-geometry oscillators,”IEEE Press, 2003.Frequency Range for Different VCOsISSCC’04, Aparacio et al.dc currentdc currentdcdcLLvirtualground pointpick up loopCenterpoint connection+-+++---V DDV DDV DDLL 'L'L'。