低功耗LVDS时钟扇出缓冲器

LVDS原理及设计指南LVDS（Low Voltage Differential Signaling）是一种低电压差分传输技术，常用于高速数据通信和时钟分配系统。

它通过使用两条平衡的信号线（一个正极和一个负极）来传输数据，以减少噪音干扰，提供更高的数据传输速率和更低的功耗。

LVDS的原理是将要传输的数据进行编码，然后在发送端将编码后的信号通过一个差分发射器发送出去。

在接收端，差分接收器将接收到的信号进行解码，并还原为原始数据。

差分发射器和差分接收器之间通过两条平衡的信号线相连，使得信号可以在传输过程中保持高的抗干扰能力。

为了实现高速数据传输和低功耗，设计LVDS系统时需要注意以下几点：1.选择合适的传输线：LVDS系统常用的传输线有两对铜排、双绞线和屏蔽电缆。

传输线的选择应根据系统需求和环境条件来确定，以保证信号传输的稳定性和可靠性。

2.保持信号的差分平衡：在设计LVDS系统时，传输线的长度和阻抗应保持一致，以保证差分信号的平衡性。

同时，在PCB设计中，需要采取合适的布线方式，如使用相邻层的信号层和地层进行屏蔽，以减少信号的串扰。

3.电源和地线的设计：为了保证LVDS系统的稳定性和可靠性，需要为差分发射器和差分接收器提供稳定的电源和地线。

一般应采用低噪声的电源和地线设计，并保持电源和地线与传输线相互独立，以防止互相干扰。

4.噪声抑制和滤波措施：在LVDS系统中，噪声干扰是一个常见的问题。

为了减少噪声的影响，可以采用电源滤波器、地线滤波器、抗干扰电容和电感等措施，以有效抑制噪声的干扰。

5.时钟分配的设计：对于需要传输时钟信号的LVDS系统，时钟分配的设计尤为重要。

时钟线应尽量短，以保证时钟信号的稳定性和准确性。

同时，需要采用低噪声的时钟源，并根据时钟分配的延时要求进行恰当的布线和抗干扰措施。

6.PCB设计布局：在LVDS系统的PCB设计中，需要合理规划和布局不同电路模块的位置，以减少信号的干扰和串扰。

BUFG，IBUFG，BUFGP，IBUFGDS等含义以及使用目前，大型设计一般推荐使用同步时序电路。

同步时序电路基于时钟触发沿设计，对时钟的周期、占空比、延时和抖动提出了更高的要求。

为了满足同步时序设计的要求，一般在FPGA设计中采用全局时钟资源驱动设计的主时钟，以达到最低的时钟抖动和延迟。

FPGA全局时钟资源一般使用全铜层工艺实现，并设计了专用时钟缓冲与驱动结构，从而使全局时钟到达芯片内部的所有可配置单元(CLB)、I/O单元(IOB)和选择性块RAM(Block Select RAM)的时延和抖动都为最小。

为了适应复杂设计的需要，Xilinx的FPGA中集成的专用时钟资源与数字延迟锁相环(DLL)的数目不断增加，最新的Virtex II器件最多可以提供16个全局时钟输入端口和8个数字时钟管理模块(DCM)。

与全局时钟资源相关的原语常用的与全局时钟资源相关的Xilinx器件原语包括：IBUFG、IBUFGDS、BUFG、BUFGP、BUFGCE、BUFGMUX、BUFGDLL和DCM等，如图1所示。

1. IBUFG即输入全局缓冲，是与专用全局时钟输入管脚相连接的首级全局缓冲。

所有从全局时钟管脚输入的信号必须经过IBUF元，否则在布局布线时会报错。

IBUFG支持AGP、CTT、GTL、GTLP、HSTL、LVCMOS、LVDCI、LVDS、LVPECL、LVTTL、PCI、PCIX和SSTL等多种格式的IO标准。

G 单2. IBUFGDS是IBUFG的差分形式，当信号从一对差分全局时钟管脚输入时，必须使用IBUFGDS作为全局时钟输入缓冲。

IBUFG支持BLVDS、LDT、LVDSEXT、LVDS、LVPECL和ULVDS等多种格式的IO标准。

3. BUFG是全局缓冲，它的输入是IBUFG的输出，BUFG的输出到达FPGA内部的IOB、CLB、选择性块RAM的时钟延迟和抖动最小。

4. BUFGCE是带有时钟使能端的全局缓冲。

AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x,Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families This application note is intended to provide optional, alternative output terminationsfor converting a low-power HCSL output clock from a Skyworks PCIe clock generatoror buffer device into a LVPECL, LVDS, or CML formatted clock. These optional termi-nations are particularly useful in applications that require both 100 MHz PCIe output clocks, as well as 100 MHz LVDS, LVPECL, or CML output clocks for FPGAs, SGMII,or other chipsets. Rather than using separate clock generators or oscillators to satisfy these system requirements, one can utilize a single-clock generator or buffer IC from Skyworks and employ different terminations on each output to achieve the desired results. It is relevant to note all Skyworks devices that provide HCSL PCIe outputs utilize low-power, push-pull buffers as opposed to constant current mode buffers. There are many advantages to using low-power, push-pull output buffers, including lower power consumption, elimination of external termination resistors, and overall reduction in total PCB area.KEY FEATURES OR KEY POINTS•Translate HCSL to LVPECL, LVDS or CML levels•Reduce Power Consumption•Simplify BOM AVL1. Conversion of HCSL Signals to LVPECL SignalsA low-power, push-pull HCSL output clock can be converted to either 2.5 V or 3.3 V LVPECL standards by using an output termination as shown in Figure 1.1 Termination Scheme for HCSL to LVPECL Conversion on page 2. Figure 1.2 Oscilloscope Measurement of LVPECL Conversion on page 2 shows the output clock at the measurement point indicated in Figure 1.1 Termination Scheme for HCSL to LVPECL Conversion on page 2. VCC supply is required to set the common mode voltage at the receiver end. Table 1.1 Resistor Selection for Different VCC Standards (LVPECL Signal Conversion) on page 3 lists the resistor selection based on VCC.GNDFigure 1.1. Termination Scheme for HCSL to LVPECL ConversionFigure 1.2. Oscilloscope Measurement of LVPECL ConversionTable 1.1. Resistor Selection for Different VCC Standards (LVPECL Signal Conversion)Table 1.2. Series Resistor Selection for PCIe Clock Generators and Buffers2. Conversion of HCSL Signals to LVDS SignalsOne can also convert a low-power, push-pull HCSL clock output to a 1.8 V, 2.5 V, or 3.3 V LVDS clock output. The recommended termination scheme is shown in Figure 2.1 Termination Scheme for Low-Power HCSL to LVDS Conversion(When Receiver has no Termination or Internal 100 Ω Termination) on page 4, with the corresponding oscilloscope measurement shown in Figure 2.2 Oscilloscope Measurement of LVDS Conversion(When Receiver has no Internal Termination) on page 4 (at the measurement point indicated in Figure 2.1 Termination Scheme for Low-Power HCSL to LVDS Conversion(When Receiver has no Termination or Internal 100 Ω Termination) on page 4).GNDFigure 2.1. Termination Scheme for Low-Power HCSL to LVDS Conversion(When Receiver has no Termination or Internal 100 Ω Termination)Figure 2.2. Oscilloscope Measurement of LVDS Conversion(When Receiver has no Internal Termination)The swing will be reduced by 50% by an internal or external termination (the signal will be similar to the signal seen in Figure 2.4 Oscilloscope Measurement of LVDS Conversion(When Receiver has Internal or External 100 Ω Termination) on page 5). If the receiver does not have an internal 100 Ω termination,an external 100 Ω termination may be added, as shown in Figure 2.3 Termination Scheme for Low-Power HCSL to LVDS Conversion (When Receiver has no Internal 100 Ω Termination) on page 5.GNDFigure 2.3. Termination Scheme for Low-Power HCSL to LVDS Conversion(When Receiver has no Internal 100 Ω Termination)Figure 2.4. Oscilloscope Measurement of LVDS Conversion (When Receiver has Internal or External 100 Ω Termination)The resistor selection guide for different VCC values at the receiver end is given in Table 2.1 Resistor Selection on page 5.Table 2.1. Resistor SelectionFor series resistor selection of PCIe clock generators and buffers, see Table 1.2 Series Resistor Selection for PCIe Clock Generators and Buffers on page 3.Buffer Families • Conversion of HCSL Signals to CML Signals (AC Coupled to Receivers)3. Conversion of HCSL Signals to CML Signals (AC Coupled to Receivers)AC coupling is the recommended method for converting low-power HCSL signals to CML. The receiver should be able to generate the references needed to generate the common mode for CML signals. The recommended schematic is shown in Figure 3.1 Termination Scheme for HCSL to CML AC Coupling on page 6. It is also important to note that many CML receivers come with internal 50 Ωterminations to VCC, as shown in Figure 3.2 Typical CML Receiver Circuit Structure on page 6. Such internal terminations can reduce the signal swing by 50%.Figure 3.1. Termination Scheme for HCSL to CML AC CouplingFigure 3.2. Typical CML Receiver Circuit StructureBuffer Families • Conclusion4. ConclusionThis application note details methods in which low-power HCSL output clocks from the Si5211x, Si5213x, Si5214x, Si5216x, Si5310x, Si5311x, Si5315x, and Si522xx device families can be used to drive receivers that use other differential formats, specifically LVPECL, LVDS, and CML standards.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne ®, SkyBlue™, Skyworks Green™, Clockbuilder ®, DSPLL ®, ISOmodem ®, ProSLIC ®, and SiPHY ® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.Portfolio/ia/timingSW/HW/CBProQuality/qualitySupport & Resources/supportClockBuilder ProCustomize Skyworks clock generators, jitter attenuators and networksynchronizers with a single tool. With CBPro you can control evaluationboards, access documentation, request a custom part number, export for in-system programming and more!/CBPro。

Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL Fanout BufferICS8535-01General DescriptionThe ICS8535-01is a low skew,high performance 1-to-4LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer.The ICS8535-01has two single ended clock inputs.the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels.The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin.Guaranteed output and part-to-part skew characteristics make the ICS8535-01ideal for those applications demanding well defined performance and repeatability.6 7 89 1019 20 18 17 1612345V CC Q2nQ2V CC nc1314151211Q3nQ3V CC V EE CLK_ENQ 0n Q 0Q 1n Q 1V C Cn cC L K 0C L K _S E LC L K 1n c12345678910Q0nQ0V CC Q1nQ1Q2nQ2V CC Q3nQ320191817161514131211V EE CLK_EN CLK_SELCLK0nc CLK1nc nc nc V CCICS8535-0120-Lead VFQFN4mm x 4mm x 0.9body packageK PackageTop ViewICS8535-0120-Lead TSSOP4.4mm x 6.5mm x 0.92body packageG PackageTop ViewPin AssignmentFeatures•Four differential 3.3V LVPECL outputs•Selectable CLK0or CLK1inputs for redundant and multiple frequency fanout applications•CLK0or CLK1can accept the following input levels:LVCMOS or LVTTL•Maximum output frequency:266MHz•T ranslates LVCMOS and LVTTL levels to 3.3V LVPECL levels •Output skew:30ps (maximum)•Part-to-part skew:250ps (maximum)•Propagation delay:1.9ns (maximum)•Additive phase jitter,RMS:<0.09ps (typical)•3.3V operating supply•0°C to 70°C ambient operating temperature •Lead-free (RoHS 6)packagingBlock DiagramICS8535-01 DATA SHEETPin Descriptions and CharacteristicsTable 1.Pin Descriptions 1Table 2.Pin CharacteristicsICS8535-01 DATA SHEETFigure 1.Table 3A.Control Input Function TableCLK0, CLK1CLK_ENnQ0:nQ3Q0:Q3Table 3B.Clock Input Function TableICS8535-01 DATA SHEETAbsolute Maximum RatingsNOTE:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress specifications only.Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics or AC Characteristics is not implied.Exposure to absolute maximum rating conditions for extended periods may affect product reliability.DC Electrical CharacteristicsTable 4A.Power Supply DC Characteristics,V CC =3.3V±5%,T A =0°C to 70°CTable 4B.LVCMOS/LVTTL DC Characteristics,V CC =3.3V±5%,T A =0°C to 70°CTable 4C.LVPECL DC Characteristics,V CC =3.3V±5%,T A =0°C to 70°CCCICS8535-01 DATA SHEETAC CharacteristicsTable5.AC Characteristics,V CC =3.3V±5%,T A =0°C to 70°C 1The part does not add jitter.NOTE 2:Measured from the V CC /2of the input to the differential output crosspoint.NOTE 3:Defined as skew between outputs at the same supply voltage and with equal load conditions.Measured at the output differentialcrosspointsNOTE 4:This parameter is defined in accordance with JEDEC Standard 65.NOTE 5:Defined as skew between outputs on different devices operating at the same supply voltages and with equal load ingthe same type of inputs on each device,the outputs are measured at the differential crosspoints.NOTE 6:Driving only one input clock.ICS8535-01 DATA SHEETAdditive Phase JitterThe spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise.This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications.Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental.This ratio is expressed in decibels (dBm)or a ratioof the power in the 1Hz band to the power in the fundamental.When the required offset is specified,the phase noise is called a dBc value,which simply means dBm at a specified offset from the fundamental.By investigating jitter in the frequency domain,we get a betterunderstanding of its effects on the desired application over the entire time record of the signal.It is mathematically possible to calculate an expected bit error rate given a phase noise plot.As with most timing specifications,phase noise measurements have issues.The primary issue relates to the limitations of the equipment.Often the noise floor of the equipment is higher than the noise floorof the device.This is illustrated above.The device meets the noise floor of what is shown,but can actually be lower.The phase noise is dependent on the input source and measurement equipment.N o i s e P o w e r (d B c /H z )Offset Frequency (Hz)Input/Output Additive Phase Jitter at 156.25MHz =0.09ps (typical)1k10k100k1M10M-190-180-170-160-150-140-130-120-110-100-90-80-70-60-50-40-30-20-100100MICS8535-01 DATA SHEET Parameter MeasurementInformation3.3V Output Load Test CircuitOutput SkewPropagation DelayPart-to-Part SkewOutput Rise/Fall TimeOutput Duty Cycle/Pulse Width/PeriodICS8535-01 DATA SHEETApplications InformationRecommendations for Unused Input PinsInputs:CLK InputFor applications not requiring the use of a clock input,it can be left floating.Though not required,but for additional protection,a 1k Ωresistor can be tied from the CLK input to ground.LVCMOS Control PinsAll control pins have internal pullups;additional resistance is not required but can be added for additional protection.A 1k Ωresistor can be used.Outputs:LVPECL OutputsAll unused LVPECL outputs can be left floating.We recommend that there is no trace attached.Both sides of the differential output pair should either be left floating or terminated.Termination for 3.3V LVPECL OutputsThe clock layout topology shown below is a typical termination for LVPECL outputs.The two different layouts mentioned are recommended only as guidelines.The differential output is a low impedance follower output thatgenerate ECL/LVPECL compatible outputs.Therefore,terminating resistors (DC current path to ground)or current sources must be used for functionality.These outputs are designed to drive 50Ωtransmission lines.Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.Figure 2A and Figure 2B show two different layouts which arerecommended only as guidelines.Other suitable clock layouts may exist and it would be recommended that the board designerssimulate to guarantee compatibility across all printed circuit and clock component process variations.Figure 2A.3.3V LVPECL Output Termination Figure 2B.3.3V LVPECL Output TerminationICS8535-01 DATA SHEETSchematic ExampleFigure 3shows a schematic example of the ICS8535-01.In this example,the CLK0input is selected.The decoupling capacitors should be physically located near the power pin.For ICS8535-01,the unused clock outputs can be left floating.Figure 3.ICS8535-01Schematic ExampleICS8535-01 DATA SHEETPower ConsiderationsThis section provides information on power dissipation and junction temperature for the ICS8535-01.Equations and example calculations are also provided.1.Power Dissipation.The total power dissipation for the ICS8535-01is the sum of the core power plus the power dissipated in the load(s).The following is the power dissipation for V CC =3.3V +5%=3.465V ,which gives worst case results.NOTE:Please refer to Section 3for details on calculating power dissipated in the load.•Power (core)MAX =V CC_MAX *I EE_MAX =3.465V *50mA =173.25mW •Power (outputs)MAX =30mW/Loaded Output pairIf all outputs are loaded,the total power is 4*30mW =120mWTotal Power_MAX (3.465V ,with all outputs switching)=173.25mW +120mW =293.25mW 2.Junction Temperature.Junction temperature,Tj,is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.The maximum recommended junction temperature is 125°C.The equation for Tj is as follows:Tj =θJA *Pd_total +T A Tj =Junction T emperatureθJA =Junction-to-Ambient Thermal ResistancePd_total =T otal Device Power Dissipation (example calculation is in section 1above)T A =Ambient T emperatureIn order to calculate junction temperature,the appropriate junction-to-ambient thermal resistance θJA must be used.Assuming a moderate air flow of 200linear feet per minute and a multi-layer board,the appropriate value is 66.6°C/W per T able 6A below.Therefore,Tj for an ambient temperature of 70°C with all outputs switching is:70°C +0.293W *66.6°C/W =89.5°C.This is below the limit of 125°C.This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs,supply voltage,air flow and the type of board (single layer or multi-layer).Table 6A.Thermal Resistance θfor 20-Lead TSSOP ,Forced ConvectionNOTE:Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.Table 6B.θvs.Air Flow Table for 20-Lead VFQFNICS8535-01 DATA SHEET 3.Calculationsand Equations.The purpose of this section is to derive the power dissipated into the load.LVPECL output driver circuit and termination are shown in Figure4.Figure4.LVPECL Driver Circuit and TerminationT o calculate worst case power dissipation into the load,use the following equations which assume a50Ωload,and a termination voltage of V CC–2V.•For logic high,V OUT=V OH_MAX=V CC_MAX–0.9V(V CC_MAX–V OH_MAX)=0.9V•For logic low,V OUT=V OL_MAX=V CO_MAX–1.7V(V CC_MAX–V OL_MAX)=1.7VPd_H is power dissipation when the output drives high.Pd_L is the power dissipation when the output drives low.Pd_H=[(V OH_MAX–(V CC_MAX–2V))/R L]*(V CC_MAX–V OH_MAX)=[(2V-(V CC_MAX–V OH_MAX))/R L]*(V CC_MAX–V OH_MAX)=[(2V-0.9V)/50Ω]*0.9V=19.8mWPd_L=[(V OL_MAX–(V CC_MAX–2V))/R L]*(V CC_MAX–V OL_MAX)=[(2V–(V CC_MAX–V OL_MAX))/R L]*(V CC_MAX–V OL_MAX)=[(2V–1.7V)/50Ω]*1.7V=10.2mWT otal Power Dissipation per output pair=Pd_H+Pd_L=30mWICS8535-01 DATA SHEETReliability InformationNOTE:Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.Table 7B.θvs.Air Flow Table for 20-Lead VFQFNTransistor CountThe transistor count for the IS8535-01is 412.Table 7A.θJA vs.Air Flow Table for a 20-Lead TSSOPICS8535-01 DATA SHEETPackage Outline and Package DimensionsICS8535-01 DATA SHEETPackage Outline and Package Dimensions (continued)Package Outline -K Suffix for 20-Lead VFQFNReference Document:JEDEC Publication 95,MO-220NOTE:The drawing and dimension data originate from IDT package outline drawing PSC-4170,rev03.1.Dimensions and tolerances conform to ASME Y14.5M-19942.All dimensions are in millimeters.All angles are in degrees.3.N is the total number of terminals.4.All specifications comply with JEDEC MO-220.Table 9.Package Dimensions for 20-Lead VFQFNICS8535-01 DATA SHEETOrdering InformationTable10.Ordering InformationICS8535-01 DATA SHEETRevision History SheetICS8535-01 DATA SHEETDISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. 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Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputsand Frequency Range from dc to 200 MHzThe Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distri-bution and redundant clocking applications. The family utilizes Skyworks advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR performance and eliminates the need for external components simplifying low jitter clock distribution in noisy environments.The CMOS buffers are available in multiple configurations with 8 outputs(Si53360/61/65), or dual banks of 6 outputs each (Si53362). These buffers can be paired with the Si534x clock generators and Si5xx oscillators to deliver end-to-end clock tree performance.KEY FEATURES•Low additive jitter: 120 fs rms•Built-in LDOs for high PSRR performance •Up to 12 LVCMOS Outputs from LVCMOS inputs•Frequency range: dc to 200 MHz •Multiple configuration options•Dual Bank option•2:1 Input MUX option•RoHS compliant, Pb-free •Temperature range: –40 to +85 °CCLK0CLK1CLK_SEL CLKTable of Contents1. Ordering Guide (3)2. Functional Description (4)2.1 LVCMOS Input Termination (4)2.2 Input Mux (4)2.3 Output Clock Termination Options (5)2.4 AC Timing Waveforms (6)2.5 Power Supply Noise Rejection (6)2.6 Typical Phase Noise Performance: Single-Ended Input Clock (7)2.7 Input Mux Noise Isolation (8)3. Electrical Specifications (9)4. Detailed Block Diagrams (12)5. Si5336x Pin Descriptions (15)5.1 Si53360 Pin Descriptions (15)5.2 Si53361 Pin Descriptions (17)5.3 Si53362 Pin Descriptions (19)5.4 Si53365 Pin Descriptions (21)6. Package Outline (22)6.1 16-Pin TSSOP Package (22)6.2 16-Pin QFN Package (24)6.3 24-Pin QFN Package (25)7. PCB Land Pattern (26)7.1 16-Pin TSSOP Land Pattern (26)7.2 16-Pin QFN Land Pattern (27)7.3 24-Pin QFN Land Pattern (29)8. Top Markings (31)8.1 Si53360/65 Top Markings (31)8.2 Si53361 Top Marking (32)8.3 Si53362 Top Marking (33)9. Revision History (34)Si53360/61/62/65 Data Sheet • Ordering Guide1. Ordering GuideTable 1.1. Si5336x Ordering Guide2. Functional DescriptionThe Si53360/61/62/65 are a family of low-jitter, low skew, fixed format (LVMCOS) buffers. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations).2.1 LVCMOS Input TerminationThe table below summarizes the various ac- and dc-coupling options supported by the LVCMOS device, and the figure shows the recommended input clock termination.Table 2.1. LVCMOS Input Clock OptionsV DDCMOSDriverNote: Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace.Figure 2.1. Recommended Input Clock Termination2.2 Input MuxThe Si53360-61/62 provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The following table summarizes the input and output clock based on the input mux settings.Table 2.2. Input Mux Logic2.3 Output Clock Termination OptionsThe recommended output clock termination options are shown below. Unused outputs should be left unconnected.CMOSNote:Rs = 33 ohm for 3.3 V and 2.5 V operation.Rs = 0 ohm for 1.8 V operation.Figure 2.2. LVCMOS Output Termination2.4 AC Timing WaveformsQ N Q MT SKT SKT PLHT RT FQQCLK QT PHLOutput-Output SkewPropagation DelayRise/Fall TimeVPP/2VPP/280% VPP 20% VPPFigure 2.3. AC Timing Waveforms2.5 Power Supply Noise RejectionThe device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world envi-ronments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements.See “AN491: Power Supply Rejection for Low-Jitter Clocks ” for more information.2.6 Typical Phase Noise Performance: Single-Ended Input ClockEach of the phase noise plots superimposes Source Jitter and Total Jitter on the same diagram.•Source Jitter - Reference clock phase noise (measured Single-ended to PNA).•Total Jitter - Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. For more information, see 3. Electrical Specifications.Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).measured hereFigure 2.4. Single-ended Measurement Method The following figure shows three phase noise plots superimposed on the same diagram.Figure 2.5. Total Jitter Single-Ended Input (156.25 MHz)2.7 Input Mux Noise IsolationThe input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation.Figure 2.6. Input Mux Noise Isolation (Single-ended Input Clock, 16QFN Package)3. Electrical SpecificationsTable 3.1. Recommended Operating ConditionsTable 3.2. Input Clock SpecificationsV DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.3. DC Common Characteristics (CLK_SEL, OEx) V DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.4. Output Characteristics (LVCMOS) V DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.5. AC CharacteristicsV DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.6. Additive JitterTable 3.7. Thermal ConditionsTable 3.8. Absolute Maximum Ratings4. Detailed Block DiagramsCLK0CLK1 CLK_SELQ0Q1Q2Q3Q4Q5Q6Q7Si53361 - 16-QFN 3x3 mmVDDO (Si53361 only)Figure 4.1. Si53360 and Si53361 Block DiagramQ7Q6Q8OEBVDDOBQ10Q9Q11Q1Q0Q2OEA VDDOA Q4Q3Q5CLK0CLK1CLK_SELFigure 4.2. Si53362 Block DiagramCLKFigure 4.3. Si53365 Block Diagram5. Si5336x Pin Descriptions5.1 Si53360 Pin DescriptionsCLK0CLK1Q2Q1GND Q6Q5Q3VDD Q0VDD Q7GND OE Q4CLK_SELFigure 5.1. Si53360 Pin Descriptions Table 5.1. Si53360 16-TSSOP Pin Descriptions5.2 Si53361 Pin DescriptionsO EC L K 1Q0Q1Q 2Q 3Q 4Q 5Q6C L K _S E LQ7VDDGND VDDO C L K 0GNDFigure 5.2. Si53361 Pin Descriptions Table 5.2. Si53361 16-QFN Pin Descriptions5.3 Si53362 Pin DescriptionsVDDN CN CN C CLK_SELQ2Q3V D D O A Q 4Q 5Q 6Q 7V D D O BQ11Q8N CQ9Q1OEA C L K 1OEB Q0C L K 0Q10Figure 5.3. Si53362 Pin Descriptions Table 5.3. Si53362 24-QFN Pin Descriptions5.4 Si53365 Pin DescriptionsQ6Q7VDD GND VDD Q2GND Q4OE Q0Q3VDD GND CLK Q5Q1Figure 5.4. Si53365 Pin Descriptions Table 5.4. Si53365 16-TSSOP Pin DescriptionsSi53360/61/62/65 Data Sheet • Si5336x Pin Descriptions6. Package Outline6.1 16-Pin TSSOP PackageFigure 6.1. 16-Pin TSSOP PackageTable 6.1. 16-Pin TSSOP Package DimensionsTable 6.2. 16-QFN Package DimensionsTable 6.3. 24-QFN Package Dimensions7. PCB Land Pattern7.1 16-Pin TSSOP Land PatternFigure 7.1. 16-Pin TSSOP Land PatternTable 7.1. 16-Pin TSSOP Land Pattern Dimensions7.2 16-Pin QFN Land PatternFigure 7.2. 16-Pin QFN Land PatternTable 7.2. 16-QFN Land Pattern Dimensions7.3 24-Pin QFN Land PatternFigure 7.3. 24-Pin QFN Land PatternTable 7.3. 24-QFN Land Pattern Dimensions8. Top Markings8.1 Si53360/65 Top MarkingsFigure 8.1. Si53360 Top Marking Figure 8.2. Si53365 Top MarkingTable 8.1. Si53360/65 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm)Right-JustifiedLine 1 Marking:Device Part Number53360 for Si53360, 53365 for Si53365Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking YY = Year, WW = WorkCorresponds to the year and work week of the mold date.WeekFigure 8.3. Si53361 Top MarkingTable 8.2. Si53361 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm) Cen-ter-alignedLine 1 Marking:Device Part Number3361 for Si53361Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.Line 3 Marking YY = Year, WW = WorkWeek Corresponds to the year and work week of the mold date.Figure 8.4. Si53362 Top MarkingTable 8.3. Si53362 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm)Right-justifiedLine 1 Marking:Device Part Number53362 for Si53362Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.Line 3 Marking YY = Year, WW = WorkWeek Corresponds to the year and work week of the mold date.9. Revision HistoryRevision 1.3December, 2018•Changed CLK_SEL from pull-down resistor to pull-up resistor.•Updated output state to low when OE pin is asserted low on Si53365.Revision 1.2December, 2016•Introduced Si53361 and Si53362 new products.•Merged Si53360/65 datasheets with the new products to create a single LVCMOS buffer datasheet.•Added Core supply current spec at multiple supply voltages.•Added “Internal pull-down resistor” typical spec.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne ®, SkyBlue™, Skyworks Green™, Clockbuilder ®, DSPLL ®, ISOmodem ®, ProSLIC ®, and SiPHY ® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.Portfolio/ia/timing SW/HW /CBPro Quality /quality Support & Resources /support ClockBuilder ProCustomize Skyworks clock generators,jitter attenuators and networksynchronizers with a single tool. WithCBPro you can control evaluationboards, access documentation, requesta custom part number, export for in-system programming and more!/CBPro。

LVDS信号的工作原理和特点LVDS（Low Voltage Differential Signaling）是一种低电压差分信号传输技术，它通过在发送端将信号分成两路相反的电平来传输数据，接收端通过比较这两路信号的差值来恢复原始数据。

LVDS信号具有较高的抗干扰能力和传输速率，被广泛应用于各种数字信号传输领域。

一、LVDS信号的工作原理1. 发送端工作原理：LVDS发送端将输入的数字信号经过编码和差分放大处理，生成两路相反的电平信号。

这两路信号的差值表示了原始数据的逻辑状态，例如低电平差值表示“0”，高电平差值表示“1”。

发送端还会根据协议要求添加时钟信号，以确保接收端能够正确解析数据。

2. 接收端工作原理：LVDS接收端通过比较两路相反的电平信号的差值来恢复原始数据。

如果差值大于一个阈值，则被判定为“1”，如果差值小于阈值，则被判定为“0”。

接收端还会根据时钟信号对数据进行同步处理，以确保数据的准确传输和解析。

二、LVDS信号的特点1. 低电压差分传输：LVDS信号采用低电平差分传输技术，相较于单端传输，具有更好的抗干扰能力和传输稳定性。

差分信号的传输方式能够减少电磁辐射和噪声干扰，提高信号传输的可靠性和抗干扰能力。

2. 高传输速率：LVDS信号传输速率高，可以达到几百兆比特每秒（Gbps）甚至更高。

这使得LVDS广泛应用于高速数据传输领域，如显示器接口、视频传输、高速通信等。

3. 低功耗：LVDS信号传输时采用较低的电压和电流，因此具有较低的功耗。

这对于需要长距离传输或者挪移设备来说非常重要，可以延长电池寿命并提高系统效率。

4. 高抗干扰能力：由于采用了差分传输和编码技术，LVDS信号具有较强的抗干扰能力。

它能够有效抵御来自外部电磁场、噪声和干扰源的影响，确保信号传输的稳定性和可靠性。

5. 长距离传输：LVDS信号可以在较长的距离范围内传输，通常可以达到几十米甚至更远的距离。

这使得LVDS在需要远距离传输的应用中具有优势，如医疗设备、工业自动化等领域。

时钟缓冲器重要参数时钟缓冲器是现代电子设备中非常重要的组成部分，它起到了信号传输和数据处理的关键作用。

时钟缓冲器的性能参数直接影响着整个系统的稳定性和可靠性。

本文将重点介绍时钟缓冲器的几个重要参数，并对其进行详细解析。

一、时钟缓冲器的输入电平电压范围时钟缓冲器的输入电平电压范围是指能够被时钟缓冲器正确识别和处理的输入信号的电压范围。

当输入信号的电压超出这个范围时，时钟缓冲器可能无法正常工作，导致系统故障。

因此，合理选择时钟缓冲器的输入电平电压范围非常重要。

二、时钟缓冲器的输入频率范围时钟缓冲器的输入频率范围是指能够被时钟缓冲器正确接收和处理的输入信号的频率范围。

输入信号的频率超出这个范围时，时钟缓冲器可能无法正确识别输入信号，导致系统时序出错。

因此，合理选择时钟缓冲器的输入频率范围对于系统的正常工作至关重要。

三、时钟缓冲器的输出电平电压范围时钟缓冲器的输出电平电压范围是指时钟缓冲器输出信号的电压范围。

输出电平电压范围过大或过小都可能导致系统工作异常或损坏。

因此，合理选择时钟缓冲器的输出电平电压范围对于保证系统的稳定性和可靠性非常重要。

四、时钟缓冲器的输出频率范围时钟缓冲器的输出频率范围是指时钟缓冲器能够提供的输出信号的频率范围。

输出频率范围不仅与时钟缓冲器本身的性能有关，还与外部电路的需求密切相关。

合理选择时钟缓冲器的输出频率范围可以确保系统工作的稳定性和可靠性。

五、时钟缓冲器的功耗时钟缓冲器的功耗是指时钟缓冲器在工作过程中消耗的电能。

功耗的大小直接影响着系统的能耗和发热量，对于一些功耗敏感的应用场景尤为重要。

因此，在选择时钟缓冲器时需要综合考虑功耗指标，以满足系统对能量消耗的要求。

六、时钟缓冲器的延迟时钟缓冲器的延迟是指时钟信号从输入到输出所经过的时间。

延迟的大小直接影响着系统的时序性能和数据传输的准确性。

合理选择时钟缓冲器的延迟指标，可以确保系统的时序要求得到满足。

七、时钟缓冲器的抖动时钟缓冲器的抖动是指时钟信号的频率或相位发生变化的波动现象。

1FeaturesInputs/Outputs •Accepts differential or single-ended input •LVPECL, LVDS, CML, HCSL, LVCMOS •On-chip input termination and biasing for AC coupled inputs•Six precision LVDS outputs •Operating frequency up to 750 MHzPower •Option for 2.5 V or 3.3 V power supply •Current consumption of 97 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejectionPerformance •Ultra low additive jitter of 135 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40217Precision 1:6 LVDS Fanout Buffer with On-Chip Input TerminationData SheetOrdering InformationZL40217LDG1 32 Pin QFN TraysZL40217LDF132 Pin QFNTape and ReelMatte TinPackage size: 5 x 5 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197.0 Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4 - Clock Input - LVPECL - DC Coupled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5 - Clock Input - LVPECL - AC Coupled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 18 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 19 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Change SummaryBelow are the changes from the February 2013 issue to the April 2014 issue:Page Item Change1Applications Added PCI Express clock distribution.6Pin Description Added exposed pad to Pin Description.7Figure 4 and Figure 5Removed 22 ohm series resistors from Figure 4 and 5. Theseresistor are not required; however there is no impact toperformance if the resistors are included.15Power supply filtering Corrected typo of 0.3 ohm to 0.15 ohm.17Figure 19Clarification of V ID and V ODBelow are the changes from the November 2012 issue to the February 2013 issue:Page Item Change7Figure 4Changed text to indicate the circuit is not recommended forVDD_driver=2.5V.11Figure 12Changed gate values to +/+ on the left and -/- on the right.1.0 Package DescriptionThe device is packaged in a 32 pin QFNFigure 2 - Pin Connections2.0Pin # Name Description3, 6clk_p, clk_n,Differential Input (Analog Input). Differential (or single ended) input signals.For all input configurations see “Clock Inputs” on page 628, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13out0_p, out0_nout1_p, out1_nout2_p, out2_nout3_p, out3_nout4_p, out4_nout5_p, out5_nDifferential Output (Analog Output). Differential outputs.9, 19,22, 32vdd Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal.1, 8vdd_core Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal.2, 7,20, 21gnd Ground. 0 V.4vt On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohmtermination resistors.The use of this pin is detailed in section 3.1, “Clock Inputs“, for various input signal types.5ctrl Digital Control for On-Chip Input Termination (Input). Selects differential input mode;0: DC coupled LVPECL or LVDS modes1: AC coupled differential modesThis pin are internally pulled down to GND. The use of this pin is detailed in section 3.1,“Clock Inputs“, for various input signal types.10, 11,12, 29,30, 31NC No Connection. Leave unconnected.Exposed Pad Device GND.Pin Description3.0 Functional Descriptionhe ZL40217 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to 750MHz.The ZL40217 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40217 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available.The ZL40217 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock InputsThe device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate. A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in Figure 3.Receiverclk_n 50clk_pVt 50BiasctrlFigure 3 - Simplified Diagram of Input StageThis following figures give the components values and configuration for the various circuits compatible with the input stage and the use of the Vt and ctrl pins in each case.In the following diagrams where the ctrl pin is "1" and the Vt pin is not connected, the Vt pin can be instead connected to V DD with a capacitor. A capacitor can also help in Figure 4 between Vt and V DD . This capacitor will minimize the noise at the point between the two internal termination resistors and improve the overall performance of the device.Clock Input - LVPECL - DC CoupledFigure 4 -Figure 6 - Clock Input - LVDS - DC CoupledFigure 7 - Clock Input - LVDS - AC CoupledFigure 8 - Clock Input - CML- AC CoupledFigure 9 - Clock Input - HCSL- AC CoupledFigure 10 - Clock Input - AC-coupled Single-EndedFigure 11 - Clock Input - DC-coupled 3.3V CMOS3.2 Clock OutputsLVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 12.Figure 12 - Simplified LVDS Output DriverFigure 15 - LVDS AC Coupled TerminationFigure 16 - LVDS AC Output Termination for CML Inputs3.3 Device Additive JitterThe ZL40217 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40217 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40217 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.Figure 17 - Additive Jitter3.4 Power SupplyThis device operates employing either a 2.5V supply or 3.3V supply.3.4.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40217 is equipped with a low drop out (LDO) linear power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.3.4.2 Power supply filteringJitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure •. •10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating •0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating •Capacitors should be placed next to the connected device power pins •A 0.15 ohm resistor is recommendedZL402171891922320.1 µF 0.1 µFvdd_core10 µF 0.1 µF0.15 Ωvdd0.1 µF 10 µFFigure 18 - Decoupling Connections for Power Pins3.4.3 PCB layout considerationsThe power nets in Figure 18 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.4.0 AC and DC Electrical CharacteristicsAbsolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3Soldering temperature T260 °C 4Storage temperature T ST-55125 °C 5Junction temperature T j125 °C 6Voltage on input pin V input V DD V 7Input capacitance each pin C p500fF * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V3Operating temperature T A-402585°C* Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVDS drivers -I dd_load97mAloaded (all outputs are active)DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes 1CMOS control logic high-level input V CIH0.7*V DD V2CMOS control logic low-level input V CIL0.3*V DD VI IL1µA V I = V DD or 0 V3CMOS control logic Input leakagecurrentV ICM 1.1 1.6V for 2.5 V 4Differential input common modevoltageV ICM 1.1 2.0V for 3.3 V 5Differential input common modevoltage6Differential input voltage difference V ID0.251V7Differential input resistance V IR80100120ohm* The VOD parameter was measured between 125 and 750 MHzFigure 19 - Differential Voltage ParameterAC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V Supply.CharacteristicsSym.Min.Typ.Max.Units Notes1Maximum Operating Frequency 1/t p 750MHz 2Input to output clock propagation delay t pd 012ns 3Output to output skew t out2out 80150ps 4Part to part output skewt part2part 120300ps 5Output clock Duty Cycle degradation t PWH / t PWL-505%6LVDS Output slew rater SL0.55V/ns* Supply voltage and operating temperature are as per Recommended Operating ConditionsInputt Pt PWLt pdt PWHOutputFigure 20 - Input To Output Timing8LVDS output differential voltage*V OD 0.250.300.40V 9LVDS Common Mode voltageV CM1.11.251.375VDC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V SupplyCharacteristicsSym.Min.Typ.Max.Units Notes5.0 Performance Characterization Additive Jitter at 2.5 V*Output Frequency (MHz)JitterMeasurementFilterTypicalRMS (fs)Notes112512 kHz - 20 MHz184 2212.512 kHz - 20 MHz174 3311.0412 kHz - 20 MHz157 442512 kHz - 20 MHz152 550012 kHz - 20 MHz139 6622.0812 kHz - 20 MHz138 775012 kHz - 20 MHz135 *The values in this table were taken with an approximate slew rate of 0.8 V/ns.Additive Jitter at 3.3 V*Output Frequency (MHz)JitterMeasurementFilterTypicalRMS (fs)Notes112512 kHz - 20 MHz1872212.512 kHz - 20 MHz1763311.0412 kHz - 20 MHz156442512 kHz - 20 MHz153550012 kHz - 20 MHz1406622.0812 kHz - 20 MHz139775012 kHz - 20 MHz137*The values in this table were taken with an approximate slew rate of 0.8 V/ns.Additive Jitter from a Power Supply Tone*CarrierfrequencyParameter Typical Units Notes125MHz25 mVat 100 kHz33fs RMS750MHz25 mVat 100 kHz33fs RMS* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.6.0 Typical BehaviorTypical Waveform at 155.52 MHz V OD vs FrequencyPower Supply Tone Frequency versus PSRR Power Supply Tone Magnitude versus PSRRPropagation Delay versus TemperatureNote:This is for a single device. For more details, see thecharacterization section.7.0 Package CharacteristicsThermal DataParameter Symbol Test Condition Value UnitJunction to Ambient Thermal Resistance ΘJA Still Air1 m/s2 m/s 37.433.131.5o C/WJunction to Case Thermal Resistance ΘJC24.4o C/W Junction to Board Thermal Resistance ΘJB19.5o C/W Maximum Junction Temperature*T jmax125o C Maximum Ambient Temperature T A85o C8.0 Mechanical DrawingInformation relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any suchinformation, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi.This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. 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介绍及时钟和数据分配的应用M-LVDS AN-1926美国国家半导体公司M-LVDS介绍及时钟和数据应用注释1926Davor Glistic分配的应用2008年12月4日自从2002 年早期公布TIA/EIA-899 (多点低压差分信号换时间,扩展输入共模电压范围和故障保护?所有这些对于或者M-LVDS )标准以来,这个标准已成为多点时钟分配和可靠的多点网络是必须的。

数据总线上传输二进制数据交换的通用电气标准。

在保持这个应用笔记概述了M-LVDS 标准,介绍了国家半导体LVDS 电路很多优点(高速,低功耗,良好的噪声抑制)的基目前M-LVDS 的产品系统,描述了M-LVDS 的一般应用,并详础上,M-LVDS 电路新增了一些特性---- 更强驱动,受控的转述了重要的设计指导。

M-LVDS 标准概述章节总结了M-LVDS 驱动器和接收器的关键特性,并将此与M-LVDS 标准规定了线路驱动器和接收器的电气特性。

其他两个通用差分标准RS-485 (TIA/EIA-485-A )和LVDS这些线路驱动器和接收器用于多达32 个节点的多点总线(TIA/EIA-644-A)的驱动器和接收器的特性做了比较。

( 图1 )内的通用数据传输。

更加具体的,此标准定义了驱动器的输出特性,以及两种接收器类型的输入特性。

如下两30086501图1 多点网络驱动器特性根据TIA/EIA-899 标准,一个M-LVDS 驱动器产生一个幅 500Mbps 最大信号速率,而目前商用M-LVDS 驱动器最大速值在480-650mV ,偏置电压范围在0.3V~2.1V 的差分信号。

率在250Mbps 。

另一方面,最大的RS-485 驱动器典型峰值为信号必须有超过1ns 的10%~90% 转换时间(上升和下降), 10Mbps ,很少芯片可以达到30Mbps 至50Mbps 的速率。

高和高达一半的单位间隔(t )。

速,低功耗,和低EMI 的优点是以降低噪声容限为代价的。

LVDSJawen_tao2011-05-09目录一、简介 (2)1、为何要用LVDS? (2)2、LVDS信号传输组成 (2)二、LVDS电气特性 (4)三、传输协议 (5)四、线路接法 (10)五、Layout (13)一、简介LVDS（Low Voltage Differential Signal）即低电压差分信号。

1、为何要用LVDS?LVDS接口又称RS644总线接口，1994年由美国国家半导体公司（NS）提出的为克服以TTL电平方式传输宽带高码率数据时功耗大、EMI电磁干扰大等缺点而研制的一种视频信号传输模式，是一种电平标准，广泛应用于液晶屏接口。

液晶显示器驱动板输出的数字信号是TTL信号，除了包括RGB数据信号外，还包括行同步、场同步、像素时钟等信号，像素时钟信号的最高频率可超过28MHZ.采用TTL接口，数据传输速率不高(一个CLK周期只能传输1bit数据)，传输距离较短，且抗电磁干扰能力比较差，会对RGB数据造成一定的影响。

另外，TTL 多路数据信号采用并行的传输方式，整个并口数量达几十路（RGB各8位，8x3=24，加 DE,HSYNC,VSYNC,至少27位），不但连接不便，而且不适合超薄化的趋势。

采用LVDS输出接口传输数据，可以使这些问题迎刃而解，实现数据的高速率、低噪声、远距离、高准确度的传输。

2、LVDS信号传输组成最基本的LVDS器件就是LVDS驱动器和接收器。

LVDS的驱动器由驱动差分线对的电流源组成，电流通常为3.5 mA。

如下图，LVDS接收器具有很高的输入阻抗，因此驱动器输出的大部分电流都流过100 Ω的匹配电阻（R=100Ω），并在接收器的输入端产生大约350 mV的电压。

（电流源为恒流特性，终端电阻在100—120 欧姆之间，则电压摆动幅度为：3.5mA x 100=350Mv；3.5mA x 120=420mV。

）当驱动器（LVDS发送）翻转时，它改变流经电阻的电流方向，因此产生有效的逻辑“1”和逻辑“0”状态。

1 LvdsLow-V oltage Differential Signaling 低压差分信号。

1994年由美国国家半导体公司提出的一种信号传输模式，它是一种标准它在提供高数据传输率的同时会有很低的功耗，另外它还有许多其他的优势：1、低电压电源的兼容性2、低噪声3、高噪声抑制能力4、可靠的信号传输5、能够集成到系统级IC内使用L VDS技术的的产品数据速率可以从几百Mbps到2Gbps。

它是电流驱动的，通过在接收端放置一个负载而得到电压，当电流正向流动，接收端输出为1，反之为0他的摆幅为250mv-450mvL VDS即低压差分信号传输，是一种满足当今高性能数据传输应用的新型技术。

由于其可使系统供电电压低至2V，因此它还能满足未来应用的需要。

此技术基于ANSI/TIA/EIA-644L VDS接口标准。

LVDS技术拥有330mV的低压差分信号(250mVMINand450mVMAX)和快速过渡时间。

这可以让产品达到自100Mbps至超过1Gbps的高数据速率。

此外，这种低压摆幅可以降低功耗消散，同时具备差分传输的优点。

L VDS技术用于简单的线路驱动器和接收器物理层器件以及比较复杂的接口通信芯片组。

通道链路芯片组多路复用和解多路复用慢速TTL信号线路以提供窄式高速低功耗LVDS接口。

这些芯片组可以大幅节省系统的电缆和连接器成本，并且可以减少连接器所占面积所需的物理空间。

L VDS解决方案为设计人员解决高速I/O接口问题提供了新选择。

L VDS为当今和未来的高带宽数据传输应用提供毫瓦每千兆位的方案。

更先进的总线LVDS(BL VDS)是在LVDS基础上面发展起来的，总线LVDS(BLVDS)是基于L VDS技术的总线接口电路的一个新系列，专门用于实现多点电缆或背板应用。

它不同于标准的LVDS，提供增强的驱动电流，以处理多点应用中所需的双重传输。

BLVDS具备大约250mV的低压差分信号以及快速的过渡时间。

1FeaturesInputs/Outputs •Accepts differential or single-ended input •LVPECL, LVDS, CML, HCSL, LVCMOS •Eight precision LVDS outputs •Operating frequency up to 750 MHzPower •Option for 2.5 V or 3.3 V power supply •Current consumption of 106 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejectionPerformance •Ultra low additive jitter of 104 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40218Precision 1:8 LVDS Fanout BufferData SheetOrdering InformationZL40218LDG1 32 Pin QFN TraysZL40218LDF132 Pin QFNTape and ReelMatte TinPackage Size: 5 x 5 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207.0 Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - LVPECL Input DC Coupled Parallel Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10 - CMOS Input DC Coupled Referenced to VDD/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 18 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 19 - Differential Voltage Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Change SummaryBelow are the changes from the February 2013 issue to the April 2014 issue:Page Item Change1Applications Added PCI Express clock distribution.6Pin Description Added exposed pad to Pin Description.7, 8Figure 3 and Figure 4Removed 22 Ohm series resistors from Figure 3 and 4. Theseresistors are not required; however there is no impact toperformance if the resistors are included.16Power supply filtering Corrected typo of 0.3 ohm to 0.15 ohm.18Figure 19Clarification of V ID and V OD.Below are the changes from the November 2012 issue to the February 2013 issue:Page Item Change8Figure 4Changed text to indicate the circuit is not recommended forVDD_driver=2.5V.8Figure 5Changed pull-up and pull-down resistors from 2kOhm to100 Ohm.12Figure 12Changed gate values to +/+ on the left and -/- on the right.1.0 Package DescriptionThe device is packaged in a 32 pin QFNFigure 2 - Pin Connections2.0 Pin DescriptionPin # Name Description3, 6clk_p, clk_n,Differential Input (Analog Input). Differential (or single ended) input signals.For all input configurations see section 3.1, “Clock Inputs“.30, 29, 28, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13, 12, 11 out0_p, out0_nout1_p, out1_nout2_p, out2_nout3_p, out3_nout4_p, out4_nout5_p, out5_nout6_p, out6_nout7_p, out7_nDifferential Output (Analog Output). Differential outputs.9, 19,22, 32vdd Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal. 1, 8vdd_core Positive Supply Voltage. 2.5 V DC or 3.3 V DC nominal. 2, 7,20, 21gnd Ground. 0 V.4, 510, 31NC No Connection. Leave unconnected.Exposed Pad Device GND.3.0 Functional DescriptionThe ZL40218 is an LVDS clock fanout buffer with eight identical output clock drivers capable of operating at frequencies up to 750MHz.Inputs to the ZL40218 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40218 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.The ZL40218 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock InputsThe ZL40218 is adaptable to support different types of differential and singled-ened input signals depending on the passive components used in the input termination. The application diagrams in the following figures allow the ZL40218 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.Figure 3 - LVPECL Input DC Coupled Thevenin EquivalentFigure 4 - LVPECL Input DC Coupled Parallel TerminationFigure 5 - LVPECL Input AC Coupled TerminationFigure 6 - LVDS Input DC CoupledFigure 7 - LVDS Input AC CoupledFigure 8 - CML Input AC CoupledFigure 9 - HCSL Input AC CoupledFigure 10 - CMOS Input DC Coupled Referenced to VDD/2Figure 11 - CMOS Input DC Coupled Referenced to GroundVDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ) C (pF) 1.5 1.25 3.075open10101.81 3.8open10102.50.33 4.2open10103.30.75open4.21010Table 1 - Component Values for Single Ended Input Reference to Ground*For frequencies below 100 MHz, increase C to avoid signal integrity issues.3.2 Clock OutputsLVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 12.Figure 12 - Simplified LVDS Output DriverThe methods to terminate the ZL40218 drivers are shown in the following figures.Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination)Figure 15 - LVDS AC Coupled TerminationFigure 16 - LVDS AC Output Termination for CML Inputs3.3 Device Additive JitterThe ZL40218 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40218 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40218 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.Figure 17 - Additive Jitter3.4 Power SupplyThis device operates employing either a 2.5V supply or 3.3V supply.3.4.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40218 is equipped with an on-chip linear power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise.The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.3.4.2 Power supply filteringJitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure . •10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating •0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating •Capacitors should be placed next to the connected device power pins •A 0.15 O hm resistor is recommendedZL402181891922320.1 µF 0.1 µFvdd_core10 µF 0.1 µF0.15 Ωvdd0.1 µF 10 µFFigure 18 - Decoupling Connections for Power Pins3.4.3 PCB layout considerationsThe power nets in Figure can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.4.0 AC and DC Electrical CharacteristicsAbsolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3Soldering temperature T260 °C 4Storage temperature T ST-55125 °C 5Junction temperature T j125 °C 6Voltage on input pin V input V DD V 7Input capacitance each pin C p500fF *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.*Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units 1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V 2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V 3Operating temperature T A-402585°C*Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVDS drivers - loadedI dd_load106mA(all outputs are active)DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes 1Differential input common modeV ICM 1.1 1.6V for 2.5 V voltageV ICM 1.1 2.0V for 3.3 V 2Differential input common modevoltage3Differential input voltage difference V ID0.251V4Differential input resistance V IR80100120ohm5LVDS output differential voltage*V OD0.250.300.40V6LVDS Common Mode voltage V CM 1.1 1.25 1.375V*The VOD parameter was measured between 125 and 750 MHzAC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply.Characteristics Sym.Min.Typ.Max.Units Notes 1Maximum Operating Frequency1/t p750MHz2Input to output clock propagation delay t pd012ns3Output to output skew t out2out80150ps4Part to part output skew t part2part120300ps5Output clock Duty Cycle degradation t PWH/ t PWL-505Percent6LVDS Output slew rate r SL0.55V/nsFigure 19 - Differential Voltage Parameter* Supply voltage and operating temperature are as per Recommended Operating ConditionsInputt Pt PWL t pdt PWHOutputFigure 20 - Input To Output TimingAdditive Jitter at 2.5 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1482212.512 kHz - 20 MHz 1383311.0412 kHz - 20 MHz 121442512 kHz - 20 MHz 115550012 kHz - 20 MHz 1076622.0812 kHz - 20 MHz 107775012 kHz - 20 MHz105Additive Jitter at 3.3 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1502212.512 kHz - 20 MHz 1383311.0412 kHz - 20 MHz 120442512 kHz - 20 MHz 115550012 kHz - 20 MHz 1076622.0812 kHz - 20 MHz 106775012 kHz - 20 MHz1045.0 Performance Characterization*The values in this table were taken with a slew rate of approximately 0.8 V/ns.*The values in this table were taken with a slew rate of approximately 0.8 V/ns.Additive Jitter from a Power Supply Tone*Carrier frequencyParameterTypicalUnitsNotes125MHz 25 mV at 100 kHz 24fs RMS 750MHz25 mV at 100 kHz23fs RMS* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.6.0 Typical BehaviorTypical Waveform at 155.52 MHzV OD vs FrequencyPower Supply Tone Frequency versus PSRRPower Supply Tone Magnitude versus PSRRPropagation Delay versus TemperatureNote:This is for a single device. For more details, see thecharacterization section.7.0 Package CharacteristicsThermal DataParameter Symbol Test Condition Value UnitJunction to Ambient Thermal Resistance ΘJA Still Air1 m/s2 m/s 37.433.131.5o C/WJunction to Case Thermal Resistance ΘJC24.4o C/W Junction to Board Thermal Resistance ΘJB19.5o C/W Maximum Junction Temperature*T jmax125o C Maximum Ambient Temperature T A85o C© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. 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ADI发布新款时钟缓冲器和分频器IC AD9508Analog Devices，Inc. ，全球领先的高性能信号处理解决方案供应商，最近发布了一款时钟缓冲器和分频器ICAD9508，该电路结合了高速、极低抖动及可选分频功能。

该1.65 GHz 时钟缓冲器设计用于要求具有最佳SNR性能的超高速数据转换的通信、仪器仪表、防务和航空航天设备。

该器件包括四个带总线可编程分频和相位延迟的专用输出分频器及自动同步功能。

分频器还具有在系统上电时进行硬连线编程的引脚绑定功能。

AD9508最高支持四个差分输出、或八个单端输出以及三种逻辑电平：LVDS 、HSTL 及CMOS 。

AD9508 1.65 GHz时钟缓冲器和分频器主要特性HSTL输出模式下的RMS抖动：41 fs @ 622.08 MHz72 fs @ 622.08 MHZ分频器引脚绑定分频系数为1、2、4、8或16输出：4 LVDS或HSTL；8个单端CMOS输出间偏斜：《48 ps电源电压：2.5 V/3.3 V供货、报价与配套产品产品供货温度范围千片订量报价封装AD9508现在-40摄氏度至85摄氏度$4.25/片24引脚LFCSPAD9508时钟缓冲器/分频器是ADI时钟发生器和高速数据转换器产品组合的补充器件。

关于ADI公司Analog Devices，Inc.将创新、业绩和卓越作为企业的文化支柱，并基此成长为该技术领域最持久高速增长的企业之一。

ADI公司是业界广泛认可的数据转换和信号处理技术全球领先的供应商，拥有遍布世界各地的60，000客户，涵盖了全部类型的电子设备制造商。

作为领先业界40多年的高性能模拟集成电路制造商，ADI的产品广泛用于模拟信号和数字信号处理领域。

公司总部设在美国马萨诸塞州诺伍德市，设计和制造基地遍布全球。

ADI公司被纳入标准普尔500指数。

时钟缓冲器原理时钟缓冲器是一种时钟信号的放大器或再生器。

它在电子系统中广泛应用于各种晶体振荡器，数字电路，以及其他时序电路中。

时钟信号的稳定性和精度对于系统的正常运行非常重要，而时钟缓冲器可以起到保护时钟信号的作用。

本文介绍时钟缓冲器的原理、工作方式及其应用。

一、时钟缓冲器的原理时钟缓冲器相当于一个信号放大器，可以将低电平的时钟信号转化为高电平信号，增强时钟信号的强度和清晰度，同时还可以使时钟信号更加平坦和稳定。

一般情况下，在系统中，时钟信号是从一个时钟源产生的，但在传输过程中可能会出现信号衰减、噪声等问题，使得时钟信号变形、失真。

这种情况会导致系统工作不稳定，甚至引起数据传输错误。

时钟缓冲器就可以解决这些问题，保证系统的可靠性。

时钟缓冲器的工作原理如下：当输入信号在低电平时，时钟缓冲器进行放大，使得输出信号变为高电平。

而输入信号在高电平时，时钟缓冲器不做放大，只起到保持的作用。

这样，在时钟信号的整个周期中，输出的电平都能够保持在高电平的状态。

时钟缓冲器还可以识别信号衰减和噪声，通过内置的反馈机制进行补偿，保证时钟信号的清晰度和稳定性。

二、时钟缓冲器的工作方式时钟缓冲器可以分为两种类型，一种是单端时钟缓冲器，另一种是差分时钟缓冲器。

单端时钟缓冲器：单端时钟缓冲器通常用于低速或中速系统中，有一个输入通道和一个输出通道。

输入是不同的，但输出始终是相同的。

输入信号是经过放大、过滤和稳定化后的，能够有效地保证系统中的可靠性和精度，输出信号的清晰度比输入信号更高。

差分时钟缓冲器：差分时钟缓冲器将输入信号分成两个通道——正向通道和反向通道。

这两个通道的输入信号相反，当正向通道的输入信号上升时，反向通道的输入信号下降，同时输出信号从低电平转换为高电平。

这样，由于输入信号是相反的，输出对象的高电平可以保持更长的时间，系统的稳定性和可靠性更高。

差分时钟缓冲器适用于高速电路，如DDRII、DDR3等。

三、时钟缓冲器的常见应用1.晶体振荡器：晶体振荡器是时钟缓冲器的一种。

后端实现时几种减小时钟延迟的有效方法顾光华;张海平;何志伟【摘要】主要探讨在嵌入式芯片后端设计时怎么实现时钟延时最小时钟网络。

时钟网络优化的障碍可能来自很多方面，主要包括以下三个方面：不同转换率的输入输出单元，具有大负载电容端口以及来自不同时钟域的时钟网络。

针对提出的问题，讨论一般采取的解决方案，优化时钟延时，通过针对性的方法技巧，可以在时钟树自动综合时有效地减少时钟树延时。

%The paper mainly discusses the clock latency is how to achieve the minimum clock network in SOC IC backend design. The clock network optimization barriers may come from many aspects, this paper discussed mainly includes the following three aspects:I/O cells with different conversion rate, high load capacitance pin and from different clock domains of clock network. For those problems, the paperwill discuss solutions generally taken, optimization of clock latency, through targeted skills, can effectively reduce the clock tree latency in clock CTS.【期刊名称】《电子与封装》【年(卷),期】2014(000)003【总页数】4页(P21-24)【关键词】嵌入式芯片;时钟延时;时钟树自动综合【作者】顾光华;张海平;何志伟【作者单位】中国电子科技集团公司第58研究所，江苏无锡214035;中国电子科技集团公司第58研究所，江苏无锡214035;中国电子科技集团公司第58研究所，江苏无锡214035【正文语种】中文【中图分类】TN4021 引言随着现代嵌入式芯片设计的芯片功能及复杂性的不断提高，需要实现更高的时钟频率、更多的时钟域及更复杂的时钟结构。