华中科技大学硕士学位论文高速数据存储系统的设计与应用姓名：黄寅申请学位级别：硕士专业：通信与信息系统指导教师：马洪20090501华中科技大学硕士学位论文摘要在现代雷达、无线电通信、遥测遥感等各个领域，需要处理各种大量、高速、实时性强的数据。
因此，数据采集和存储技术是数字信号处理系统中非常重要的运用，目前以高性能FPGA为控制核心，结合大容量SDRAM存储器的数字系统成为研究的热点。
本文以Xilinx公司的Virtex_4 FPGA为处理平台，1Gbit DDR SDRAM为存储介质，USB控制器实现数据传输，进行高速大容量存储系统的设计，为完成复杂信号处理算法的实现提供了可靠的支持。
在对DDR SDRAM存储结构、控制原理、接口时序进行深入理解的基础上，利用开源化的IP核实现DDR控制器，通过对控制器进行模块划分与仿真验证，确定了控制器逻辑功能的正确性。
在实现DDR控制器的基础上，进一步确立了高速数据存储系统的设计要求与模块组成，提出了基于FIFO 的高速数据缓存方案和利于性能优化的系统测试方案。
通过ISE 10.1开发平台和Verilog HDL设计输入方式，对每个模块进行了详细的逻辑设计和分析说明，并借助ModelSim仿真工具完成了各模块以及整个系统的功能仿真和验证，达到设计要求。
最后利用实际硬件环境对所设计的系统进行测试，通过系统资源分析，系统实时性分析和实际运行结果分析，证明了所设计的高速大容量数据存储系统符合应用需求，可进一步应用于信号处理算法的实现过程中。
论文的最后在基于复杂信号处理算法实现的应用上，对算法中涉及的数据传输和关键的运算处理进行需求分析，提出了对两种存储器资源的分配与调度策略，完成了可行性论证。
关键词：数据存储，FPGA，DDR SDRAM，FIFO，信号处理华中科技大学硕士学位论文AbstractIn the fields of radar, radio communications, remote sensing, etc. It is necessary to process mass, high speed and real-time data. So the technology of data acquisition and data storage is very important in the digital signal processing system. It is popular to use high-performance FPGA (Field Programmable Gate Array) which acts as the control core, and mass storage SDRAM (Synchronous Dynamic Random Access Memory) to design the digital system.This dissertation utilized Xilinx's Virtex_4 FPGA as the platform and 1Gbit DDR(Double Data Rate) SDRAM as the storage medium, through USB controller implementing data transmission to design the high-speed mass data storage system, and the design provide a basis for the implementation of complex signal processing algorithms. After a deeply research on the structure, principle and interface timing of DDR SDRAM, the DDR controller are designed out by means of IP core. What's more, the function of the controller is proved by the simulation. Based on the implementation of DDR controller, the design requirements and modules makeup of the high-speed mass data storage system are made certain, and the dissertation bring out two schemes, one is to storage data using FIFO(First In First Out), the other is to optimize the performance through system test bench. Through the development platform of ISE 10.1 and language using Verilog HDL, the logic design of every module is accomplished, and the performance of the system is simulated and tested by simulation tool software ModelSim. At last, it is proved that the design of high-speed mass data storage system is valid and feasible by the hardware system operation, and it meets the needs of application.At the end of the dissertation, based on implementation of the complex signal processing algorithms, this paper brings forward the strategy about distribution and schedule of the two memories, as well as fulfills the feasibility study.Keywords: Data storage, FPGA, DDR SDRAM, FIFO, Signal processing独创性声明本人声明所呈交的学位论文是我个人在导师指导下进行的研究工作及取得的研究成果。
