MSP学习笔记初识开发板和IDE

STM32F20xxx_21xxx单⽚机硬件开发⼊门笔记AN3320Application noteGetting started with STM32F20xxx/21xxx MCUhardware developmentIntroductionThis application note is intended for system designers who require a hardwareimplementation overview of the development board features such as the power supply, theclock management, the reset control, the boot mode settings and the debug management. It shows how to use the high-density performance line STM32F20xxx/21xxx product familiesand describes the minimum hardware resources required to develop anSTM32F20xxx/21xxx application.Detailed reference design schematics are also contained in this document with descriptionsof the main components, interfaces and modes.August 2011Doc ID 18267 Rev 21/29/doc/20ec15b314791711cd7917a6.htmlContents AN3320Contents1Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.1.1Independent A/D converter supply and reference voltage . . . . . . . . . . . . 71.1.2Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.3Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.2Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3.1Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 91.3.2Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 101.3.3System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.1.1External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.2External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 132.2LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.1External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 142.3Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.1Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.1SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3.2Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3.3Internal pull-up and pull-down resistors on JT AG pins . . . . . . . . . . . . . . 194.3.4SWJ debug port connection with standard JTAG connector . . . . . . . . . 20 2/29 Doc ID 18267 Rev 2AN3320Contents5Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.1Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.2Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.3Ground and power supply (V SS, V DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.4Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215.5Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.6Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.1Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.3Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.4SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.1.5Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.2Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Doc ID 18267 Rev 23/29List of tables AN3320 List of tablesTable 1.Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.SWJ I/O pin availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4.Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5.Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6.Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4/29 Doc ID 18267 Rev 2AN3320List of figures List of figuresFigure 1.Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.Power-on reset/power-down reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5.Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6.HSE external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7.HSE crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8.LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9.LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Boot mode selection implementation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Host-to-board connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13.Typical layout for V DD/V SS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14.STM32F207IG(H6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 25Doc ID 18267 Rev 25/29Power supplies AN33206/29 Doc ID 18267 Rev 21 Power supplies1.1 IntroductionThe device requires a 1.8V to 3.6V operating voltage supply (V DD ), excepted the WLCSPpackage witch requires 1.65V to 3.6V. An embedded regulator is used to supply the internal 1.2V digital power.The real-time clock (RTC) and backup registers can be powered from the V BAT voltage when the main V DD supply is powered off.1.V DDA and V SSA must be connected to V DD and V SS , respectively.2.The voltage on V REF ranges from 1.65V to V DDA for WLCSP64+2 packages.AN3320Power suppliesDoc ID 18267 Rev 27/291.1.1 Independent A/D converter supply and reference voltageTo improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.●the ADC voltage supply input is available on a separate V DDA pin ●an isolated supply ground connection is provided on the V SSA pinWhen available (depending on package), V REF– must be tied to V SSA .On 100-pin package and above and on WLCSP64+2To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on V REF+. The voltage on V REF+ may range from 1.8V to V DDA . On WLCSP64+2, the V REF- pin is not available, it is internally connected to the ADC ground (V SSA ).On 64-pin packagesThe V REF+ and V REF- pins are not available, they are internally connected to the ADC voltage supply (V DDA ) and ground (V SSA ).1.1.2 Battery backupTo retain the content of the Backup registers when V DD is turned off, the V BAT pin can beconnected to an optional standby voltage supplied by a battery or another source.The V BAT pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (V DD ) is turned off. The switch to the V BAT supply is controlled by the power down reset (PDR) circuitry embedded in the Reset block.If no external battery is used in the application, it is highly recommended to connect V BAT externally to V DD .1.1.3 Voltage regulatorThe voltage regulator is always enabled after reset. It works in three different modesdepending on the application modes.●in Run mode, the regulator supplies full power to the 1.2V domain (core, memories and digital peripherals)●in Stop mode, the regulator supplies low power to the 1.2V domain, preserving the contents of the registers and SRAM●in Standby mode, the regulator is powered down. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.Note:Depending on the selected package, there are specific pins that should be connected either to V SS or V DD to activate or deactivate the voltage regulator. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .Power supplies AN33208/29 Doc ID 18267 Rev 21.2 Power supply schemesThe circuit is powered by a stabilized power supply, V DD .●Caution:–The V DD voltage range is 1.8V to 3.6V (and 1.65V to 3.6V for WLCSP64+2 package)●The V DD pins must be connected to V DD with external decoupling capacitors: one single T antalum or Ceramic capacitor (min. 4.7µF typ.10µF) for the package + one 100nF Ceramic capacitor for each V DD pin.●The V BAT pin can be connected to the external battery (1.65V < V BA T < 3.6V). If no external battery is used, it is recommended to connect this pin to V DD with a 100nF external ceramic decoupling capacitor.●The V DDA pin must be connected to two external decoupling capacitors (100nF Ceramic + 1µF Tantalum or Ceramic).●The V REF+ pin can be connected to the V DDA external power supply. If a separate, external reference voltage is applied on V REF+, a 100nF and a 1µF capacitors must be connected on this pin. In all cases, V REF+ must be kept between 1.65V and V DDA .●Additional precautions can be taken to filter analog noise:–V DDA can be connected to V DD through a ferrite bead.–The V REF+ pin can be connected to V DDA through a resistor (typ. 47Ω).●For the voltage regulator configuration, there are specific pins (REGOFF and IRROFF depending on the package) that should be connected either to VSS or VDD to activate or deactivate the voltage regulator specific. Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details .●When the voltage regulator is enabled, V CAP1 and V CAP2 pins must be connected to 2*2.2µF Ceramic capacitor.AN3320Power suppliesDoc ID 18267 Rev 29/291.Optional. If a separate, external reference voltage is connected on V REF+, the two capacitors (100 nF and1µF) must be connected.2.V REF + is either connected to V REF or to V DDA .3.N is the number of V DD and V SS inputs.4.Refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet to connect REGOFF and IRROFFpins.1.3Reset & power supply supervisor1.3.1Power on reset (POR) / power down reset (PDR)The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8V .The device remains in the Reset mode as long as V DD is below a specified threshold, V POR/PDR , without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in STM32F20xxx/21xxx datasheets.On WLCSP66 package if IRROFF pin is set to V DD (in that case REGOFF pin must not be activated, refer to section "Voltage regulator" in STM32F20xxx/21xxx datasheet for details ), the PDR is not functional. Then the V DD can lower below 1.8V , but the external circuitry must ensure that reset pin is activated when V DD /V DDA becomes below 1.65V .Power suppliesAN332010/29 Doc ID 18267 Rev 21.t RSTTEMPO is approximately2.6ms. V POR/PDR rising edge is 1.74V (typ.) and V POR/PDR falling edge is1.70V (typ.). Refer to STM32F20xxx/21xxx datasheets for actual value.1.3.2 Programmable voltage detector (PVD)Y ou can use the PVD to monitor the V DD power supply by comparing it to a thresholdselected by the PLS[2:0] bits in the Power control register (PWR_CR).The PVD is enabled by setting the PVDE bit.A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicatewhether V DD is higher or lower than the PVD threshold. This event is internally connected to EXTI Line16 and can generatean interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V DD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge configuration. As an example the service routine can perform emergency shutdown tasks.AN3320Power suppliesDoc ID 18267 Rev 211/291.3.3 System resetA system reset sets all registers to their reset values except for the reset flags in the clockcontroller CSR register and the registers in the Backup domain (see Figure 1).A system reset is generated when one of the following events occurs:1. A low level on the NRST pin (external reset)2. window watchdog end-of-count condition (WWDG reset)3. Independent watchdog end-of-count condition (IWDG reset)4. A software reset (SW reset)5.Low-power management resetThe reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR.The STM32F20xxx/21xxx does not require an external reset circuit to power-up correctly. Only a pull-down capacitor is recommended to improve EMS performance by protecting the device against parasitic resets. See Figure 5.Charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. The capacitor recommended value (100nF) can be reduced to 10nF to limit this power consumption;Clocks AN332012/29 Doc ID 18267 Rev 22 ClocksThree different clock sources can be used to drive the system clock (SYSCLK):●HSI oscillator clock (high-speed internal clock signal)●HSE oscillator clock (high-speed external clock signal)●PLL clockThe devices have two secondary clock sources:●32kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby modes.●32.768kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.Refer to the STM32F20xxx/21xxx reference manual RM0033 for the description of the clock tree.2.1 HSE OSC clockThe high-speed external clock signal (HSE) can be generated from two possible clock sources:●HSE external crystal/ceramic resonator (see Figure 7)●HSE user external clock (see Figure 6)1.The value of R EXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 R S(resonator series resistance).2.Load capacitance C L has the following formula: C L = C L1 x C L2 / (C L1 + C L2) + C stray where: C stray is the pincapacitance and board or trace PCB-related capacitance. Typically, it is between 2pF and 7pF. Please refer to Section 5: Recommendations on page 21 to minimize its value.Figure 6.HSE external clockFigure 7.HSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 213/292.1.1 External source (HSE bypass)In this mode, an external clock source must be provided. It can have a frequency from 1 to 16MHz (refer toSTM32F20xxx/21xxx datasheets for actual max value).The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see Figure 7 and Figure 6).2.1.2 External crystal/ceramic resonator (HSE crystal)The external oscillator frequency ranges from 4 to 26MHz.The external oscillator has the advantage of producing a very accurate rate on the mainclock. The associated hardware configuration is shown in Figure 7. Using a 25MHz oscillator frequency is a good choice to get accurate Ethernet, USB OTG high-speed peripheral, and I 2S.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.For C L1 and C L2 it is recommended to use high-quality ceramic capacitors in the 5pF-to-25pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. C L1 and C L2, are usually the same value. Thecrystal manufacturer typically specifies a load capacitance that is the series combination of C L1 and C L2. The PCB andMCU pin capacitances must be included when sizing C L1 and C L2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).Refer to the electrical characteristics sections in the datasheet of your product for more details.Clocks AN332014/29 Doc ID 18267 Rev 22.2 LSE OSC clockThe low-speed external clock signal (LSE) can be generated from two possible clocksources:●LSE external crystal/ceramic resonator (see Figure 9)●LSE user external clock (see Figure 8)1.“LSE crystal/ceramic resonators” figure:To avoid exceeding the maximum value of C L1 and C L2 (15pF) it is strongly recommended to use a resonator with a load capacitance C L ≤7pF. Never use a resonator with a load capacitance of 12.5pF.2.“LSE external clock” and “LSEcrystal/ceramic resonators” figures:OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same application.3.“LSE crystal/ceramic resonators” figure:The value of R EXT depends on the crystal characteristics. A 0Ω resistor would work but would not be optimal. To fine tube R S value, refer to AN2867 - Oscillator design guide for ST microcontrollers.2.2.1 External source (LSE bypass)In this mode, an external clock source must be provided. It can have a frequency of up to 1MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 8).2.2.2 External crystal/ceramic resonator (LSE crystal)The LSE crystal is a 32.768kHz low-speed external crystal or ceramic resonator. It has theadvantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) forclock/calendar or other timing functions.The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.Figure 8.LSE external clockFigure 9.LSE crystal/ceramicAN3320ClocksDoc ID 18267 Rev 215/292.3 Clock security system (CSS)The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.●If a failure is detected on the HSE oscillator clock, the oscillator is automaticallydisabled. A clock failure event is sent to the break input of the TIM1 advanced control timer and an interrupt is generated to inform the software about the failure (clocksecurity system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex?-M3 NMI (non-maskable interrupt) exception vector.●If the HSE oscillator is used directly or indirectly as the system clock (indirectly means that it is used as the PLL input clock, and the PLL clock is used as the system clock), a detected failure causes a switch of the system clock to the HSI oscillator and thedisabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.For details, see the STM32F20xxx/21xxx (RM0033) reference manuals available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .Boot configuration AN332016/29 Doc ID 18267 Rev 23 Boot configuration3.1 Boot mode selectionIn the STM32F20xxx/21xxx, three different boot modes can be selected by means of theBOOT[1:0] pins as shown in Table 1.The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.The BOOT pins are also resampled when exiting the Standby mode. Consequently, they must be kept in the required Boot mode configuration in the Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004.3.2 Boot pin connectionFigure 10 shows the external connection required to select the boot memory of the STM32F20xxx/21xxx.1.Resistor values are given only as a typical example.Table 1.Boot modesBOOT mode selection pinsBoot mode AliasingBOOT1BOOT0x 0Main Flash memory Main Flash memory is selected as boot space01System memory System memory is selected as boot space11Embedded SRAMEmbedded SRAM is selected as boot spaceAN3320Boot configuration3.3 Embedded boot loader modeThe Embedded boot loader mode is used to reprogram the Flash memory using one of theavailable serial USART1(PA9/PA10), USART3(PB10/11 & PC10/11), CAN2(PB5/13) or USBOTG FS(PA11/12) in Device mode (DFU: device firmware upgrade).The USART peripheral operates with the internal 16MHz oscillator (HSI). The CAN andUSB OTG FS, however, can only function if an external clock (HSE) multiple of 1 MHz(between 4 and 26 MHz)is present.This embedded boot loader is located in the System memory and is programmed by STduring production.For additional information, refer to AN2606.Doc ID 18267 Rev 217/29Debug management AN332018/29 Doc ID 18267 Rev 24 Debug management4.1 IntroductionThe Host/Target interface is the hardware equipment that connects the host to theapplication board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool.Figure 11 shows the connection of the host to the evaluation board STM3220G-EVAL.Figure 11.Host-to-board connection 4.2 SWJ debug port (serial wire and JTAG)The STM32F20xxx/21xxx core integrates the serial wire / JT AG debug port (SWJ-DP). It is an ARM? standard CoreSight? debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.●The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-AP port●The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP portIn the SWJ-DP , the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP .4.3 Pinout and debug port pinsThe STM32F20xxx/21xxx MCU is offered in various packages with different numbers of available pins. As a result, some functionality related to the pin availability may differ from one package to another.4.3.1 SWJ debug port pinsFive pins are used as outputs for the SWJ-DP as alternate functions of general-purpose I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.%VALUATION BOARD(OST 0#0OWER SUPPLY*4!' 37 CONNECTOR$EBUG TOOLAI BAN3320Debug managementDoc ID 18267 Rev 219/294.3.2 Flexible SWJ-DP pin assignmentAfter reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).However, some of the JTAG pins shown in Table 3 can be configured to an alternate function through the GPIOx_AFRx registers.Table 3 shows the different possibilities to release some pins.For more details, see the STM32F20xxx/21xxx (RM0033) reference manual, available from the STMicroelectronics website /doc/20ec15b314791711cd7917a6.html .4.3.3 Internal pull-up and pull-down resistors on JTAG pinsThe JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops. Table 2.Debug port pin assignmentSWJ-DP pin nameJTAG debug portSW debug portPinassignment TypeDescription Type Debug assignment JTMS/SWDIO I JTAG test mode selection I/O Serial wire data input/output PA13JTCK/SWCLK I JTAG test clock I Serial wire clock P A14JTDII JTAG test data input --P A15JTDO/TRACESWO O JTAG test data output -TRACESWO if async traceis enabled PB3JNTRSTIJTAG test nReset。

stm32cubelde的使用方法stm32cubeide的使用方法STM32CubeIDE是针对STM32微控制器系列开发的一款集成开发环境（IDE）。

它是由STMicroelectronics开发的，并提供给开发者免费下载和使用。

STM32CubeIDE支持多种STM32微控制器系列，提供了强大的开发工具和功能，可以帮助开发者更快速、高效地开发STM32微控制器项目。

本文将介绍STM32CubeIDE的基本使用方法，以便初学者能够快速上手。

第一步：下载和安装STM32CubeIDE首先，我们需要从STMicroelectronics的官方网站上下载STM32CubeIDE的安装包。

在下载之前，我们需要注册一个STMicroelectronics的账号。

注册完成后，登录账号并在网站上找到STM32CubeIDE的下载页面。

点击下载页面上的安装包链接，选择适合您操作系统的版本进行下载。

下载完成后，双击安装包文件并按照安装向导的指示进行安装。

安装完成后，打开STM32CubeIDE。

第二步：创建新项目在STM32CubeIDE的初始界面上，点击"File"菜单，然后选择"New"->"STM32 Project"。

在弹出的对话框中，输入项目的名称和存储路径。

接下来，选择使用的STM32系列和目标芯片型号。

点击"Next"按钮。

在接下来的页面上，选择编程语言，例如C或C++。

还可以选择是否使用HAL 库和其他外设库。

点击"Finish"按钮创建新项目。

第三步：编写代码创建项目后，STM32CubeIDE将在项目文件夹中创建相应的文件。

在项目视图中，可以看到一个名称为"Core"的文件夹，其中包含了一个名为"main.c"的源文件。

这是我们编写主代码的地方。

使用IDE之前需要了解的一些概念使用IDE之前需要了解的一些概念IDE是用于提供程序开发环境的应用程序，一般包括代码编辑器、编译器、调试器和图形用户界面等工具。

集成了代码编写功能、分析功能、编译功能、调试功能等一体化的开发软件服务套。

下面是店铺分享的使用IDE之前需要了解的一些概念，欢迎大家参考!1) 源文件(Source File)在开发软件的过程中，我们需要将编写好的代码(Code)保存到一个文件中，这样代码才不会丢失，才能够被编译器找到，才能最终变成可执行文件。

这种用来保存代码的文件就叫做源文件(Source File)。

每种编程语言的源文件都有特定的后缀，以方便被编译器识别;源文件后缀大都根据编程语言本身的名字来命名，例如C语言源文件的后缀是.c，C++ 源文件的后缀是.cpp，Java 源文件的后缀是.java，Python 源文件的后缀是.py。

源文件其实就是纯文本文件，它的内部并没有特殊格式，能证明这一结论的典型例子是：在Windows 下用记事本程序新建一个文本文档，并命名为demo.txt，输入一段C语言代码并保存，然后将该文件强制重命名为demo.c(后缀从.txt变成了.c)，发现编译器依然能够正确识别其中的C语言代码，并顺利生成可执行文件。

源文件的后缀仅仅是为了表明该文件中保存的是某种语言的代码(例如.c文件中保存的是C语言代码)，这样程序员更加容易区分，编译器也更加容易识别，它并不会导致该文件的内部格式发生改变。

C++ 是在C语言的基础上进行的扩展，C++ 包含了C语言的全部内容(请猛击《C和C++到底有什么关系》一文了解更多)，将C语言代码放在.cpp文件中不会有错，很多初学者都是这么做的，很多大学老师也是这么教的。

但是，我还是强烈建议将C语言代码放在.c文件中，这样能够更加严格地遵循C语言的语法，也能够更加清晰地了解C语言和C++的区别。

2) 工程/项目(Project)一个真正的程序(也可以说软件)往往包含多项功能，每一项功能都需要几十行甚至几千行、几万行的代码来实现，如果我们将这些代码都放到一个源文件中，那将会让人崩溃，不但源文件打开速度极慢，代码的编写和维护也将变得非常困难。

Arduino入门教程引言Arduino作为一种开源电子平台，已经广泛应用于各种领域，无论是学习电子基础知识还是 DIY 制作小玩具，Arduino 都是一个不错的选择。

本文将从硬件选购、开发环境搭建、基础编程语言以及实例应用等方面为读者介绍 Arduino 的入门知识。

一、硬件选购对于初学者来说，选择一款合适的 Arduino 开发板是至关重要的。

在市面上有各式各样的 Arduino 开发板可供选择，如 Arduino Uno、Arduino Nano、Arduino Mega等。

首先要考虑的是项目需求，确定所需的输入输出接口、处理器性能和存储容量等因素，然后再选择合适的开发板。

此外，应该选择正版的 Arduino 开发板，以确保质量和稳定性。

二、开发环境搭建在开始编程之前，需要搭建一个 Arduino 集成开发环境（IDE）。

首先，从Arduino 官网上下载最新版本的Arduino IDE，并根据操作系统进行安装。

搭建好开发环境后，可以将 Arduino开发板连接到电脑上，并选择正确的开发板和端口。

通过该IDE，可以编写、上传和调试 Arduino 的代码。

三、基础编程语言Arduino 的编程语言基于C/C++，但相对于传统的C/C++ 语言，Arduino 提供了更为简洁的函数库和接口，使得编程变得更加容易上手。

以下是一些基本语法和函数的介绍：1. 串口通信Arduino 通过串行通信口（Serial）与电脑进行通信。

通过使用Serial.begin() 函数来初始化串口，Serial.print() 和 Serial.println() 函数可用于向串口输出数据。

2. 控制结构Arduino 支持常见的控制结构，如 if 语句、for 循环和 while 循环等，这些控制结构可以用于条件判断和循环控制。

3. 数组和字符串Arduino 支持数组和字符串操作。

可以通过声明数组变量和使用 strcpy()、strcat() 等字符串函数进行操作。

IDE知识点大全IDE（集成开发环境）是软件开发中常用的工具，为开发者提供了一站式的开发环境，包括代码编辑、编译、调试等多个功能。

本文将介绍IDE的基本概念和常见功能，以及如何选择适合自己的IDE。

1.IDE的概念 IDE是一种软件工具，它集成了多种开发工具和环境，方便开发者进行软件开发。

它通常包括代码编辑器、编译器、调试器、版本控制等功能。

2.常见IDE 目前市面上有许多常见的IDE可供选择，其中一些最受开发者欢迎的包括：–Eclipse：开源的Java IDE，支持多种编程语言，拥有丰富的插件生态系统。

–Visual Studio：微软的集成开发环境，支持多种编程语言，尤其适用于Windows平台开发。

–IntelliJ IDEA：Java开发的IDE，被认为是最好的Java IDE之一，功能强大且易于使用。

–Xcode：苹果公司的开发工具，适用于iOS和Mac应用程序开发。

–Android Studio：谷歌官方推出的Android应用开发工具，集成了Android SDK和各种开发工具。

3.IDE的基本功能 IDE提供了许多基本功能，使得开发变得更加高效和便捷。

–代码编辑器：IDE提供了专门的代码编辑器，支持语法高亮、自动补全、代码重构等功能，提高了编写代码的效率。

–编译器：IDE可以将源代码编译成可执行文件或库文件，让开发者可以直接运行和测试代码。

–调试器：IDE内置了调试器，可以帮助开发者进行代码调试，查找和修复bug。

–版本控制：许多IDE支持版本控制系统（如Git），方便团队协作和代码管理。

–构建工具：IDE通常集成了构建工具（如Maven、Gradle），可以自动化构建和管理项目。

4.如何选择合适的IDE 选择合适的IDE取决于多个因素，包括编程语言、项目需求和个人偏好。

–编程语言：不同的IDE对不同的编程语言支持不同程度，需要选择适合编程语言的IDE。

–项目需求：一些IDE专注于特定类型的项目开发，如移动应用开发、Web开发等，需要根据项目需求选择合适的IDE。

stm32cubeidea使用手册STM32CubeIDE使用手册欢迎使用STM32CubeIDE，这是一款为STM32系列单片机提供开发环境的集成开发工具。

本手册将为您介绍STM32CubeIDE的安装、项目创建、调试以及其他操作的详细步骤和注意事项。

一、安装STM32CubeIDE首先，您需要从STMicroelectronics官方网站上下载STM32CubeIDE的安装程序。

安装程序支持多个操作系统，您可以根据自己的需求选择对应的版本进行下载。

安装程序下载完成后，双击运行并按照提示完成安装。

安装过程中，请确保勾选所需的组件，例如编译器、调试器以及相关的软件包。

二、新建项目1. 打开STM32CubeIDE，点击菜单栏上的“File”选项，然后选择“New”->“STM32 Project”。

2. 在弹出的窗口中，选择合适的板级支持包(BSP)，例如您可以选择Nucleo系列的开发板。

3. 在弹出的项目配置向导中，根据您的需求填写项目名称、选择工程模板、选择适合的MCU型号，然后点击“Finish”按钮。

三、项目配置1. 在项目中选择适当的MCU型号后，您可以进一步配置项目的各项参数，例如时钟设置、外设初始化等。

可以通过鼠标右键单击项目名称，在弹出的菜单中选择“Properties”打开项目属性窗口进行配置。

2. 通过添加文件和库函数，您可以扩展和定制项目的功能。

四、编写代码在STM32CubeIDE中，您可以使用C或者C++语言编写代码。

您可以单击源文件夹，在右键菜单中选择“New”->“Source File”来添加新的源文件。

编写代码时，建议使用相关的代码提示和自动完成功能，这有助于提高开发效率。

五、编译与调试1. 在STM32CubeIDE中，您可以点击工具栏上的“Build”按钮，或者使用快捷键F7来进行编译。

2. 编译完成后，您可以通过菜单栏上的“Debug”选项来进行调试。