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74ABT273CMSA中文资料

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© 1999 Fairchild Semiconductor Corporation DS011549January 1993Revised November 199974ABT273 Octal D-Type Flip-Flop74ABT273Octal D-Type Flip-FlopGeneral DescriptionThe ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi-tion, is transferred to the corresponding flip-flop’s Q output.All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.Featuress Eight edge-triggered D-type flip-flops s Buffered common clocks Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE versions Output sink capability of 64 mA, source capability of 32mA s Guaranteed latchup protections High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capabilitys Disable time less than enable time to avoid bus conten-tionOrdering Code:Device also available in Tape and Reel. Specify by appending suffix letter “X ” to the ordering code.Connection Diagram Pin DescriptionsOrder Number Package NumberPackage Description74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT273CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT273CMSA MSA2020-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide74ABT273CMTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names DescriptionD 0–D 7Data InputsMR Master Reset (Active LOW)CP Clock Pulse Input (Active Rising Edge)Q 0–Q 7Data Outputs 274A B T 273Truth TableH= HIGH Voltage Level steady stateh = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady stateI = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial= LOW-to-HIGH clock transitionLogic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.Operating ModeInputs Output MRCP D n Q n Reset (Clear)L XX L Load “1”H h H Load “0”HlL74ABT273Absolute Maximum Ratings (Note 1)Recommended Operating ConditionsNote 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.Note 2: Either voltage limit or current limit is sufficient to protect inputs.DC Electrical CharacteristicsNote 3: Guaranteed but not tested.Note 4: For 8 bits toggling, I CCD < 0.5 mA/MHz.Storage Temperature−65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2)−0.5V to +7.0V Input Current (Note 2)−30 mA to +5.0 mAVoltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +4.75V in the HIGH State −0.5V to V CC Current Applied to Output in LOW State (Max)twice the rated I OL (mA)DC Latchup Source Current −500 mA(Across Comm Operating Range)Over Voltage LatchupV CC + 4.5VFree Air Ambient Temperature −40°C to +85°C Supply Voltage+4.5V to +5.5VMinimum Input Edge Rate (∆V/∆t)Data Input 50 mV/ns Enable Input20 mV/ns Symbol ParameterMin TypMaxUnits V CCConditionsV IH Input HIGH Voltage 2.0V Recognized HIGH Signal V IL Input LOW Voltage 0.8V Recognized LOW Signal V CD Input Clamp Diode Voltage −1.2V Min I IN = −18 mA V OH Output HIGH Voltage 2.5V Min I OH = −3 mA 2.0I OH = −32 mA V OL Output LOW Voltage 0.55V Min I OL = 64 mA I IH Input HIGH Current 1µA Max V IN = 2.7V (Note 3)1V IN = V CC I BVI Input HIGH Current 7µA Max V IN = 7.0V Breakdown Test I IL Input LOW Current −1µA Max V IN = 0.5V (Note 3)−1V IN = 0.0V V ID Input Leakage Test 4.75V 0.0I ID = 1.9 µAAll Other Pins Grounded I OS Output Short-Circuit Current −100−275mA Max V OUT = 0.0V I CEX Output HIGH Leakage Current 50µA Max V OUT = V CC I CCH Power Supply Current 50µA Max All Outputs HIGH I CCL Power Supply Current 30mA Max All Outputs LOW I CCTMaximum I CC /InputOutputs Enabled1.5mAMax V I = V CC − 2.1VData Input V I = V CC − 2.1V All Others at V CC or GNDI CCDDynamic I CCNo Load0.3mA/MaxOutputs Open (Note 4)MHzOne Bit Toggling, 50% Duty Cycle 474A B T 273AC Electrical Characteristics(SSOIC package)AC Operating RequirementsCapacitance(SOIC package)Note 5: C OUT is measured at frequency f = 1 MHz, per MIL-STD-833, Method 3012.SymbolParameterT A = +25°CT A = −55°C to +125°C T A = −40°C to +85°C UnitsV CC = +5.0V V CC = 4.5V to 5.5VV CC = 4.5V to 5.5VC L = 50 pFC L = 50 pF C L = 50 pF MinTyp MaxMin MaxMin Maxf MAX Maximum Clock Frequency 150200150150 MHz t PLH Propagation Delay 2.0 6.0 1.07.0 2.0 6.0ns t PHL CP to O n2.8 6.8 1.07.5 2.8 6.8t PHLPropagation Delay 2.57.4 1.08.2 2.57.4ns MR to O nSymbolParameterT A = +25°CT A = −55°C to +125°C T A = −40°C to +85°C UnitsV CC = +5.0V V CC = 4.5V to 5.5VV CC = 4.5V to 5.5VC L = 50 pF C L = 50 pF C L = 50 pF MinMaxMin MaxMin Maxt S (H)Setup Time, HIGH 2.0 2.0 2.0ns t S (L)or LOW D n to CP 2.5 2.5 2.5t H (H)Hold Time, HIGH 1.2 1.4 1.2ns t H (L)or LOW D n to CP 1.2 1.4 1.2t W (H)Pulse Width, CP , 3.3 3.3 3.3ns t W (L)HIGH or LOW 3.3 3.3 3.3t W (L)Master Reset Pulse 3.3 3.3 3.3ns Width, LOW t RECRecovery Time 2.02.02.0ns MR to CPSymbol ParameterTyp Units Conditions T A = 25°CC INInput Capacitance 5pF V CC = 0V C OUT (Note 5)Output Capacitance9pFV CC = 5.0V 74ABT273AC Loading*Includes jig and probe capacitanceFIGURE 1. Standard AC Test LoadFIGURE 2. V M= 1.5VInput Pulse RequirementsFIGURE 3. Test Input Signal RequirementsAC WaveformsFIGURE 4. Propagation Delay,Pulse Width WaveformsFIGURE 5. 3-STATE Output HIGHand LOW Enable and Disable TimesFIGURE 6. Propagation Delay Waveforms forInverting and Non-Inverting FunctionsFIGURE 7. Setup Time, Hold Timeand Recovery Time WaveformsAmplitude Rep. Rate t W t r t f3.0V 1 MHz500 ns 2.5 ns 2.5 ns 674A B T 273Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide BodyPackage Number M20B 74ABT273Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 874A B T 273Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm WidePackage Number MSA20974ABT273 Octal D-Type Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

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TC74VHC273FT资料

TC74VHC273FT资料

TOSHIBA CMOS Digital Integrated Circuit Silicon MonolithicTC74VHC273F,TC74VHC273FT,TC74VHC273FKOctal D-Type Flip-Flop with ClearThe TC74VHC273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C 2MOS technology.It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.When the CLR input is held “L”, the Q outputs are at a low logic level independent of the other inputs.An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.Features• High speed: f max = 165 MHz (typ.) at V CC = 5 V • Low power dissipation: I CC = 4 μA (max) at Ta = 25°C • High noise immunity: V NIH = V NIL = 28% V CC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: t pLH ∼ − t pHL•Wide operating voltage range: V CC (opr) = 2 to 5.5 V • Low noise: V OLP = 0.9 V (max)• Pin and function compatible with 74ALS273WeightSOP20-P-300-1.27A : 0.22 g (typ.) TSSOP20-P-0044-0.65A : 0.08 g (typ.) VSSOP20-P-0030-0.50: 0.03 g (typ.)TC74VHC273FTC74VHC273FTTC74VHC273FKPin AssignmentIEC Logic SymbolTruth TableX: Don’t careSystem DiagramV CC 16 Q8 D8 D7 15 14 CLR1234567D2 Q2 Q3 D3 D4 Q7 8D5 13 Q6 D6 (top view)Q1 D1 12 9Q4GND 10CK11Q5 19 18 17 20 (11)(1)(3)(7)(4)D11DD3D2(13)(8)(14)D5D4(2) (6) (12) Q1 Q3 Q5 (5) (9) (15)Q2 Q4 Q6R C1CKCLR D6(17)(18)D7(16) Q7 (19)Q8D8Absolute Maximum Ratings (Note)Characteristics Symbol Rating Unit Supply voltage range V CC−0.5 to 7.0 VDC input voltage V IN−0.5 to 7.0 VDC output voltage V OUT−0.5 to V CC+ 0.5 VInput diode current I IK−20 mA Output diode current I OK±20 mA DC output current I OUT±25 mA DC V CC/ground current I CC±75 mA Power dissipation P D 180mW Storage temperature T stg−65 to 150 °CNote: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction.Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and thesignificant change in temperature, etc.) may cause this product to decrease in the reliability significantlyeven if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolutemaximum ratings and the operating ranges.Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability testreport and estimated failure rate, etc).Operating Ranges (Note)Characteristics Symbol Rating Unit Supply voltage V CC 2.0 to 5.5 VInput voltage V IN0 to 5.5VOutput voltage V OUT0 to V CC VOperating temperature T opr−40 to 85 °CInput rise and fall time dt/dv 0 to 100 (V CC= 3.3 ± 0.3 V)0 to 20 (V CC= 5 ± 0.5 V)ns/VNote: The operating ranges must be maintained to ensure the normal operation of the device.Unused inputs must be tied to either VCC or GND.Electrical CharacteristicsDC CharacteristicsTest Condition Ta = 25°CTa = −40 to 85°CCharacteristics SymbolV CC (V)Min Typ.Max Min MaxUnitHigh-level input voltageV IH⎯2.03.0 to 5.5 1.50V CC × 0.7⎯ ⎯ ⎯ ⎯1.50 V CC × 0.7⎯ ⎯VLow-level input voltageV IL⎯2.03.0 to 5.5 ⎯ ⎯⎯ ⎯0.50 V CC × 0.3⎯ ⎯0.50V CC × 0.3VI OH = −50 μA2.03.04.5 1.9 2.9 4.4 2.0 3.0 4.5⎯ ⎯ ⎯ 1.9 2.9 4.4 ⎯ ⎯ ⎯ High-level output voltageV OHV IN= V IH or V ILI OH = −4 mA I OH = −8 mA3.04.5 2.583.94⎯ ⎯⎯ ⎯2.483.80⎯ ⎯VI OL = 50 μA2.03.04.5 ⎯ ⎯ ⎯ 0.0 0.0 0.00.1 0.1 0.1 ⎯ ⎯ ⎯ 0.1 0.1 0.1 Low-level output voltageV OLV IN= V IH or V ILI OL = 4 mA I OL = 8 mA3.04.5 ⎯ ⎯ ⎯ ⎯ 0.36 0.36⎯ ⎯ 0.440.44VInput leakage currentI IN V IN = 5.5 V or GND 0 to 5.5 ⎯ ⎯±0.1⎯±1.0μA Quiescent supply currentI CCV IN = V CC or GND5.5⎯⎯ 4.0 ⎯ 40.0μATiming Requirements (input: t r = t f = 3 ns)AC Characteristics (input: t r= t f= 3 ns)Note 1: Parameter guaranteed by design.t osLH= |t pLHm− t pLHn|, t osHL= |t pHLm− t pHLn|Note 2: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Average operating current can be obtained by the equation:I CC (opr)= C PD·V CC·f IN+ I CC/8 (per bit)And the total C PD when n pcs.of flip flop operate can be gained by the following equation:C PD (total) = 22 + 9·nNoise Characteristics (input: t r= t f= 3 ns)Test Condition Ta = 25°CUnit Characteristics SymbolV CC (V)Typ. MaxQuiet output maximum dynamic V OL V OLP C L= 50 pF 5.0 0.5 0.8 V Quiet output minimum dynamic V OL V OLV C L= 50 pF 5.0 −0.5 −0.8VMinimum high level dynamic inputV IHD C L= 50 pF 5.0 ⎯ 3.5 V voltageMaximum low level dynamic inputV ILD C L= 50 pF 5.0 ⎯ 1.5 V voltageInput Equivalent CircuitWeight: 0.22 g (typ.)Weight: 0.08 g (typ.)Weight: 0.03 g (typ.)RESTRICTIONS ON PRODUCT USE20070701-EN GENERAL •The information contained herein is subject to change without notice.•TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk.•The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.• Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.。

74系列芯片简介——功能与描述

74系列芯片简介——功能与描述

7400、74H00、74L00、74LS00、74S00、74HC00、74C00、74F00、74ALS00四2输入与非门Y=\AB。

7401、74LS01、74HC01、74ALS01四2输入与非门（OC）Y=\AB。

7402、74L02、74LS02、74S02、74HC02、74C02、74ALS02、74F02四2输入或非门。

Y=/A+B。

7403、74L03、74LS03、74ALS03、74S03、74HC037404、74H04、74L04、74S04、74HC04、74C04、74F04、74ALS04六反相器Y=/A。

7405、74H05、74LS05、74S05、74HC05、74F05、74ALS05六反相器（OC）Y=/A。

7406、74LS06六反相缓冲器/驱动器（OC、高压输出）Y=/A;是7405高耐压输出型，耐压30V。

7407、74LS07、74HC07六缓冲器/驱动器（OC、高压输出）Y=A; 30V耐高压输出。

7408、74LS08、74F08、74ALS08、74S08、74HC08、74C08四2输入与门Y=AB。

7409、74LS09、74F09、74ALS09、74S09、74HC09四2输入与门（OC）Y=AB。

7410、74H10、74L10、74LS10、74ALS10、74S10、74HC10、74C1074H11、74LS11、74S11、74F11、74ALS11、74HC11三3输入与门Y=ABC。

7412、74LS12、74ALS12三3输入与非门（OC）Y=\ABC。

7413、74LS13双4输入与非门Y=\ABCD。

7414、74LS14、74HC14、74C1474H15、74LS15、74ALS15、74S15三3输入与门（OC）Y=ABC。

7416、74LS16六反相缓冲器/驱动器Y=/A；7417、74LS17六缓冲器/驱动器（OC、高压输出）Y=A；15V耐压输出。

74AC273MTR,74AC273MTR,74AC273MTR, 规格书,Datasheet 资料

74AC273MTR,74AC273MTR,74AC273MTR, 规格书,Datasheet 资料

1/11April 2001s HIGH SPEED:s f MAX = 250MHz (TYP.) at V CC = 5V sLOW POWER DISSIPATION:I CC = 8µA(MAX.) at T A =25°C sHIGH NOISE IMMUNITY:V NIH = V NIL = 28 % V CC (MIN.)s50Ω TRANSMISSION LINE DRIVING CAPABILITYsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 6VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273sIMPROVED LATCH-UP IMMUNITYDESCRIPTIONThe 74AC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. Information signals applied to D inputs aretransfered to the Q output on the positive goingedge of the clock pulse.When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74AC273OCTAL D-TYPE FLIP FLOP WITH CLEARPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP 74AC273B SOP 74AC273M74AC273MTRTSSOP74AC273TTRs l c )d u c t () -O bs o e t eP r od u t (s74AC2732/11INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLELOGIC DIAGRAMThis logic diagram has not be used to estimate propagation delaysPIN No SYMBOL NAME AND FUNCTION 1CLEAR Asyncronous Master Reset (Active LOW)2, 5, 6, 9, 12, 15, 16,19Q0 to Q7Flip-Flop Outputs 3, 4, 7, 8, 13, 14, 17, 18D0 to D7Data Inputs11CLOCK Clock Input (LOW-to-HIGH Edge Triggered)10GND Ground (0V)20V CCPositive Supply Voltagel s l u )Ob so e t ePr od u c t () -O bs o e t eP r od c t(s74AC2733/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.RECOMMENDED OPERATING CONDITIONS1) V IN from 30% to 70% of V CCSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current± 400mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue UnitV CC Supply Voltage 2 to 6V V I Input Voltage 0 to V CCV V O Output Voltage 0 to V CCV T op Operating Temperature-55 to 125°Cdt/dvInput Rise and Fall Time V CC = 3.0, 4.5 or 5.5V (note 1)8ns/Vl s e c )Ob so e t ePr od u c t () -O bs o l t eP r od u t (s74AC2734/11DC SPECIFICATIONS2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50ΩSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage3.0V O = 0.1 V or V CC -0.1V 2.1 1.5 2.1 2.1V4.5 3.15 2.25 3.15 3.155.5 3.852.753.853.85V ILLow Level Input Voltage3.0V O = 0.1 V or V CC -0.1V 1.50.90.90.9V4.5 2.25 1.35 1.35 1.355.5 2.75 1.651.651.65V OHHigh Level Output Voltage3.0I O =-50 µA 2.9 2.99 2.9 2.9V4.5I O =-50 µA 4.4 4.49 4.4 4.45.5I O =-50 µA 5.4 5.495.4 5.43.0I O =-12 mA 2.56 2.46 2.44.5I O =-24 mA 3.86 3.76 3.75.5I O =-24 mA 4.864.764.7V OLLow Level Output Voltage3.0I O =50 µA 0.0020.10.10.1V4.5I O =50 µA 0.0010.10.10.15.5I O =50 µA 0.0010.10.10.13.0I O =12 mA 0.360.440.54.5I O =24 mA 0.360.440.55.5I O =24 mA 0.360.440.5I I Input Leakage Current5.5V I = V CC or GND ± 0.1± 1± 1µA I CC Quiescent Supply Current5.5V I = V CC or GND880160µA I OLD Dynamic Output Current (note 1, 2)5.5V OLD = 1.65 V max 7550mA I OHDV OHD = 3.85 V min-75-50mAl t l c )Ob so e t ePr od u c (s ) -O bs o e t eP r od u t (s74AC2735/11AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, R L = 500 Ω, Input t r = t f = 3ns)(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5VCAPACITIVE CHARACTERISTICSPD load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per circuit)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t PLH t PHL Propagation Delay TimeCLOCK to Q3.3(*)4.07.512.5 3.014.0 3.016.0ns5.0(**) 3.0 5.09.0 2.510.0 2.511.0t PHL Propagation Delay TimeCLEAR to Q3.3(*)4.08.513.0 3.014.0 3.016.0ns5.0(**) 3.06.510.02.511.02.512.0t W CLEAR Pulse Width, LOW3.3(*)5.56.0 6.0ns 5.0(**)4.0 4.5 4.5t W CLOCK Pulse Width3.3(*) 5.5 6.0 6.0ns5.0(**)4.0 4.5 4.5t s Setup Time D to CLOCK, HIGH orLOW3.3(*) 5.5 6.0 6.0ns5.0(**) 4.0 4.5 4.5t h Hold Time D toCLOCK, HIGH or LOW3.3(*) 1.5 1.5 1.5ns5.0(**) 1.5 1.51.5t REM Recovery Time CLEAR to CLOCK 3.3(*) 4.0 4.5 4.5ns 5.0(**) 3.0 3.0 3.0f MAXMaximum Clock Frequency3.3(*)907575MHz5.0(**)140250125125Symbol ParameterTest ConditionValueUnitV CC(V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance5.04pF C PDPower DissipationCapacitance (note 1)5.0f IN = 10MHz32pFc u t 74AC2736/11TEST CIRCUITC L = 50pF or equivalent (includes jig and probe capacitance)R L = R 1 = 500Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)74AC273 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)7/11l slc)O b s oe t eP ro du ct()-O bs oe t eP ro dut(s74AC273Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 11/11芯天下--/。

54LS47 74LS47 中文数据手册Data Sheet

54LS47 74LS47 中文数据手册Data Sheet

LS47 有自动前、后沿灭零控制（RBI 和 RBO）。试灯（LT）可在 BI/RBO 端处于高电平 的任何时刻去进行，该电路还含有一个灭灯输入（BI），它用来控制灯的亮度或禁止输出。
LS47 这种七段译码器在应用中可以驱动共阳极的发光二极管或直接驱动白炽灯指示器。
功能表
十进制 或功能
输 LT RBI
入
BT/RBO
输
出
注
DCBA
●
a
b
c
d
e
fg
0
H
H
LLLL
H
开 开 开 开 开 开关
1
H
x
LLLH
H
关 开 开 关 关 关关
2
H
x
LLHL
H
开 开 关 开 开 关开
3
H
x
LLHH
H
开 开 开 开 关 关开
4
H
x
LHLL
H
关 开 开 关 关 开开
5
H
x
LHLH
H
开 关 开 开 关 开开
6
H
x
LHHL
H
说明 LS47 是由“与非”门、输入缓冲器和 7 个“与一或—非”门组成的 BCD—7 段译码器/
驱动器。通常是低电平有效，高的灌入电流的输出可直接驱动显示器。7 个“与非”门和 1 个驱动器成对连接，以产生可用的 BCD 数据及其补码至 7 个“与—或—非”译码门。剩下 的“与非”门和 3 个输入缓冲器作为“试灯输入”LT 端、灭灯输入/动态灭灯输出 BI/RBO 端及动态灭灯输入 RBI 端。
14
H
x
HHHL
H
关 关 关 开 开 开开