74ABT125CSJ中文资料

© 2005 Fairchild Semiconductor Corporation DS011667March 1994Revised February 200574ABT125 Quad Buffer with 3-STATE Outputs74ABT125Quad Buffer with 3-STATE OutputsGeneral DescriptionThe ABT125 contains four independent non-inverting buff-ers with 3-STATE outputs.Featuress Non-inverting bufferss Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protections High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capabilitys Disable time less than enable time to avoid bus contentionOrdering Code:Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Pb-Free package per JEDEC J-STD-020B.Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.Connection Diagram Pin DescriptionsFunction TableH HIGH Voltage Level L LOW Voltage Level Z HIGH Impedance X ImmaterialOrder Number Package Package DescriptionNumber 74ABT125CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ABT125CSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74ABT125CMTC MTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT125CMTCX_NL (Note 1)MTC14Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names Descriptions A n , B n Inputs O nOutputsInputs Output A n B nO nLLL L H H HXZ 274A B T 125Absolute Maximum Ratings (Note 2)Recommended Operating ConditionsNote 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.Note 3: Either voltage limit or current limit is sufficient to protect inputs.DC Electrical CharacteristicsNote 4: Guaranteed, but not tested.Note 5: For 8 bits toggling, I CCD 0.8 mA/MHz.Storage Temperature65q C to 150q C Ambient Temperature under Bias 55q C to 125q CJunction Temperature under Bias 55q C to 150q CV CC Pin Potential to Ground Pin 0.5V to 7.0V Input Voltage (Note 3) 0.5V to 7.0V Input Current (Note 3) 30 mA to 5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State 0.5V to 5.5V in the HIGH State 0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (mA)DC Latchup Source Current (Across Comm Operating Range) 300 mAOver Voltage Latchup (I/O)10VFree Air Ambient Temperature 40q C to 85q C Supply Voltage4.5V to5.5VMinimum Input Edge Rate ('V/'t)Data Input 50 mV/ns Enable Input20 mV/nsSymbol ParameterMin Typ Max Units V CC ConditionsV IH Input HIGH Voltage V Recognized HIGH Signal V IL Input LOW Voltage 0.8V Recognized LOW SignalV CD Input Clamp Diode Voltage 1.2V Min I IN 18 mA V OH Output HIGH Voltage 2.5V Min I OH 3 mA 2.0VMin I OH 32 mA V OL Output LOW Voltage 0.55V Min I OL 64 mA I IH Input HIGH Current1P A Max V IN 2.7V (Note 4)1V IN V CC I BVI Input HIGH Current Breakdown Test 7P A Max V IN 7.0V I IL Input LOW Current 1P A Max V IN 0.5V (Note 4) 1V IN 0.0VV ID Input Leakage Test V 0.0I ID 1.9 P A, All Other Pin Grounded I OZH Output Leakage Current 10P A 0 5.5V V OUT 2.7V; OE n 2.0V I OZL Output Leakage Current 10P A 0 5.5V V OUT 0.5V; OE n 2.0V I OS Output Short-Circuit Current 275mA Max V OUT 0.0V I CEX Output HIGH Leakage Current 50P A Max V OUT V CCI ZZ Bus Drainage Test 100P A 0.0V OUT 5.5V; All Others GND I CCH Power Supply Current 50P A Max All Outputs HIGH I CCL Power Supply Current 15mA Max All Outputs LOW I CCZ Power Supply Current 50P A MaxOE n V CC ;All Others at V CC or GroundI CCTAdditional I CC /InputOutputs Enabled 1.5mA Max V I V CC 2.1VOutputs 3-STATE 1.5mA Enable Input V I V CC 2.1V Outputs 3-STATE50P A Data Input V I V CC 2.1V All Others at V CC or GroundI CCDDynamic I CC No LoadmA/MaxOutputs Open (Note 4)0.1MHzOE n GND, (Note 5)One Bit Toggling, 50% Duty Cycle74ABT125AC Electrical CharacteristicsCapacitanceNote 6: C OUT is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.T A 25q CT A 40q C to 85q C SymbolParameterV CC 5V V CC 4.5V–5.5V UnitsC L 50 pFC L 50 pF MinTypMax Min Max t PLH Propagation Delay 1.0 4.6 1.0 4.6 ns t PHL Data to Outputs 1.0 4.9 1.0 4.9 t PZH Output Enable 1.0 5.1 1.0 5.1 ns t PZL Time1.0 6.8 1.0 6.8 t PHZ Output Disable 1.0 6.2 1.0 6.2 ns t PLZTime1.05.51.05.5Symbol ParameterTyp Units Conditions T A 25q CC INInput Capacitance 5.0 pF V CC 0V C OUT (Note 6)Output Capacitance9.0pFV CC 5.0V 474A B T 125Physical Dimensions inches (millimeters) unless otherwise noted14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M14A 74ABT125Physical Dimensions inches (millimeters) unless otherwise noted (Continued)Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D674A B T 125 Q u a d B u f f e r w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC14Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。