普适介电弛豫讲习班共60页文档

普适弛豫定律普适弛豫定律（Universal Relaxation Law）是物理学中一个重要的概念，它描述了在普适弛豫定律（Universal Relaxation Law）是物理学中一个重要的概念，它描述了在热力学过程中，系统从一个非平衡状态向平衡状态过渡时，其能量分布和粒子运动状态的变化规律。

这个定律在许多不同的物理系统中都有应用，如固体物理、统计物理、化学等领域。

本文将对普适弛豫定律进行详细的介绍，包括其基本概念、数学表述、实验验证以及在不同领域的应用。

一、基本概念普适弛豫定律的基本思想是：在一个封闭的系统中，当系统受到外部扰动而偏离平衡状态时，系统的能量分布和粒子运动状态会随着时间的推移而发生变化，最终趋向于一个稳定的平衡状态。

在这个过程中，系统的能量分布和粒子运动状态的变化遵循一定的规律，这个规律就是普适弛豫定律。

二、数学表述普适弛豫定律可以用数学公式来表示。

对于一个封闭的系统，其能量分布可以表示为：E(t) = E0 + ∫V ρ(r, t) [H(r, t) - H0] dr其中，E(t)表示系统在时刻t的能量；E0表示系统的初始能量；ρ(r, t)表示系统在时刻t的密度分布；H(r, t)表示系统在时刻t的总哈密顿量；H0表示系统的初始哈密顿量。

上式表明，系统的能量分布是由系统的密度分布和总哈密顿量共同决定的。

普适弛豫定律还可以用来描述粒子运动状态的变化。

对于一个封闭的系统，其粒子运动状态可以用波函数Ψ(r, t)来表示。

根据量子力学的理论，波函数Ψ(r, t)满足薛定谔方程：iħ∂Ψ/∂t = HΨ其中，i是虚数单位；ħ是约化普朗克常数。

上式表明，波函数Ψ(r, t)随时间的变化是由系统的总哈密顿量H决定的。

根据普适弛豫定律，波函数Ψ(r, t)随时间的变化可以表示为：Ψ(r, t) = e^(-iH0t/ħ)Ψ0(r)其中，Ψ0(r)表示系统的初始波函数；e^(-iH0t/ħ)表示系统在时刻t的状态演化算符。

波尔兹曼常数：K J k 231038.1-⨯=电介质的极化克劳休斯方程：()E E N E N E P ee r αεεαεε+=⇒=-=001，其中N 为单位体积内的粒子数洛伦兹有效电场：E E E E e ''+'+=0立方点整结构的NaCl 型离子晶体、非极性分子、弱极性： K-M 方程：αεεεN r r 03121=+-，单原子气体、相同原子组成的双原子气体以及具有对称机构的多原子气体均为非极性气体和弱极性液体、电介质的极化形式主要是电子位移极化：e αα=；非极性固体：e αα=； 应当注意的是固体电介质的热膨胀效应V dTdVV dTdNN β-=-=11，L V ββ3=极性气体分子电介质：d e ααα+=；极性液体电介质：()221103121ααεεεN N r r+=+- 立方点整结构的NaCl 型离子晶体电介质：a e e αααα++=-+电介质的损耗γωωωαi m e +-=22021，γωi 为阻尼力的影响 加上电场：()τt rm r e P t P --=1)(，移除电场：τt rm r e P t P -=)(恒定电场下的吸收电流：加上电场：ττt t am a gAEe ei i --== 到达稳态后移去电场：ττt t am a gAEe ei i ---=-= 在交变电场作用下t E t E m ωsin )(= 1、极化强度：()()()t P t P t P r +=∞ 2、介质中的电流：()()()()()()()()()tI I t I I t i t i t i t i t i t i t i rrm m ram Rm ra rr R P R ωωcos sin +++=+++=+=∞∞3、介质中的损耗：介电常数：221τωεεεε+-+=∞∞S介电损耗：()222220)(1AdE g AdE W S +=⎥⎦⎤⎢⎣⎡+-+=∞γτωτωεεεγ 单位体积内的介电损耗：()222220)(1E g E P s +=⎥⎦⎤⎢⎣⎡+-+=∞γτωτωεεεγ 介电损耗角正切：()εωεγεωετωτωεεεγδ0022201tan g s +=+-+=∞ 复介电系数和德拜函数εεε''-'=i ，ωτεεεεi s +-+=∞∞1 ；推出德拜方程如下：德拜函数：22221,11τωωτεεετωεεεε+=-''+=--'∞∞∞S S 当温度一定的时候 根据0=∂''∂ωε找出ε''最大值所对应的频率，τω1=m 当m ωω=时，()∞+='εεεS 21，()∞-=''εεεS 21max ，∞∞+-=εεεεδS S tan根据()0tan =∂∂ωδ得到δtan 最大值时的频率：mSmεετω1=' 当m ωω'=时，∞∞∞∞∞∞∞-=+-=''+='εεεεδεεεεεεεεεεεεS S S S SS S 2tan ,,2maxFigure: s S 1010,2,10-∞===τεεCole-Cole 图：圆弧上的每一点对应于德拜方程计算出来的某一频率ε'，ε''的值温度变化时：当温度升高时，ε'，ε''同时向高频方向 移动，而S ε，maxε''值稍有下降低温时，中温时，高温时ε'，ε'' 当频率升高时ε'，ε''同时向高温方向移动而S ε，maxε''值稍有下降 电介质的电导和击穿电介质的导电形式：离子电导、电子电导、电泳电导 电流密度：deJ J α0=，()110--=d de e J J ααγ电场加强了以后： 这时：∞→J 气体介质自持放电。

2008年 第53卷 第9期: 1022 ~ 10251022 《中国科学》杂志社SCIENCE IN CHINA PRESS论 文高温超导微波限幅滤波器补世荣①②, 羊恺①②, 陶伯万①, 陈光荣③, 齐锋③, 李言荣①, 罗正祥①, 张其劭①① 电子科技大学电子薄膜与集成器件国家重点实验室, 成都 610054; ② 电子科技大学空天技术研究院, 成都 610054; ③ 南京电子技术研究所, 南京 210013 E-mail: bsr@2007-12-29收稿, 2008-04-16接受国家高技术研究发展计划(编号: 2007AA03Z212)和电子科技大学青年基金(批准号: L08047401JX0649)资助项目摘要 利用高温超导薄膜材料的临界电流特性, 并与微波谐振器的电流分布特性相结 合, 在同一微波器件中实现限幅和滤波功能. 理论分析和实验结果表明, 在通讯和雷达系统应用中, 该器件可以在极大提高系统灵敏度的同时增强系统抗干扰和抗烧毁能力.关键词 高温超导 滤波器 限幅器 接收机 抗干扰高温超导薄膜材料在微波器件中的应用已进入产业化阶段, 其典型应用包括移动通信基站接收系统以及各类军民用通信和雷达接收前端等[1]. 在目前的高温超导接收系统中, 利用超导薄膜的低微波损耗特性是应用的重点, 而据此特性设计的微波滤波器则形成当前产业化应用的主流. 事实上, 高温超导材料还具有许多独特性能, 如临界电流特性、非线性特性和量子效应等, 对于这些特性的研究也已形成各种器件应用, 包括利用临界电流特性进行工作的微波限幅器[2]、利用量子效应工作的各种Josephson 器件等. 但是由于各种特性需要在独特的工艺条件及电路布局设计下才能达到最佳应用效果, 因此目前的许多器件应用都处于追求单一器件的最佳性能设计上, 使得超导材料本身的各种优异性能不能同时体现. 如果需要同时应用多种性能, 目前的解决方法主要是将不同的超导器件集成在一起使用, 这样的优点很明显, 但也存在工艺复杂、整体性能低等问题.本文从通信系统接收前端的结构出发, 分析超导材料引入系统对系统性能及结构的影响, 并据此提出限幅/滤波合一器件的必要性和可能性. 然后以超导材料的特性为基础, 结合滤波器结构讨论限幅滤波器的构建方案, 提出了以滤波器为框架, 在谐振器内部引入微桥来实现限幅滤波的方案, 并完成了原型限幅滤波器件的设计、加工和测试. 最后对测试结果进行了分析.1 高温超导接收前端1.1 常规接收机前端常规微波接收机前端[3]一般由图1(a)和(b)所示的两种结构构成. 该接收机前端包括天线、限幅器、低噪声放大器、带通滤波器和下变频模块等, 完成微波图1 微波接收机的构成(a) 低噪放前置的接收前端; (b) 低噪放后置于滤波器的接收前端;(c) 高温超导接收前端1023信号的接收、放大和混频处理功能. 为完成信号的高质量接收, 需要从最佳系统噪声设计考虑, 通常当滤波器噪声大于低噪放噪声时, 系统设计需要后置滤波器(图1(a)), 反之则前置滤波器(图1(b)). 图中限幅器主要用于对敏感元件低噪声放大器进行电平保护. 这种传统的系统方案最大的缺点是限幅器在受到通带外强信号干扰时容易被阻塞, 不能适应现代复杂电磁环境下的通讯需求. 1.2 高温超导限幅接收前端如果将图1(b)中的限幅器和带通滤波器做在一起(图1(c)), 对于带外强干扰信号就可以由滤波器反射抑制而不会造成阻塞[4], 带内则由限幅器进行保护. 这样的接收方案在系统噪声(一个器件的噪声比两个器件的噪声低)、抗干扰性能和抗烧毁能力方面将大大优于传统方案. 而系统的关键就是限幅滤波器的实现, 就现有文献和专利资料来看, 目前还没有相关的常规器件具有这样的功能.2 高温超导限幅滤波器的实现对于高温超导微波限幅器, 目前主要有两种方案实现, 其中一种是通过在均匀微带传输线上加微桥结构实现, 另外一种是利用共面波导结构实现微细50 Ω传输线条来达到限幅目的. 对比这两种结构的微波限幅器, 可以发现微桥结构限幅器对实现工艺要求不高但适用带宽较窄, 而共面波导结构要求工艺高但适用带宽非常宽(几乎可以适用于全微波频段). 对于高温超导微波滤波器, 最常见的结构是由半波长微带谐振器通过各种耦合方式构成, 现在需要构成微波限幅滤波器, 最直观的方法就是将限幅器采用的两种方案直接应用于微带滤波器的谐振器上, 为此需要对这两种方案进行对比分析.与高温超导微波限幅器工作的行波状态相比, 微波滤波器中谐振器上的微波电流主要处于驻波状态, 这种谐振器工作在基波谐振状态时, 谐振器中部的微波电流分布最强(沿谐振器方向的电流分布). 因此, 如果要在谐振器内部引入微桥结构实现限幅滤波器, 则需要选取微桥的位置, 为了达到最大的限幅效果, 我们考虑在微波电流最强的地方引入微桥.下面以开口环谐振器滤波器[5]为例, 先对比均匀微带线谐振器滤波器(如图2(a), 图中谐振器上谐振电流越强, 灰度级越高, 下同)和在谐振器内部引入微桥的滤波器(如图2(b), 其中微桥宽度为10 µm, 长度为200 µm)两者的谐振电流分布情况. 如图2(a)所示, 均匀微带线谐振器上的电流分布沿谐振器方向呈抛物线分布, 两端电流小, 中间电流大. 而对于引入微桥的谐振器, 谐振时谐振电流大大集中在微桥上(见图2(b)~(d)). 由于微桥上集中的微波电流对限幅很有利, 同时滤波器工作带宽不宽而且由于长细图2 微桥结构引入对滤波器谐振电流分布的影响(a) 均匀线开口环滤波器的谐振电流分布; (b) 谐振器内部引入微桥的开口环滤波器的谐振电流分布; (c) 谐振时微桥部分电流分布仿真结果(谐振频率处, 红色电流分布强, 蓝色电流分布弱); (d) 非谐振时微桥部分电流分布仿真结果2008年5月 第53卷 第9期1024微带线滤波器难以实现, 我们可以选定微桥结构的限幅滤波器实现.3 限幅滤波器的制作及测试结果按上述思路我们在YBCO/LAO/YBCO 双面高温超导薄膜[6]上设计并制作了工作在S 波段的高温超导限幅滤波器. 该滤波器采用标准湿法光刻工艺完成. 图3是在输入功率为−10 dBm 时测得的滤波器性能,图4是在输入功率为15 dBm 时测得的滤波器性能.滤波器的限幅功率在滤波器中心频率按文献[7]所述方案进行测试, 测试结果如图4所示. 该滤波器针对接收机系统应用的结果及系统应用情况见文献[4].图3 S 波段限幅滤波器低功率情况下的滤波特性输入功率为−10 dBm图4 S 波段限幅滤波器限幅情况下的滤波特性输入功率为15 dBm4 测试结果分析从图3的滤波器测试结果来看, 整个通带内的插入损耗小于0.3 dB, 略大于普通微带线高温超导滤波器[8], 这是由于谐振器内部引入微桥结构造成谐振器Q 值下降, 从滤波器的反射、形状和带外抑制来看, 微桥结构的引入并无明显影响.图4是输入功率超过限幅电平时的滤波器测试形状. 从图中可以看到, 当输入功率超过限幅电平时滤波器起衰减器作用, 但由于谐振器是频率敏感元件, 整体衰减性能并不平坦, 若能实现平坦衰减或对于窄带信号, 该限幅滤波器即使限幅工作后也可以在后端检测信号, 将可起到自动增益调整器的作用, 这一特点可能是该器件与常规限幅器相比的最大优势.从图5所示的功率测试结果可以看到, 本文设计的限幅滤波器限幅电平为12.5 dBm, 该限幅电平与常规零偏压PIN 二极管限幅器限幅电平相当, 但该限幅电平是在微带微桥线宽为10µm 时获得的, 如果选用更窄的微桥线宽将可以获得更低的限幅电平, 显然该限幅器与常规PIN 二极管相比具有更大的限幅电平设计灵活性, 并且不需要复杂的偏压电路来实现.图5 限幅滤波器功率容量测试结果对于接收系统使用该限幅滤波器的效果详见文献[4], 在灵敏度、抗干扰性能和抗烧毁能力等方面均大大优于常规接收系统, 并在抗干扰性能和抗烧毁能力方面优于普通高温超导接收机前端系统. 5 结论本文同时利用高温超导薄膜的低微波损耗特性和临界电流特性构建并实现了高温超导限幅滤波器,单一器件测试和系统测试证明该方案可行. 该器件的成功实现证明, 同时利用高温超导材料的多种特性实现创新型器件将大大拓展高温超导材料的应用范围, 并体现高温超导材料不可替代的重要性. 关于高温超导限幅滤波器的研究还需要在限幅电平设计等与材料科学直接相关的领域作进一步工作.参考文献1 Mansour R R. Microwave superconductivity. IEEE Trans Microw Theory Tech, 2002, 50: 750—7592 Booth J C, Rudman D A, Ono R H. A self-attenuating superconducting transmission line for use as a microwave power limiter. IEEETrans Appl Supercond, 2003, 13(2): 305—3103 Laskar J, Matinpour B, Chakraborty S. Modern Receiver Front-Ends: Systems, Circuits, and Integration. Hoboken, New Jersey: JohnWiley & Sons, Inc. 20044 羊恺, 补世荣, 刘娟秀, 等. 限幅自保护高温超导接收机前端研究. 电子科技大学学报, 2007, 36(2): 223—2265 Hong J S, Lancaster M J. Couplings of microstrip square open-loop resonators for cross-coupled planar microwave filters. IEEETrans-MTT, 1996, 44(9): 2099—21096 Tao B W, Chen J J, Liu X Z, et al. Speed modulation technique to achieve simultaneous deposition of 3-in. double-sided Y-Ba-Cu-Othin films. Physica C, 2005, 433: 87—927 Shen Z Y. High-temperature superconducting microwave circuits. Boston, MA: Artech House, 19948 羊恺, 补世荣, 张其劭, 等. 高温超导小型化多曲折线滤波器研制. 科学通报, 2002, 49(18): 1378—1380·动态·第12届全国电介质物理、材料与应用学术会议在西安召开由中国物理学会电介质物理专业委员会主办、西安交通大学电子陶瓷与器件教育部重点实验室承办的“第12届全国电介质物理、材料与应用学术会议”于2008年4月17~20日在西安交通大学隆重召开. 包括1名院士、2名“973”首席科学家、4名长江学者和6名国家杰出青年科学基金获得者在内的电介质各相关领域的283名代表齐聚西安, 开展交流互动, 共商合作, 分享研究成果, 启迪创新思维.本届会议为中国物理学电介质物理专业委员会主办的系列学术会议, 旨在展示我国电介质物理及交叉领域所取得的重要进展和创新成果, 促进我国电介质物理的学术繁荣和创新. 本次会议是历届会议中规模最大的. 大会主席由西安交通大学任巍和徐卓两位教授担任, 开幕式上, 全国人大常委会委员、西安交通大学副校长蒋庄德教授和任巍教授先后致辞.本届会议共收到论文摘要252篇, 研究内容涉及电介质理论、压电材料、介电材料、多铁性材料、低维介质与薄膜材料、测试与表征和器件与加工方面. 会议安排了5个大会报告、7个专题分会和1个墙报分会. 每个专题分会安排7~8个特邀报告, 共有60位知名学者或在该领域做出有影响工作的学者作特邀报告, 66人作口头报告. 此外, 会议还设墙报119篇. 美国的陈充林教授和潘晓晴教授、加拿大的叶作光教授, 以及日本、新加坡的几位学者, 均专程回国参加会议并作报告.本届会议还专门组织电介质领域的8位专家学者在会前举办了为期2天的“普适介电弛豫讲习班”, 着重讲解A. K. Jonscher教授编著Dielectric Relaxation in Solids和Universal Relaxation Law两本专著. 该书是姚熹院士引进发行的经典电介质科学丛书影印本教材系列中的两本, 是电介质弛豫理论的经典著作. 共有来自全国50多个大专院校和科研院所的240人参加了本次讲习班.会议期间, 中国物理学会电介质物理专业委员会召开工作会议, 决定第13届全国电介质物理、材料与应用会议将于2010年在成都召开, 由电子科技大学承办; 第14届全国电介质物理、材料与应用会议将于2012年在武汉召开,由湖北大学承办. 另外, 本届会议主席任巍和徐卓教授还介绍了将于2009年8月23~27日在西安联合举行的“第12届国际铁电学会议(IMF12)”和“第18届IEEE国际铁电应用会议(ISAF)”的筹备情况. 这两个会议是铁电学界最主要的学术会议, 均为第一次在中国举行, 对于促进我国铁电和电介质的发展, 向世界全面展示我国在铁电和电介质方面的研究进展和取得的成果, 具有重要意义.1025。

ISP1582Hi-Speed Universal Serial Bus peripheral controllerRev. 03 — 25 August 2004Preliminary data1.General descriptionThe ISP1582 is a cost-optimized and feature-optimized Hi-Speed Universal SerialBus (USB) peripheral controller. It fully complies with Universal Serial BusSpecification Rev.2.0, supporting data transfer at high-speed (480Mbit/s) andfull-speed (12Mbit/s).The ISP1582 provides high-speed USB communication capacity to systems basedon microcontrollers or microprocessors. It communicates with a microcontroller ormicroprocessor of a system through a high-speed general-purpose parallel interface.The ISP1582 supports automatic detection of Hi-Speed USB system operation.Original USB fall-back mode allows the device to remain operational under full-speedconditions. It is designed as a generic USB peripheral controller so that it can fit intoall existing device classes, such as imaging class, mass storage devices,communication devices, printing devices and human interface devices.The internal generic Direct Memory Access (DMA) block allows easy integration intodata streaming applications.The modular approach to implementing a USB peripheral controller allows thedesigner to select the optimum system microcontroller from the wide variety available.The ability to reuse existing architecture and firmware investments shortens thedevelopment time, eliminates risk and reduces cost. The result is fast and efficientdevelopment of the most cost-effective USB peripheral solution.The ISP1582 is ideally suited for many types of peripherals, such as: printers,scanners, digital still cameras, USB-to-Ethernet links, cable and DSL modems. Thelow power consumption during suspend mode allows easy design of equipment thatis compliant to the ACPI™, OnNow™ and USB power management requirements.The ISP1582 also incorporates features such as SoftConnect™, a reducedfrequency crystal oscillator,and integrated termination resistors.These features allowsignificant cost savings in system design and easy implementation of advanced USBfunctionality into PC peripherals.2.Featuress Complies fully with:x Universal Serial Bus Specification Rev.2.0x Most Device Class specificationsx ACPI™, OnNow™ and USB power management requirements.s Supports data transfer at high-speed (480Mbit/s) and full-speed (12Mbit/s)s High performance USB peripheral controller with integrated Serial InterfaceEngine (SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver s Automatic Hi-Speed USB mode detection and Original USB fall-back modes Supports sharing modes Supports V BUS sensings High-speed DMA interfaces Fully autonomous and multiconfiguration DMA operations7 IN endpoints, 7 OUT endpoints and a fixed control IN/OUT endpoints Integrated physical 8kbytes of multiconfiguration FIFO memorys Endpoints with double buffering to increase throughput and ease real-time datatransfers Bus-independent interface with most microcontrollers and microprocessorss12MHz crystal oscillator with integrated PLL for low EMIs Software-controlled connection to the USB bus (SoftConnect™)s Low-power consumption in operation and power-down modes; suitable for use inbus-powered USB devicess Supports Session Request Protocol (SRP) that complies with On-The-GoSupplement to the USB Specification Rev.1.0as Internal power-on and low-voltage reset circuits; also supports software resets Operation over the extended USB bus voltage range (DP, DM and V BUS)s5V tolerant I/O pads at 3.3Vs Operating temperature range from−40°C to +85°Cs Available in HVQFN56 halogen-free and lead-free package.3.Applicationss Personal digital assistants Digital video cameras Digital still cameras3G mobile phones MP3 players Communication device, for example: router and modems Printers Scanner.4.AbbreviationsDMA —Direct Memory AccessEMI —ElectroMagnetic InterferenceFS —Full-speedGDMA —Generic DMAHS —High-speedMMU —Memory Management UnitNRZI —Non-Return-to-Zero InvertedOTG —On-The-GoPDA —Personal Digital AssistantPID —Packet IDentifierPIE —Parallel Interface EnginePIO —Parallel Input/OutputPLL —Phase-Locked LoopSE0 —Single-Ended zeroSIE —Serial Interface EngineSRP —Session Request ProtocolUSB —Universal Serial Bus.5.Ordering informationTable 1:Ordering informationType number PackageName Description VersionISP1582BS HVQFN56plastic thermal enhanced very thin quadflat package;no leads; 56terminals; body 8×8×0.85mmSOT684-1xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x xPhilips SemiconductorsISP1582Hi-Speed USB peripheral controller9397 750 13699© Koninklijke Philips Electronics N.V . 2004. All rights reserved.Preliminary data Rev. 03 — 25 August 20044 of 666.Block diagramFig 1.Block diagram.1.5k Ω12.0k ΩV CC004aaa199ISP1582MEMORY MANAGEMENTUNITINTEGRATEDRAM (8 KBYTES)SYSTEM CONTROLLERVOLT AGE REGULA TORSPOWER-ON RESETHI-SPEED USB TRANSCEIVERinternal resetSoftConnectanalog supplydigital supplyI/O pad supplyMICRO-CONTROLLER HANDLER MICRO-CONTROLLER INTERFACEOTG SRP MODULEDMA REGISTERSDMA HANDLERDMA INTERFACEPHILIPS SIE/PIEINTDATA [15:0]A [7:0]8DACK3.3 VV CC(1V8)SUSPENDWAKEUPAGNDDGND 3.3 VRD_N EOTV CC(I/O)161, 5278DREQDIORDIOW910111213, 26, 29, 4114CS_N WR_N 15161718 to 20,22 to 25,2721, 34, 4828, 5030 to 33,35 to 40,42 to 4712 MHzXTAL2XTAL1to/from USB DMDP V BUS4349525153, 5455566RPURREFRESET_N7.Pinning information7.1PinningFig 2.Pin configuration HVQFN56 (top view).Fig 3.Pin configuration HVQFN56 (bottom view).DATA0DATA1DATA2DATA10V CC(I/O)DATA4DATA5DATA6DATA7DATA8DATA9DGND D A T A 13D A T A 14C S _N RD _N W R _N A 1A 2A 3A 4A 5A 6D G N D A 7V C C (1V 8)S U S PE N DD A T A 15V C C (1V 8)V B U S X T A L 1X T A L 2D A T A 12D A T A 11V C CV C C (I /O )DATA3W A K E U P V C CDGNDV C C (I /O )A 0004aaa536ISP1582BS1314121110968455153494746485052545556262124254344282723222019171518164753293134333032353638403739214241INT DIOW DIOR DGND DREQDACK RESET_NEOT AGND DM RREF RPU AGND DP DGND DATA9DATA8DGND DATA6DATA5DATA4V CC(I/O)DATA3DATA2DATA1DATA0D G N DA 6AGNDDP DM RPU RREFAGND EOT RESET_NDACK DIOR DREQ DGND INT S U S P E N D W A K E U P V C C X T A L 1X T A L 2V B U S V C C (I /O )D A T A 15D A T A 14D A T A 13D A T A 12D A T A 11C S _NA 5V C C (I /O )A 3DIOW A 1A 2A 7V C C (1V 8)A 0A 4DATA7R D _NW R _NDATA10V C C (1V 8)V C C 004aaa377ISP1582BS2134569726201822242523211917161545504746282743444849515254565355118101242403738413936353331343213142930Bottom Viewterminal 1GND (exposed die pad)7.2Pin descriptionTable 2:Pin descriptionSymbol[1]Pin Type[2]DescriptionAGND1-analog groundRPU2A connect to the external pull-up resistor for pin DP; must beconnected to 3.3V via a 1.5kΩ resistorDP3A USB D+ line connection (analog)DM4A USB D− line connection (analog)AGND5-analog groundRREF6A connect to the external bias resistor; must be connected toground via a 12.0kΩ±1% resistorRESET_N7I reset input(500µs);a LOW level produces an asynchronousreset; connect to V CC for the power-on reset (internal PORcircuit)TTL; 5V tolerantEOT8I End-of-transfer input (programmable polarity); used in DMAslave mode only;when not in use,connect this pin to V CC(I/O)through a 10kΩ resistorinput pad; TTL; 5V tolerantDREQ9O DMA request (programmable polarity) output; when not inuse,connect this pin to ground through a10kΩresistor;seeT able54 and T able55TTL; 4ns slew-rate controlDACK10I DMA acknowledge input (programmable polarity); when notin use, connect this pin to V CC(I/O) through a 10kΩ resistor;see T able54 and T able55TTL; 5V tolerantDIOR11I DMA read strobe input(programmable polarity);when not inuse,connect this pin to V CC(I/O)through a10kΩresistor;seeT able54 and T able55TTL; 5V tolerantDIOW12I DMA write strobe input(programmable polarity);when not inuse,connect this pin to V CC(I/O)through a10kΩresistor;seeT able54 and T able55TTL; 5V tolerantDGND13-digital groundINT14O interrupt output; programmable polarity (active HIGH orLOW) and signaling (edge or level triggered)CMOS output; 8mA driveCS_N15I chip select inputinput pad; TTL; 5V tolerantRD_N16I read strobe inputinput pad; TTL; 5V tolerantWR_N17I write strobe inputinput pad; TTL; 5V tolerantTable 2:Pin description…continuedSymbol[1]Pin Type[2]DescriptionA018I bit0 of the address businput pad; TTL; 5V tolerantA119I bit1 of the address businput pad; TTL; 5V tolerantA220I bit2 of the address businput pad; TTL; 5V tolerantV CC(I/O)[3]21-supply voltage; used to supply voltage to the I/O pads; seeSection8.14A322I bit3 of the address businput pad; TTL; 5V tolerantA423I bit4 of the address businput pad; TTL; 5V tolerantA524I bit5 of the address businput pad; TTL; 5V tolerantA625I bit6 of the address businput pad; TTL; 5V tolerantDGND26-digital groundA727I bit7 of the address businput pad; TTL; 5V tolerantV CC(1V8)[3]28-regulator output voltage(1.8V±0.15V);tapped out voltagefrom the internal regulator; this regulated voltage cannotdrive external devices; decouple this pin using a 0.1µFcapacitor; see Section8.14DGND29-digital groundDA T A030I/O bit0 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A131I/O bit1 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A232I/O bit2 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A333I/O bit3 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerantV CC(I/O)[3]34-supply voltage; used to supply voltage to the I/O pads; seeSection8.14DA T A435I/O bit4 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A536I/O bit5 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A637I/O bit6 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A738I/O bit7 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerantTable 2:Pin description…continuedSymbol[1]Pin Type[2]DescriptionDA T A839I/O bit8 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A940I/O bit9 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DGND41-digital groundDA T A1042I/O bit10 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A1143I/O bit11 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A1244I/O bit12 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A1345I/O bit13 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A1446I/O bit14 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerant DA T A1547I/O bit15 of bidirectional data busbidirectional pad; 4ns slew-rate control; TTL; 5V tolerantV CC(I/O)[3]48-supply voltage; used to supply voltage to the I/O pads; seeSection8.14V BUS49A USB bus power pin sensing input; used to detect whetherthe host is connected or not; it is an output for V BUS pulsingin OTG mode; when V BUS is not detected, pin RPU isinternally disconnected from pin DP in approximately 4ns;connect a 1µF electrolytic capacitor and a 1MΩ pull-downresistor to ground; see Section8.125V tolerantV CC(1V8)[3]50-regulator output voltage(1.8V±0.15V);tapped out voltagefrom the internal regulator; this regulated voltage can driveexternal devices up to 1mA; decouple this pin using 4.7µFand 0.1µF capacitors; see Section8.14XT AL251O crystal oscillator output (12MHz); connect a fundamentalparallel-resonant crystal; leave this pin open-circuit whenusing an external clock source on pin XT AL1; see T able83 XT AL152I crystal oscillator input (12MHz); connect a fundamentalparallel-resonant crystal or an external clock source(leavingpin XTAL2 unconnected); see T able83V CC[3]53-supply voltage (3.3V±0.3V); this pin supplies the internalvoltage regulator and the analog circuit; see Section8.14V CC[3]54-supply voltage (3.3V±0.3V); this pin supplies the internalvoltage regulator and the analog circuit; see Section8.14[1]Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.[2]All outputs and I/O pins can source 4mA.[3]Add a decoupling capacitor (0.1µF) to all the supply pins. For better EMI results, add a 0.01µF capacitor in parallel to the 0.1µF .WAKEUP55Iwake-up input;when this pin is at the HIGH level,the chip is prevented from getting into the suspend state and the chip wakes up from the suspend state; when not in use, connect this pin to ground through a 10k Ω resistor input pad; TTL; 5V tolerantSUSPEND 56Osuspend state indicator output; used as a power switch control output for powered-off application or as a resume signal to the CPU for powered-on application CMOS output; 8mA driveGNDexposed die pad-ground supply; down bonded to the exposed die pad (heatsink); to be connected to DGND during PCB layoutTable 2:Pin description …continued Symbol [1]Pin Type [2]Description8.Functional descriptionThe ISP1582 is a high-speed USB peripheral controller. It implements the Hi-SpeedUSB or the Original USB physical layer and the packet protocol layer.It maintains upto 16USB endpoints concurrently (control IN and control OUT, 7IN and 7OUTconfigurable) along with endpoint EP0 setup, which accesses the setup buffer. TheUSB Chapter9 protocol handling is executed by means of external firmware.For high-bandwidth data transfer, the integrated DMA handler can be invoked totransfer data to or from external memory or devices. The DMA interface can beconfigured by writing to the proper DMA registers (see Section9.4).The ISP1582 supports Hi-Speed USB and Original USB signaling. The USBsignaling speed is automatically detected.The ISP1582 has 8kbytes of internal FIFO memory, which is shared among theenabled USB endpoints.There are 7IN endpoints, 7OUT endpoints and 2control endpoints that are a fixed64bytes long. Any of the 7IN and 7OUT endpoints can be separately enabled ordisabled. The endpoint type (interrupt, isochronous or bulk) and packet size of theseendpoints can be individually configured depending on the requirements of theapplication. Optional double buffering increases the data throughput of these dataendpoints.The ISP1582 requires 3.3V power supply. It has 5V tolerant I/O pads whenoperating at V CC(I/O)=3.3V and an internal 1.8V regulator for powering the analogtransceiver.The ISP1582 operates on a 12MHz crystal oscillator. An integrated 40×PLL clockmultiplier generates the internal sampling clock of 480MHz.8.1DMA interface, DMA handler and DMA registersThe DMA block can be subdivided into two blocks: the DMA handler and the DMAinterface.The firmware writes to the DMA command register to start a DMA transfer (seeT able47).The command opcode determines whether a generic DMA or PIO transferwill start. The handler interfaces to the same FIFO (internal RAM) as used by theUSB core. On receiving the DMA command, the DMA handler directs the data fromthe endpoint FIFO to the external DMA device or from the external DMA device to theendpoint FIFO.The DMA interface configures the timing and the DMA handshake. Data can betransferred using either the DIOR and DIOW strobes or by the DACK and DREQhandshakes.The DMA configurations are set up by writing to the DMA Configurationregister (see T able52 and T able53).For a generic DMA interface, Generic DMA (GDMA) slave mode can be used.Remark:The DMA endpoint buffer length must be a multiple of 4bytes.For details on DMA registers, see Section9.4.8.2Hi-Speed USB transceiverThe analog transceiver directly interfaces to the USB cable through integratedtermination resistors. The high-speed transceiver requires an external resistor(12.0kΩ±1%) between pin RREF and ground to ensure an accurate current mirrorthat generates the Hi-Speed USB current drive.A full-speed transceiver is integrated as well. This makes the ISP1582 compliant to Hi-Speed USB and Original USB,supporting both the high-speed and full-speed physical layers.After automatic speed detection, the Philips Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling.8.3MMU and integrated RAMThe Memory Management Unit (MMU) and the integrated RAM provide theconversion between the USB speed (full-speed: 12Mbit/s, high-speed: 480Mbit/s)and the microcontroller handler or the DMA handler. The data from the USB bus isstored in the integrated RAM,which is cleared only when the microcontroller has read or written all data from or to the corresponding endpoint buffer or when the DMAhandler has read or written all data from or to the endpoint buffer.The OUT endpoint buffer can also be cleared forcibly by setting bit CLBUF in the Control Functionregister. A total of 8kbytes RAM is available for buffering.8.4Microcontroller interface and microcontroller handlerThe microcontroller handler allows the external microcontroller or microprocessor to access the register set in the Philips SIE as well as the DMA handler. Theinitialization of the DMA configuration is done through the microcontroller handler.8.5OTG SRP moduleThe OTG supplement defines a Session Request Protocol (SRP), which allows aB-device to request the A-device to turn on V BUS and start a session. This protocolallows the A-device,which may be battery-powered,to conserve power by turning off V BUS when there is no bus activity while still providing a means for the B-device toinitiate bus activity.Any A-device, including a PC or laptop, can respond to SRP. Any B-device, includinga standard USB peripheral, can initiate SRP.The ISP1582 is a device that can initiate SRP.8.6Philips high-speed transceiver8.6.1Philips Parallel Interface Engine (PIE)In the high-speed (HS) transceiver, the Philips PIE interface uses a 16-bit parallelbidirectional data interface.The functions of the HS module also include bit-stuffing or destuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.8.6.2Peripheral circuitT o maintain a constant current driver for HS transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an RREF resistor form thereference current. This circuit requires an external precision resistor (12.0kΩ±1%) connected to the analog ground.8.6.3HS detectionThe ISP1582 handles more than one electrical state—full-speed (FS) or high-speed (HS)—under the USB specification. When the USB cable is connected from theperipheral to the host controller, the ISP1582 defaults to the FS state until it sees abus reset from the host controller.During the bus reset, the peripheral initiates an HS chirp to detect whether the host controller supports Hi-Speed USB or Original USB. Chirping must be done with the pull-up resistor connected and the internal termination resistors disabled. If the HShandshake shows that there is an HS host connected, then the ISP1582 switches to the HS state.In the HS state, the ISP1582 should observe the bus for periodic activity. If the busremains inactive for 3ms, the peripheral switches to the FS state to check for aSingle-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected for the designated time (100µs to 875µs; refer to section 7.1.7.6 of the USBspecification Rev. 2.0), the ISP1582 switches to the HS chirp state to perform an HS detection handshake.Otherwise,the ISP1582remains in the FS state adhering to the bus-suspend specification.8.7Philips Serial Interface Engine (SIE)The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include:synchronization pattern recognition, parallel or serial conversion, bit (de)stuffing,CRC checking or generation, Packet IDentifier (PID) verification or generation,address recognition, handshake evaluation or generation.8.8SoftConnectThe connection to the USB is established by pulling pin DP (for full-speed devices)HIGH through a 1.5kΩ pull-up resistor. In the ISP1582, an external 1.5kΩ pull-upresistor must be connected between pin RPU and 3.3V. Pin RPU connects thepull-up resistor to pin DP,when bit SOFTCT in the Mode register is set(see Table20 and T able21). After a hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT=0). The USB bus reset does not change the value of bit SOFTCT.When the V BUS is not present, the SOFTCT bit must be set to logic0 to comply with the back-drive voltage.8.9System controllerThe system controller implements the USB power-down capabilities of the ISP1582.Registers are protected against data corruption during wake-up following a resume(from the suspend state) by locking the write access until an unlock code has beenwritten in the Unlock Device register (see Table73 and Table74).8.10Output pins statusT able3 illustrates the behavior of output pins when V CC(I/O) is supplied with V CC invarious operating conditions.Table 3:ISP1582 pin status[1]V CC V CC(I/O)State PinRESET_N INT_N SUSPEND DREQ DATA[15:0] 0V V CC dead[2]X X X X X0V V CC plug-out[3]X LOW HIGH high-Z input0V−>3.3V V CC plug-in[4]X LOW HIGH high-Z high-Z3.3V V CC reset LOW HIGH LOW high-Z high-Z3.3V V CC normal HIGH HIGH LOW high-Z high-Z[1]X: Don’t care.[2]Dead: The USB cable is plugged-out and V CC(I/O) is not available.[3]Plug-out: The USB cable is not present but V CC(I/O) is available.[4]Plug-in: The USB cable is being plugged-in and V CC(I/O) is available.8.11Interrupt8.11.1Interrupt output pinThe Interrupt Configuration register of the ISP1582 controls the behavior of the INToutput pin.The polarity and signaling mode of pin INT can be programmed by settingbits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); seeT able24. Bit GLINTENA of the Mode register (R/W: OCh) is used to enable pin INT.Default settings after reset are active LOW and level mode. When pulse mode isselected, a pulse of 60ns is generated when the OR-ed combination of all interruptbits changes from logic0 to logic1.Figure4 shows the relationship between the interrupt events and pin INT.Each of the indicated USB and DMA events is logged in a status bit of the Interruptregister and the DMA Interrupt Reason register, respectively. Corresponding bits inthe Interrupt Enable register and the DMA Interrupt Enable register determinewhether or not an event will generate an interrupt.Interrupts can be masked globally by means of bit GLINTENA of the Mode register;see T able21.Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generationof the INT signals for the control pipe. Field DDBGMODIN[1:0] of the InterruptConfiguration register controls the generation of the INT signals for the IN pipe.FieldDDBGMODOUT[1:0]of the Interrupt Configuration register controls the generation ofthe INT signals for the OUT pipe; see Table25.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxPhilips SemiconductorsISP1582Hi-Speed USB peripheral controller9397 750 13699© Koninklijke Philips Electronics N.V . 2004. All rights reserved.Preliminary data Rev. 03 — 25 August 200414 of 66Fig 4.Interrupt logic.ORInterrupt register DMA Interrupt ReasonregisterDMA Interrupt EnableregisterInterrupt Enable registerDMA_XFER_OKEXT_EOT INT_EOT IE_DMA_XFER_OK IE_EXT_EOTIE_INT_EOT ORIEBRESET IESOFIEDMAIEP7RX IEP7TXBRESET SOFDMAEP7RX EP7TX..............................004aaa275LATCHGLINTENA INTPOLLE Interrupt ConfigurationregisterMode registerINTPULSE/LEVEL GENERATOR8.11.2Interrupt controlBit GLINTENA in the Mode register is a global enable/disable bit.The behavior of this bit is given in Figure 5.Event A: When an interrupt event occurs (for example, SOF interrupt) withbit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will,however, be registered in the corresponding Interrupt register bit.Event B:When bit GLINTENA is set to logic 1,pin INT is asserted because bit SOF in the Interrupt register is already set.Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted.The bold dashed line shows the desired behavior of pin INT.Deassertion of pin INT can be achieved either by clearing all the Interrupt register or the DMA Interrupt Reason register, depending on the event.Remark:When clearing an interrupt event, perform write to all the bytes of the register.For more information on interrupt control, see Section 9.2.2,Section 9.2.5 and Section 9.5.1.8.12V BUS sensingPin V BUS is one of the ways to wake up the clock when the ISP1582 is suspended with bit CLKAON set to logic 0 (clock off option).T o detect whether the host is connected or not,that is V BUS sensing,a 1M Ωresistor and a 1µF electrolytic capacitor must be added to damp the overshoot upon plug-in.Pin INT: HIGH =deassert; LOW =assert (individual interrupts are enabled).Fig 5.Behavior of bit GLINTENA.INT pin004aaa394GLINTENA = 0SOF assertedGLINTENA = 1SOF assertedGLINTENA = 0(during this time,an interrupt event occurs. For example, SOF asserted.)AB CFig 6.Resistor and electrolytic capacitor needed for V BUS sensing.1 M ΩISP1582004aaa440+1 µF49USB Connector8.13Power-on resetThe ISP1582 requires a minimum pulse width of 500µs.Pin RESET_N can be either connected to V CC (using the internal POR circuit) or externally controlled (by the microcontroller, ASIC, and so on). When V CC is directly connected to pin RESET_N, the internal pulse width t PORP will be typically 200ns.The power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5on the V CC(POR) curve (Figure 9).t0 —The internal POR starts with a HIGH level.t1 —The detector will see the passing of the trip level and a delay element will add another t PORP before it drops to LOW.t2-t3 —The internal POR pulse will be generated whenever V CC(POR) drops below V trip for more than 11µs.t4-t5 —The dip is too short (<11µs) and the internal POR pulse will not react and will remain LOW.Figure 10 shows the availability of the clock with respect to the external POR.Fig 7.Oscilloscope reading:no resistorand capacitor in the network.Fig 8.Oscilloscope reading: withresistor and capacitor in the network.004aaa441004aaa442(1) PORP = power-on reset pulse.Fig 9.POR timing.004aaa389V BAT(POR)t0t1t2t3t4t5V triptPORPPORP (1)tPORP。