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D Wake-Up From Standby Mode in 6 µs D 16-Bit RISC Architecture,125-ns Instruction Cycle Time D 12-Bit A/D Converter With InternalReference, Sample-and-Hold and Autoscan FeatureD 16-Bit Timer_B With SevenCapture/Compare-With-Shadow Registers D 16-Bit Timer_A With Three Capture/Compare Registers D On-Chip ComparatorDSerial Onboard Programming,No External Programming Voltage Needed Programmable Code Protection by Security FuseDevicesDFamily Members Include:– MSP430F133:8KB+256B Flash Memory,256B RAM– MSP430F135:16KB+256B Flash Memory,512B RAM– MSP430F147:32KB+256B Flash Memory,1KB RAM– MSP430F148:48KB+256B Flash Memory,2KB RAM– MSP430F149:60KB+256B Flash Memory,2KB RAMD Available in 64-Pin Quad Flat Pack (QFP)DFor Complete Module Descriptions, See the MSP430x1xx Family User’s Guide ,Literature Number SLAU049descriptionThe Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.The MSP430x13x and the MSP430x14x series are microcontroller configurations with two built-in 16-bit timers,a fast 12-bit A/D converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution.Copyright 2000 – 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.pin designation, MSP430F133, MSP430F135171819P5.4/MCLK P5.3P5.2P5.1P5.0P4.7/TBCLK P4.6P4.5P4.4P4.3P4.2/TB2P4.1/TB1P4.0/TB0P3.7P3.6P3.5/URXD0484746454443424140393837363534332012345678910111213141516DV CC P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7V REF+XINXOUT/TCLKVe REF+V REF –/Ve REF –P1.0/TACLK P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21222324P 5.6/A C L K T D O /T D I 63626160596458A V P 6.2/A 2P 6.1/A 1P 6.0/A 0R S T /N M I T C K T M S P 2.6/A D C 12C L K P 2.7/T A 0P 3.0/S T E 0P 3.1/S I M O 0P 1.7/T A 2P 2.1/T A I N C L K P 2.2/C A O U T /T A 0P 2.3/C A 0/T A 1P 2.4/C A 1/T A 2P 2.5/R o s c 5655545725262728295352P 1.5/T A 0X T 2I N X T 2O U T 515049303132P 3.2/S O M I 0P 3.3/U C L K 0P 3.4/U T X D 0P 5.7/T B o u t HT D I P 5.5/S M C L KA V D V PM PACKAGE (TOP VIEW)P 1.6/T A 1P 2.0/A C L K C CS SS Spin designation, MSP430F147, MSP430F148, MSP430F149171819P5.4/MCLK P5.3/UCLK1P5.2/SOMI1P5.1/SIMO1P5.0/STE1P4.7/TBCLK P4.6/TB6P4.5/TB5P4.4/TB4P4.3/TB3P4.2/TB2P4.1/TB1P4.0/TB0P3.7/URXD1P3.6/UTXD1P3.5/URXD0484746454443424140393837363534332012345678910111213141516DV CC P6.3/A3P6.4/A4P6.5/A5P6.6/A6P6.7/A7V REF+XINXOUT/TCLKVe REF+V REF –/Ve REF –P1.0/TACLK P1.1/TA0P1.2/TA1P1.3/TA2P1.4/SMCLK21222324P 5.6/A C L K T D O /T D I 63626160596458A V P 6.2/A 2P 6.1/A 1P 6.0/A 0R S T /N M I T C K T M S P 2.6/A D C 12C L K P 2.7/T A 0P 3.0/S T E 0P 3.1/S I M O 0P 1.7/T A 2P 2.1/T A I N C L K P 2.2/C A O U T /T A 0P 2.3/C A 0/T A 1P 2.4/C A 1/T A 2P 2.5/R o s c 5655545725262728295352P 1.5/T A 0X T 2I N X T 2O U T 515049303132P 3.2/S O M I 0P 3.3/U C L K 0P 3.4/U T X D 0P 5.7/T B o u t HT D I P 5.5/S M C L KA V D V PM PACKAGE (TOP VIEW)P 1.6/T A 1P 2.0/A C L K C CS SS Sfunctional block diagrams MSP430x13xRoscXT2INXT2OUTTMSTCKTDITDO/TDIMSP430x14xRoscXT2INXT2OUTTMSTCKTDITDO/TDITerminal FunctionsTerminal Functions (Continued)General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R12R13General-Purpose Register General-Purpose Register R6R7General-Purpose Register General-Purpose Register R8R9General-Purpose Register General-Purpose Register R10R11General-Purpose Register General-Purpose RegisterR14R15short-form descriptionCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions,are performed as register operations in conjunc-tion with seven addressing modes for source operand and four addressing modes for destina-tion operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register,and constant generator respectively. The remain-ing registers are general-purpose registers.Peripherals are connected to the CPU using data,address, and control buses, and can be handled with all instructions.instruction setThe instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.Table 1. Instruction Word FormatsTable 2. Address Mode Descriptionsoperating modesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.The following six operating modes can be configured by software:D Active mode AM;–All clocks are activeD Low-power mode 0 (LPM0);–CPU is disabledACLK and SMCLK remain active. MCLK is disabledD Low-power mode 1 (LPM1);–CPU is disabledACLK and SMCLK remain active. MCLK is disabledDCO’s dc-generator is disabled if DCO not used in active modeD Low-power mode 2 (LPM2);–CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator remains enabledACLK remains activeD Low-power mode 3 (LPM3);–CPU is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledACLK remains activeD Low-power mode 4 (LPM4);–CPU is disabledACLK is disabledMCLK and SMCLK are disabledDCO’s dc-generator is disabledCrystal oscillator is stoppedinterrupt vector addressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.2.Interrupt flags are located in the module.3.Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.4.(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disableit.5.Timer_B7 in MSP430x14x family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interruptflags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.special function registersMost interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.interrupt enable 1 and 2Address 0hWDTIE:Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.OFIE:Oscillator-fault-interrupt enable NMIIE:Nonmaskable-interrupt enable ACCVIE:Flash access violation interrupt enableURXIE0:USART0, UART, and SPI receive-interrupt enable UTXIE0:USART0, UART, and SPI transmit-interrupt enablerw-0rw-0Address 01hURXIE1:USART1, UART, and SPI receive-interrupt enable UTXIE1:USART1, UART, and SPI transmit-interrupt enableinterrupt flag register 1 and 2Address 02hWDTIFG:Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V CC OFIFG:Flag set on oscillator fault NMIIFG:Set via RST/NMI pinURXIFG0:USART0, UART, and SPI receive flag UTXIFG0:USART0, UART, and SPI transmit flagrw-1rw-0Address 03hURXIFG1:USART1, UART, and SPI receive flag UTXIFG1:USART1, UART, and SPI transmit flagmodule enable registers 1 and 2rw-0rw-0Address 04hURXE0:USART0, UART receive enable UTXE0:USART0, UART transmit enableUSPIE0:USART0, SPI (synchronous peripheral interface) transmit and receive enablerw-0rw-0Address 05hURXE1:USART1, UART receive enable UTXE1:USART1, UART transmit enableUSPIE1:USART1, SPI (synchronous peripheral interface) transmit and receive enableLegend: rw:Bit Can Be Read and WrittenBit Can Be Read and Written. It Is Reset by PUC.SFR Bit Not Present in Devicememory organizationbootstrap loader (BSL)The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430Bootstrap Loader , Literature Number SLAA089.flash memoryThe flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128bytes each. Each segment in main memory is 512 bytes in size.D Segments 0 to n may be erased in one step, or each segment may be individually erased.D Segments A and B can be erased individually, or as a group with segments 0–n.Segments A and B are also called information memory.D New devices may have some bytes programmed in the information memory (needed for test duringmanufacturing). The user should perform an erase of the information memory prior to the first use.Main MemoryInformation Memory8 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh16 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh32 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh48 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh60 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh0E400h 0E3FFh 0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h01400h 013FFh01200h 011FFh01100h 010FFh01080h 0107Fh01000hperipheralsPeripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions.digital I/OThere are six 8-bit I/O ports implemented—ports P1 through P6:D All individual I/O bits are independently programmable.D Any combination of input, output, and interrupt conditions is possible.D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.D Read/write access to port-control registers is supported by all instructions.oscillator and system clockThe clock system in the MSP430x13x and MSP43x14x family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) anda high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both lowsystem cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals:D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.D Main clock (MCLK), the system clock used by the CPU.D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.watchdog timerThe primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.multiplication (MSP430x14x Only)The multiplication operation is supported by a dedicated peripheral module. The module performs 1616, 168, 816, and 88 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.USART0The MSP430x13x and the MSP430x14x have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.USART1 (MSP430x14x Only)The MSP430x14x has a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.Operation of USART1 is identical to USART0.timer_A3Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B7 (MSP430x14x Only)Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.timer_B3 (MSP430x13x Only)Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.comparator_AThe primary function of the comparator_A module is to support precision slope analog–to–digital conversions, battery–voltage supervision, and monitoring of external analog signals.ADC12The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.peripheral file mapperipheral file map (continued)peripheral file map (continued)peripheral file map (continued)absolute maximum ratings over operating free-air temperature (unless otherwise noted)†. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage applied at V CC to V SS–0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage applied to any pin (referenced to V SS) –0.3 V to V CC+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage temperature (unprogrammed device) –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage temperature (programmed device) –40°C to 85°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE:All voltages referenced to V SS.recommended operating conditionsNOTES: 1.In LF mode, the LFXT1 oscillator requires a watch crystal and the LFXT1 oscillator requires a 5.1-M Ω resistor from XOUT to V SS when V CC <2.5 V. In XT1 mode, the LFXT1. and XT2 oscillators accept a ceramic resonator or a 4-MHz crystal frequency at V CC ≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or an 8-MHz crystal frequency at V CC ≥ 2.8V.2.In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, FXT1 accepts a ceramic resonator or a crystal.3.The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if segment write option is used.4.The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cummulative mass erase time needed is 200 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of 19 cycles may be required).f (MHz)8.0 MHzSupply Voltage – V’F13x/’F14x,Figure 1. Frequency vs Supply Voltage, MSP430F13x or MSP430F14xelectrical characteristics over recommended operating free-air temperature (unless otherwise noted)+ DV excluding external currentsupply current into AVCC2.Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to V CC. Outputs do not source or sink any current. The currentconsumption in LPM2 and LPM3 are measured with ACLK selected.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)Current consumption of active mode versus system frequency, F-versionI(AM) = I(AM) [1 MHz]× f(System) [MHz]Current consumption of active mode versus supply voltage, F-versionI(AM) = I(AM)[3V]+ 175 µA/V × (V CC– 3 V)SCHMITT-trigger inputs – Ports P1, P2, P3, P4, P5, and P6standard inputs – RST/NMI; JTAG: TCK, TMS, TDI, TDO/TDIOH(max)OL(max),specified voltage drop.2.The maximum total current, I OH(max) and I OL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximumspecified voltage drop.outputs – Ports P1, P2, P3, P4, P5, and P6 (continued)Figure 2V OL – Low-Level Output Voltage – V 02468101214160.00.5 1.0 1.5 2.0 2.5TYPICAL LOW-LEVEL OUTPUT CURRENTvsLOW-LEVEL OUTPUT VOLTAGEO L I – L o w -L e v e l O u t p u t C u r r e n t – m AFigure 3V OL – Low-Level Output Voltage – V05101520250.00.5 1.0 1.5 2.0 2.5 3.03.5TYPICAL LOW-LEVEL OUTPUT CURRENTvsLOW-LEVEL OUTPUT VOLTAGEO L I – L o w -L e v e l O u t p u t C u r r e n t – m AFigure 4V OH – High-Level Output Voltage – V–14–12–10–8–6–4–200.00.51.01.52.02.5TYPICAL HIGH-LEVEL OUTPUT CURRENTvsHIGH-LEVEL OUTPUT VOLTAGEO H I – H i g h -L e v e l O u t p u t C u r r e n t – m AFigure 5V OH – High-Level Output Voltage – V–30–25–20–15–10–50.00.5 1.0 1.5 2.0 2.5 3.03.5TYPICAL HIGH-LEVEL OUTPUT CURRENTvsHIGH-LEVEL OUTPUT VOLTAGEO H I – H i g h -L e v e l O u t p u t C u r r e n t – m Aelectrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)output frequencyfrequencies can be different.(int)trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles.2.The external capture signal triggers the capture event every time the minimum t(cap) cycle and time parameters are met. A capturemay be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set.3.Seven capture/compare registers in ’x14x and three capture/compare registers in ’x13x.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)leakage current (see Note 1)SS CC 2.The port pin must be selected as input and there must be no optional pullup or pulldown resistor.should take place during this supply voltage condition.lkg(Px.x)2.The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.The two successive measurements are then summed together.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)T A – Free-Air Temperature – °C 400450500550600650–45–25–51535557595Figure 6. V (RefVT) vs Temperature, V CC = 3 VV (R E F V T )– R e f e r e n c e V o l t s –m VFigure 7. V (RefVT) vs Temperature, V CC = 2.2 VT A – Free-Air Temperature – °C400450500550600650–45–25–51535557595V (R E F V T )– R e f e r e n c e V o l t s –m VV+τ ≈ 2.0 µsTo Internal ModulesSet CAIFG FlagCAOUT V –Figure 8. Block Diagram of Comparator_A ModuleV Figure 9. Overdrive Definitionelectrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)PORVVVFigure 10. Power-On Reset (POR) vs Supply Voltage1.20.800.20.40.60.811.21.41.61.82–40–2020406080T A – Temperature – °CV P O R – VFigure 11. V POR vs Temperatureelectrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)DCO (see Note 1)(System)2.This parameter is not production tested.f DCO_0f DCO_7–F r e q u e n c y V a r i a n c eFigure 12. DCO Characteristicselectrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)main DCO characteristicsD Individual devices have a minimum and maximum operation frequency. The specified parameters forf DCOx0 to f DCOx7 are valid for all devices.D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps withRsel7.D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S DCO.D Modulation control bits MOD0 to MOD4 select how often f DCO+1 is used within the period of 32 DCOCLKcycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to f(DCO) × (2MOD/32 ).(t) URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(t). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)12-bit ADC, power supply and input range conditions (see Note 1)‡Not production tested, limits verified by designNOTES: 1.The leakage current is defined in the leakage current table with P6.x/Ax parameter.2.The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reducedaccuracy requirements.3.The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reducedaccuracy requirements.4.The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied withreduced accuracy requirements.5.The analog input voltage range must be within the selected reference voltage range V R+ to V R– for valid conversion results.6.The internal reference supply current is not included in current consumption parameter I ADC12.7.The internal reference current is supplied via terminal AV CC. Consumption is independent of the ADC12ON control bit, unless aconversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)12-bit ADC, built-in reference (see Note 1)‡Not production tested, limits verified by designNOTES: 1.The voltage source on V eREF+ and V REF–/V eREF–) needs to have low dynamic impedance for 12-bit accuracy to allow the charge to settle for this accuracy.2.The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance shouldfollow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.3.The internal buffer operational amplifier and the accuracy specifications require an external capacitor.4.The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the referencesupply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. All INL and D NL t ests u ses t wo c apacitors b etween p ins V REF+a nd A V SS a nd V REF–/V eREF–a nd A V SS: 10 µF t antalum a nd 100nF c eramic.electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)12-bit ADC, timing parameters‡Not production tested, limits verified by designNOTES: 1.The condition is that the error in a conversion started after t REF(ON) is less than ±0.5 LSB. The settling time depends on the externalcapacitive load.2.The condition is that the error in a conversion started after t ADC12ON is less than ±0.5 LSB. The reference and input signal are alreadysettled.3.Ten Tau (τ) are needed to get an error of less than ±0.5 LSB. t Sample = 10 x (Ri + Zi) x Ci+ 800 nsC 1 µ in µF100 µ10 µFigure 13. Typical Settling Time of Internal Reference t REF(ON) vs External Capacitor on V REF +electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)12-bit ADC, linearity parameters。
MSP430系列单片机简介MSP430系列单片机是美国德州仪器(TI)推向市场的一个16位、具有精简指令集、超低功耗的混合型单片机，自1996年问世，由于它具有极低的功耗、丰富的片内外设备和方便灵活的开发手段，成为许多电子产品设计的首选，1999年进入中国就受到了中国广大设计工程师的青睐。
目前，该系列单片机不仅在电子工程、测控技术与仪器、自动控制、机电一体化等方面得到广泛应用，而且逐渐走进校园，被越来越多的使用在硕士研究生和高年级本科生的科技实践和毕业设计中，在2005年暑期全国大学生电子设计竞赛中就选用了该系列的单片机[5]。
MSP430系列单片机的型号很多，TI公司用3或4位数字表示单片机型号，其中一位数字表示一个系列。
目前有四大系列：带有液晶驱动的MSP430F4xx 系列单片机、不带液晶驱动器的MSP430F1xx系列单片机、16MIPS高速MSP430F2xx系列单片机、一次性写入（OTP）型低价MSP430C系列单片机，每个系列中又含有许多子系列。
单片机型号的第二位数字表示子系列号，一般子系列号越大包含的功能模块越多，最后一或两位数字表示存储器容量，数字越大表示ROM和RAM的容量越大。
此外，MSP430系列单片机还针对许多热门应用设计了一系列专用单片机，如水表专用单片机、医疗仪器专用单片机，电能计量专用单片机，这些单片机都是在相同型号的通用单片机的基础上增加专用模块构成的[5]。
MSP430F449单片机的主要性能有：●低供电电压范围：1.8V-3.6V及欠电压检测器●超低功耗，具有五种省电模式：活动模式：1MHz，2.2V时为280uA；等待模式：1.6uA；关闭模式（RAM保持）：0.1uA●数字控制的振荡器（DCO）可以在6us内将CPU从休眠中唤醒，这也是实现低功耗的重要手段之一●16位精简指令结构，125ns指令时间周期，10个16位的寄存器以及常数发生器，能够最大限度的提高代码的效率●具有内部参考电平，采样保持和自动扫描的12位A/D转换器●带有三个或七个捕捉/比较影子寄存器的16位定时器B●带有三个捕捉/比较寄存器的16位定时器A● 串行通讯接口（USART ），软件选择异步UART 或者同步SPI 接口，对于MSP430F44x 系列的单片机有两个UART （UART0，UART1）● 可编程电平检测的供电电压管理器/监视器● 串行在线编程无需外部编程电压，可编程的安全熔丝代码保护● 集成多达160段的LCD 驱动器如图2.1所示为MSP430F449单片机的引脚图。
