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CS5530-ISZ;CS5530-ISZR;CDB5530U;中文规格书,Datasheet资料

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Copyright Cirrus Logic, Inc. 2009CS553024-bit ADC with Ultra-low-noise AmplifierFeatures & Description❑Chopper-stabilized Instrumentation Amplifier, 64X• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)• 1200pA Input Current❑Digital Gain Scaling up to 40x❑Delta-sigma Analog-to-digital Converter • Linearity Error: 0.0015% FS• Noise Free Resolution: Up to 19 bits❑Scalable V REF Input: Up to Analog Supply ❑Simple Three-wire Serial Interface• SPI™ and Microwire™ Compatible• Schmitt-trigger on Serial Clock (SCLK)❑Onboard Offset and Gain Calibration Registers❑Selectable Word Rates: 6.25 to 3,840 Sps ❑Selectable 50 or 60 Hz Rejection❑Power Supply Configurations• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V• VA+ = +3 V; VA- = -3 V; VD+ = +3 V General DescriptionThe CS5530 is a highly integrated ΔΣ Analog-to-Digital Converter (ADC) which uses charge-balance techniques to achieve 24-bit performance. The ADC is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADC includes a very-low-noise, chopper-stabilized instrumentation amplifier (12nV/√Hz@0.1Hz) with a gain of 64X. This device also includes a fourth-order ΔΣ modulator fol-lowed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK=4.9152MHz).To ease communication between the ADC and a micro-controller, the converter includes a simple three-wire se-rial interface which is SPI and Microwire compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options make this device an ideal solution for weigh scale and process control applications.ORDERING INFORMATIONSee page35.VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ΔΣMODULATOR PROGRAMMABLE SINC FIR FILTERAIN1+AIN1-SERIALINTERFACELATCHCLOCKGENERATOR CALIBRATIONSRAM/CONTROLLOGICDGNDCSSDISDOSCLKOSC2OSC1A1A0VA-64XNOV ‘09TABLE OF CONTENTS 1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL NOISE-FREE RESOLUTION (BITS) (6)5 V DIGITAL CHARACTERISTICS (7)3 V DIGITAL CHARACTERISTICS (7)DYNAMIC CHARACTERISTICS (8)ABSOLUTE MAXIMUM RATINGS (8)SWITCHING CHARACTERISTICS (9)2.GENERAL DESCRIPTION (11)2.1.Analog Input (11)2.1.1. Analog Input Span (12)2.1.2. Voltage Noise Density Performance (12)2.1.3. No Offset DAC (12)2.2.Overview of ADC Register Structure and Operating Modes (12)2.2.1. System Initialization (12)2.2.2. Command Register Descriptions (14)2.2.3. Serial Port Interface (16)2.2.4. Reading/Writing On-Chip Registers (17)2.3.Configuration Register (17)2.3.1. Power Consumption (17)2.3.2. System Reset Sequence (17)2.3.3. Input Short (17)2.3.4. Voltage Reference Select (17)2.3.5. Output Latch Pins (18)2.3.6. Filter Rate Select (18)2.3.7. Word Rate Select (18)2.3.8. Unipolar/Bipolar Select (18)2.3.9. Open Circuit Detect (18)2.3.10. Configuration Register Description (19)2.4.Calibration (21)2.4.1. Calibration Registers (21)2.4.2. Gain Register (21)2.4.3. Offset Register (21)2.4.4. Performing Calibrations (22)2.4.5. System Calibration (22)2.4.6. Calibration Tips (22)2.4.7. Limitations in Calibration Range (23)2.5.Performing Conversions (23)2.5.1. Single Conversion Mode (23)2.5.2. Continuous Conversion Mode (24)ing Multiple ADCs Synchronously (25)2.7.Conversion Output Coding (25)2.7.1. Conversion Data Output Descriptions (26)2.8.Digital Filter (27)2.9.Clock Generator (28)2.10.Power Supply Arrangements (28)2.11.Getting Started (31)2.12.PCB Layout (31)3.PIN DESCRIPTIONS (32)Clock Generator (32)Control Pins and Serial Data I/O (32)Measurement and Reference Inputs (33)Power Supply Connections (33)4.SPECIFICATION DEFINITIONS (33)5.PACKAGE DRAWINGS (34)6.ORDERING INFORMATION (35)7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (35)LIST OF FIGURES Figure 1. SDI Write Timing (Not to Scale) (10)Figure 2. SDO Read Timing (Not to Scale) (10)Figure 3. Front End Configuration (11)Figure 4. Input Model for AIN+ and AIN- Pins (11)Figure 5. Measured Voltage Noise Density (12)Figure 5. Measured Voltage Noise Density (12)Figure 6. CS5530 Register Diagram (13)Figure 7. Command and Data Word Timing (16)Figure 8. Input Reference Model when VRS = 1 (18)Figure 9. Input Reference Model when VRS = 0 (18)Figure 10. System Calibration of Offset (22)Figure 11. System Calibration of Gain (22)Figure 12. Synchronizing Multiple ADCs (25)Figure 13. Digital Filter Response (Word Rate = 60 Sps) (27)Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz (27)Figure 15. 120 Sps Filter Phase Plot to 120 Hz (27)Figure 16. Z-Transforms of Digital Filters (27)Figure 17. On-chip Oscillator Model (28)Figure 18. CS5530 Configured with a Single +5 V Supply (29)Figure 19. CS5530 Configured with ±2.5 V Analog Supplies (29)Figure 20. CS5530 Configured with ±3 V Analog Supplies (30)LIST OF TABLES Table 1. Conversion Timing for Single Mode (24)Table 2. Conversion Timing for Continuous Mode (24)Table 3. Output Coding (25)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARCTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C to +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3.This specification applies to the device only and does not include any effects by external parasiticthermocouples.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterCS5530-CSUnit Min Typ Max Accuracy Linearity Error -±0.0015±0.003%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset -±32±64LSB 24Offset Drift(Notes 3 and 4)-10-nV/°C Bipolar full-scale Error -±8±31ppm Unipolar full-scale Error -±16±62ppm full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.See the section of the data sheet which discusses input models.6.Input current on VREF+ or VREF- may increase to 250nA if operated within 50mV of VA+ or VA-. Thisis due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode (VA-) + 1.6-(VA+) - 1.6VCVF Current on AIN+ or AIN--1200-pAInput Current Noise -1-pA/√HzOpen Circuit Detect Current 100300-nACommon Mode Rejection DC 50, 60 Hz --130120--dBdBInput Capacitance -10-pF Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 5, 6)-50-nA Common Mode Rejection DC 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)7.All outputs unloaded. All input CMOS levels.8.Tested with 100 mV change on VA+ or VA-.TYPICAL NOISE-FREE RESOLUTION (BITS) (See Notes 9 and 10)9.Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the Noise Free Resolution accordingly.10.“Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on theRMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.ParameterCS5530-CSMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 60.681.0mA mA Power ConsumptionNormal Mode (Note 7)Standby Sleep---35550045--mW mW µW Power Supply Rejection (Note 8)DC Positive Supplies DC Negative Supply--115115--dB dBOutput Word Rate (Sps)-3 dB Filter Frequency (Hz)Noise-free BitsNoise (nV rms )7.5 1.94191715 3.881924307.7518346015.51848120311768240621611548012216163960230152291,920390153443,8407801313905 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND =0 V; See Notes 2 and 11.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND =0V; See Notes 2 and 11.)11.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-Level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-Level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS12.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.13.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.14.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full-scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 15.)Notes:15.All voltages with respect to ground.16.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.17.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.18.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.19.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.20.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (full-scale Step Input)Single Conversion mode (Notes 12, 13, and 14)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 16 and 17)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 18 and 19)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 20)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:21.Device parameters are specified with a 4.9152 MHz clock.22.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.23.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 21)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 22)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 22)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 23)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150nsFigure 1. SDI Write Timing (Not to Scale)Figure 2. SDO Read Timing (Not to Scale)分销商库存信息:CIRRUS-LOGICCS5530-ISZ CS5530-ISZR CDB5530U。

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DS2250微处理器产品说明书

DS2250微处理器产品说明书

Printed in U.S.A.TABLE OF CONTENTSPageSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1CONNECTOR CHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1CIRCUIT ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1DS2250 MICROPROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1DUAL PORT RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ON BOARD RAM U12 AND U13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2LOAD/RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2RS-232 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2BIT I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2LED INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3PROGRAMMING INSTRUCTIONSLOADING 344A4414G1 SOFTWARE INTO THE GETC 1e MODULE . . . . . . . . . . . . . . . . . 3REQUIRED ITEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3LOADING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3SERIAL NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4IC DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5HARNESS ASSEMBLY DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7INSTALLATION INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7OUTLINE DIAGRAMS:HARNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8GETC 1e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8SCHEMATIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9MAINTENANCE MANUAL GE TRUNKING CARD 1e19D903536P1LBI-38822ACIRCUIT ANALYSISBLOCK DIAGRAMThe 1e module consists of two almost independent microprocessor (µP) sections (See Figure 2). The heart of each section is a DS2250 microprocessor, U1 or U2. In addition to its internal memory, each µP has a 32K byte external RAM, U12 or U13. Each section also contains a 4K byte dual port RAM (DPR), U3 or U4, which provides the interface to the GETC. A single oscillator, U14 provides clock for both processors. Each processor has a serial port which is converted to RS-232 by U8. Indicator LED’s D1 and D2 are activated by one-shots in U9 as long as they are triggered by the associated processor. A single input bit and a single output bit are available on each processor for I/O. The module has a single RESET button which resets both processors. LOAD/RUN circuits on each processor set op-erating mode. Port 1 and INT0 of both processors are tied together to provide a high speed parallel communication link between the two processors.DS2250 MICROPROCESSORThe microprocessor is a Dallas Semiconductor proprie-tary derivative of the Intel 8031. This special version proc-essor has internal circuitry for a bootstrap loader, terminal interface and internal control of 64K bytes of battery backed up RAM. The RAM can be partitioned into separate code and data spaces, with the code space write protected after code is loaded. An internal bit ECE2 under program control alters the memory map allowing access to all available memory.DUAL PORT RAMU3 and U4 provide the interface to the GETC 8032 processor. The GETC sees U3 and U4 as a single 8K byte memory block, addressed from 0 to 1FFFH. U1 sees U3 on its opposite port as a 4K byte RAM addressed from 0 to 0FFFH and likewise, U2 sees U4 as a 4K byte RAM ad-dressed from 0 to 0FFFH. Thus each 1e processor shares 4K bytes of memory space with the GETC processor, allowing efficient exchange of data. U11-D and U10-D drive the output enable (read) input from the GETC. U10-A, B, and C and U11-A and B drive DPR chip enables from the GETC.Copyright© January 1993, Ericsson GE Mobile Communications Inc.SPECIFICATIONSCurrent Drain80 to 120 ma.Supply Voltage 4.75VDC to 5.25VDCMemory Provided (bytes)64K on board, not backed up.128K in the DS2250’s, battery backed up.8K Dual PortRS-232 Serial Ports2I/O 2 bits input - Diode protected, weakly pulled upinverted before processor2 bits output - Transistor buffered, weakly pulled upopen collector.Oscillator frequency 1.0592 MHzIndicators One RED LED controlled by each DS2250 Dimensions 3.00in. x 7.75in. (board)INTRODUCTIONThe GETC 1e (expansion) module (19D903536P1) pro-vides additional processing power and memory for the G eneral E ectric T runking C ard (GETC) which will allow software growth, and expanded features for the E nhanced D igital A c-cess C ommunication S ystem (EDACS™). The 1e module is supplied standard with EDACS station GETC’s, Downlink GETC’s, CNI GETC’s, SCAT GETC’s, EDACS Site Control-ler GETC’s, Simulcast Control GETC’s, and EDACS Satellite Receiver GETC’s beginning in January 1993. The 1e module is not required, but is compatible with all previous hardware and software releases.The 1e module uses mostly surface mount components and mounts on spacers above the GETC. Electrical connections to the GETC are made by removing U3 from the GETC and plugging the 1e modules 28 pin ribbon cable and connector P1 into the GETC’s socket XU3. A small shield above the 1e module protects it from damage when sliding the GETC drawer in and out.CONNECTOR CHARTConnector DescriptionP11e module interface to the GETCaddress/data bus and powerJ1Allow serial interface to U2 at TTLlevelsJ2RS-232 serial interface to U1J3RS-232 serial interface to U2J4I/O on U1J5I/O on U2Figure 1 - Memory Map For Each DS2250MEMORY MAPLBI-38822LBI-388221ON BOARD RAM U12 AND U13When ECE2 is 0, each processor accesses a 32K RAM at address 8000H to 0FFFFH. These RAM’s are on the 1e module board, not on the DS2250, thus they are not backed up by the DS2250 battery. This memory space is used as temporary scratch pad by the processors. U10-E and U10-F drive the RAM CE (chip enable) pin from bit 15 of the address bus. A low enables the RAM.OSCILLATORU14 is an unbuffered CMOS inverter (HCU04). Here, U14-A functions as a linear gain stage with crystal Y1 in its feedback, forming an oscillator at 11.0592 MHz. U14-B buff-ers the clock and drives both processors.RESETSwitch S1 resets the 1e module and S4 on the GETC resets the GETC. Software will usually start properly with only a GETC reset, however resetting both will work.Depressing switch S1 grounds R21 and R22 and the posi-tive side of C21. This turns on PNP transistors Q4 and Q7 which pulls the RESET input of each processor high, holding them in the RESET condition. When S1 is released, the voltage at C21+ (and Q4 and Q7 bases) slowly rises as C21 charges through R8 and R15. Eventually this voltage rises high enough so Q4 and Q7 turn off and the processor RESET inputs fall low and are held low by R7 and R14. R8 and R15 hold Q4 and Q7 off.LOAD/RUN CIRCUITIn normal RUN mode, the processors RESET input is held low and PSEN is an output which controls external memory. The DS2250 is put into LOAD mode by holding the RESET pin high and the PSEN pin low.Switch S2 controls RUN/LOAD for processor U1. When S2 is down (toward S1) (shorting pins 2 and 3) U1 is in LOAD mode. VCC (5V) is applied to R10 and R12. This turns on Q8 which turns on Q7 through R9 thus pulling U1’s RESET high. VCC on R12 turns on Q6 which holds PSEN low. When S2 is up (shorting pins 1 and 2) the processor is in RUN mode. VCC is not applied to R10 and R12. Q8 is held off by R11 and Q7is held off by R8 so RESET is pulled low by R7. Q6 is held off by R13 so PSEN is not held low and may become an output of U1.Switch S3 controls RUN/LOAD for processor U2. When S3 is down (shorting pins 2 and 3) U2 is in LOAD mode. VCC (5V) is applied to R17 and R19. This turns on Q5 which turns on Q4 through R16 thus pulling U2’s RESET high. VCC on R19 turns on Q3 which holds PSEN low. When S3 is up (shorting pins 1 and 2) the processor is in RUN mode. VCC is not applied to R17 and R19. Q5 is held off by R18 and Q4 is held off by R15 so RESET is pulled low by R14. Q3 is held off by R20 so PSEN is not held low and may become an output of U2.RS-232 INTERFACEThe RS-232 interfaces are used to program the DS2250 modules and to interface to other serial devices (future appli-cations). An Intel Hex format file from a PC can be loaded into memory via the serial ports. Complete instructions will accom-pany software loaded in the field.U8 is a dual TTL to RS-232 duplex serial interface. Ca-pacitors C1, C2, C3, and C4 are used by U8 to convert 5V to RS-232 levels. Section 1 converts U1’s serial port to RS-232 and section 2 converts U2’s serial port to RS-232. Serial output for U1 is J2-1 and input is J2-2. Serial output for U2 is J3-1 and input is J3-2. J1 is inserted in the RXD line of U2 to allow interfacing to U2’s serial port at TTL levels.BIT I/OOne output bit from U1 is available. It is buffered by Q9 and drives out on J4-2. Weak pullup R30 holds J4-2 high when Q9 is turned off by U1. One input bit to U1 is available. It is buffered by U15-A and protected from static and overdrive by D3 and R27. Weak pullup R35 holds the input high when not in use.One output bit from U2 is available. It is buffered by Q10 and drives out on J5-2. Weak pullup R32 holds J5-2 high when Q9 is turned off by U1. One input bit to U2 is available. It is buffered by U15-B and protected from static and overdrive by D4 and R31. Weak pullup R36 holds the input high when notin use.Figure 2 - GETC 1e Block DiagramLBI-38822LBI-38822 2LED INDICATORSLED D1 is controlled by processor U1. The processor must apply pulses to retriggerable one-shot U9-A, pin 4, about every half second or faster to keep the light on. It is used as a visual indication that the software is running. The pulse on U9-4 retriggers the output on U9-6 keeping Q1 on and LED D1 on. If the pulses don’t appear in time, the one-shot times out and U9-6 falls low turning off Q1 and D1. R1 and C17 determine the drop out time.LED D2 is controlled by processor U2. The processor must apply pulses to retriggerable one-shot U9-B, pin 12, about every half second or faster to keep the light on. It is used as a visual indication that the software is running. The pulse on U9-12 retriggers the output on U9-10 keeping Q2 on and LED D2 on. If the pulses don’t appear in time, the one-shot times out and U9-10 falls low turning off Q2 and D2. R4 and C18 determine the drop out time.TROUBLESHOOTINGVery little troubleshooting is possible in the field. Prob-lems may be traced to the 1e module by substituting another 1e module. If it is not known that the substitute module has correct software, either load correct software into it or take the DS2250 modules out of the suspect 1e and put them into the new 1e. If DS2250 modules are substituted, be sure to put U1 from the old 1e into XU1 of the new 1e and likewise for U2. The two processors will generally contain different software.If problems can be traced to the 1e module, here are some things to look for. Visually check for damaged parts, un-soldered pins or parts, broken cable or pins (P1), or unseated DS2250 modules. Look for trash in the SIMM sockets. A magnifying glass or low power microscope is helpful. Make sure S2 and S3 are positioned toward the rear of the GETC in the RUN condition. Make sure the jumper is on J1-1 to 2. Check for 5V 0.25V at C5+. With a high speed, high impedance scope, check for oscillations at U14-4. A somewhat flattened sine wave of about 4V amplitude at 11.0592 Mhz will be seen.PROGRAMMING INSTRUCTIONSLOADING 344A4414G1 SOFTWARE INTOTHE GETC 1e MODULEREQUIRED ITEMS•IBM compatible PC, monitor and keyboard with atleast 640K memory,•Hard disk (recommended but not required) and serialport (COM1)•TQ-3360 programming cable•DB-25 male to DB-9 female adapter or cable (neededif PC COM1 connector is DB-9 male instead of DB-25 male)•Software Distribution diskette 344A4414G1PREPARATIONBefore loading can begin, the files listed below must existon the PC used as the loader. Create a new directory, forinstance, "LOAD1e" with the command "MKDIRLOAD1E". Then change into that directory and copy thefollowing files from the distribution diskette.load1e.exe1etop.hex1ebot.hex1ecrc.hexAlways change to this directory before loading softwareto 1e modules.The executable file "load1e.exe" loads the file"1etop.hex" into the top processor on the 1e module. Thisprocessor is physically in the rear as viewed from the front ofthe GETC and it accesses the top half of GETC RAM memoryspace (1000-1FFF). It is loaded through J2 and J104. Then"load1e.exe" loads file "1ebot.hex" into the bottom proces-sor on the 1e module. This processor is physically in the front,accesses the bottom half of GETC memory (0-FFF) and isserially loaded through J3 and J103. The loader uses file"1ecrc.hex" to check that the file was loaded correctly.This procedure assumes loading will occur after the iemodule is mounted in a GETC and installed in an EDACSstation.LOADING PROCEDURE1.Connect loader cable TQ-3360 from COM1 on thePC to J104 at rear of GETC. A DB-25 male to DB-9female adapter or cable may be required.2.Move S2 and S3 on the 1e module toward the front.If either switch is already positioned to the front,move it to the rear and then back to the front.3.Execute program LOAD1E and follow its instruc-tions. You will be kept informed of execution steps.After the top processor is loaded, move the program-ming cable to J103, then hit a key to load the bottomprocessor.4.When both processors are loaded correctly, thescreen will say "FINISHED - SWITCH S2 AND S3TO THE REAR". Do so and D1 and D2 shouldcome on to indicate code is executing. Unplug theprogramming cable.ERRORSErrors usually mean communications have been lostbetween the PC and the 1e module. If errors occur, checkcables, plugs, and move S2 and S3 to the rear then backtoward the front.Error 1 Did not receive signon banner from DS-2250.Error 2 Did not receive CR-LF from DS-2250.Error 3 Did not receive prompt from DS-2250.Error 4 Did not receive CRC value from DS-2250.Error 5 Did not receive serial number from DS-2250."Cannot open COM1" - COM1 on the PC is non-existentor in use by other software or hardware. A PC re-configu-ration is required."Cannot open ’filename’" - Be sure file exists in theappropriate directory."BAD CRC" - A CRC error means that after loading,memory contents are incorrect or the wrong 1ecrc.hex filewas used. If 1ecrc.hex is the same version shipped withthe software, a 1e module hardware problem is indicated."Wrong serial number-check cables" - If cabling iscorrect, DS-2250 stiks may have been swapped. The fourbyte serial number is printed to the screen to help inrestoring DS-2250’s to their proper locations. The fourbyte serial numbers must be the same for both DS-2250’sexcept that the least significant byte must be an oddnumber for the top DS-2250 and exactly one less for thebottom DS-2250."Illegal serial number" - Serial number is either invalid,was never programmed, or has been erased.*******END OF PROGRAMMING SPEC*******SERIAL NUMBERINGEach DS-2250 contains a unique serial number. Toavoid loading software to the wrong DS-2250, the loaderprogram, 1eload.exe, uses these serial numbers to checkcabling during programming. GETC code will check DS-2250 serial numbers and will not operate if serial numbersare in the wrong location or if the two serial numbers do notcompare correctly.Do not swap DS-2250 stiks in a 1e module or take oneDS-2250 from a 1e and put it in another 1e. It is permissibleto swap DS-2250’s as pairs if the top and bottom positionsare maintained.LBI-38822LBI-388223PARTS LISTSYMBOL PART NUMBER DESCRIPTION— — — CAPACITORS— — — C119A705205P21Tantalum: 22 µf ±20%, 20 VDCW.thruC5C619A702052P14Ceramic: .01 µf ±10%, 50 VDCW.thruC24C1719A705205P19Tantalum: 2.2 µf ±20%, 10 VDCW.andC18C1919A702061P35Ceramic: 30 pf ±5%, 50VDCW.andC20C2119A705205P2Tantalum: 1 µf ±20%, 16 VDCW.— — — — DIODES— — — — D1HP HSMS-T400LEDandD2D319A700053P2Silicon: 2Diode, Fast Recovery, 250 and mA, 70 PIV.D4— — — — JACKS— — — — J122-12-20343Pin; MolexthruJ5J822-10-20919Pin; MolexandJ9— — — — PLUGS— — — — P119B802001P1Header, 14X2; Samtec SpecialSEP-50546-1.7/01— — — TRANSISTORS— — — Q119A700076P2Transistor; NPN, 3904thruQ3,Q5andQ6,Q8thruQ10Q419A700059P2Transistor; PNP, 3906andQ7SYMBOL PART NUMBER DESCRIPTION— — — — RESISTORS— — — — R119B800607P473Metal Film: 47k ohms ±5%, 1/8 w.R219B800607P103Metal Film: 10k ohms ±5, 1/8 w.R319B800607P102Metal Film: 270 ohms ±5%, 1/8 w.R419B800607P473Metal Film: 47k ohms ±5%, 1/8 w.R519B800607P103Metal Film: 10k ohms ±5%, 1/8 w.R619B800607P271Metal Film: 270 ohms ±5%, 1/8 w.R719B800607P102Metal Film: 1k ohms ±5%, 1/8 w.R819B800607P103Metal Film: 10k ohms ±5%, 1/8 w.thruR13R1419B800607P102Metal Film: 1k ohms ±5%, 1/8 w.R1519B800607P103Metal Film: 10k ohms ±5%, 1/8 w.thruR22R2319B800607P105Metal Film: 1M ohm ±5%, 1/8 w.R2419B800607P102Metal Film: 1k ohms ±5%, 1/8 w.R2519B800607P104Metal Film: 100k ohms ±5%, 1/8 w.andR26R2719B800607P101Metal Film: 100 ohms ±5%, 1/8 w.R2819B800607P103Metal Film: 10k ohms ±5%, 1/8 w.andR29R3019B800607P104Metal Film: 100k ohms ±5%, 1/8 w.R3119B800607P101Metal Film: 100 ohms ±5%, 1/8 w.R3219B800607P104Metal Film: 100k ohms ±5%, 1/8 w.R3319B800607P103Metal Film: 10k ohms ±5%, 1/8 w.andR34R3519B800607P104Metal Film: 100k ohms 5%, 1/8 w.andR36— — — — SWITCHES— — — — S119A701324P1SW, PUSHBUTTON.S2ALCO SE1DGPC SW, 2 Position Slide.andS3— —INTEGRATED CIRCUITS— — U1DS2250-64-12Microcontroller SipStik.andU2U3IDT 7134S70J CMOS Dual-Port RAM, 32k (4kX8-Bit).andU4U519A703471P318Octal 3-State Noninverting Transparent and Latch, 74HC573.U6U819A149446P2RS-232 Drivers/Receivers, MAX232A.U9MC514538BDW Multivibrator (Retriggerable,Resettable).U1019A703483P304Hex Inverter, 74HC04AU1119A703483P302Quad 2-Input NAND Gate, 74HC00.GETC 1e MODULE19D903536P1 (344A3912G1, Rev. 0)Issue 1SYMBOL PART NUMBER DESCRIPTION U1219A705981P101Static RAM (SRAM), HM62256A.andU13U1419A703995P2Hex Unbuffered Inverter, 74HCU04.U1519A703483P321Hex Schmitt-Trigger Inverter, 74HC14.— — — — CRYSTALS— — — — Y119A702511G2611.059 MHz.— — — — SOCKETS— — — — XU1AMP 4-382486-0SIMM Socket.andXU2— — — — JUMPERS— — — — P219A702104P1Jumper.BIVAR CI-192-028Insulator (Under Y1).XETEL 42-000967Printed Wire Board.— — — MISCELLANEOUS— — —HARDWARE KIT344A4019G1(1e Installation) 119B802166P1Guard319B201955P9SPC, Thread4N84P13004B6Screw, Machine519A701365P8Washer6N80P13004B6Screw, machine: Pan head;No. 6-32 x 1/4".7N404P13B6Lockwasher, internal tooth: No. 6.84035306P25Washer, Fiber.919J706152P5Strap, Retaining.HARNESS INSTALLATIONHARDWARE KIT19C337712G17160861P33Clip.19A134011P1Screw (wire tie).LBI-38822LBI-38822 4IC DATA MICROCONTROLLER U1/U2DS2250DUAL PORT SRAM U3/U4IDT7134S70J (344A3040P201)OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH U5, U619A703471P318 (74HC573)RS-232 DRIVERS/RECEIVERS U819A149446P2 (MAX232A)MULTIVIBRATOR (Retriggerable, Resettable) U9MC14538BDWHEX INVERTER U1019A703483P304LBI-38822LBI-388225IC DATAQUAD 2-INPUT NAND GATE U11 19A703483P302 (74HC00) STATIC RAM U12, U1319A705981P101 (62256)HEX UNBUFFERED INVERTER U1419A703995P2 (74HCU04)HEX SCHMITT-TRIGGER INVERTER U15 19A703483P321 H(74HC14)LBI-38822LBI-38822 6INSTALLATION INSTRUCTIONSHARNESS ASSEMBLY(19C337712, Sh. 1, Rev. 0)(19D438125, Sh. 3, Rev. 6) LBI-38822LBI-388227OUTLINE DIAGRAM GETC 1e Module(19D903536, Rev. 1)HARNESS(19D904442, Sh. 1, Rev. 0)LBI-38822LBI-388228SCHEMATIC DIAGRAMLBI-38822LBI-38822GETC 1e Module(19D903613, Sh. 1, Rev. 0)9SCHEMATIC DIAGRAMGETC 1e Module(19D903613, Sh. 2, Rev. 0)LBI-38822LBI-38822 10LBI-38822LBI-38822This page intentionally left blank11。

毛斯（Moxa）UC-8200系列双核ARM Cortex-A7 1GHz IIoT网关产品说明书

毛斯（Moxa）UC-8200系列双核ARM Cortex-A7 1GHz IIoT网关产品说明书

UC-8200SeriesArm Cortex-A7dual-core1GHz IIoT gateways with built-in LTE Cat.4,1mini PCIe expansion slot for a Wi-Fi module,1CAN port,4DIs,4DOsFeatures and Benefits•Armv7Cortex-A7dual-core1GHz•ISASecure IEC62443-4-2Security Level2certified with Moxa IndustrialLinux3Secure•Moxa Industrial Linux with10-year superior long-term support•LTE-ready computer with Verizon/AT&T certification and industrial-grade CE/FCC/UL certifications•Dual-SIM slots•2auto-sensing10/100/1000Mbps Ethernet ports•Integrated LTE Cat.4module with US/EU/APAC band support•1CAN port supports CAN2.0A/B•microSD socket for storage expansion•-40to85°C wide temperature range and-40to70°C with LTE enabledCertificationsIntroductionThe UC-8200computing platform is designed for embedded data acquisition applications.The computer comes with dual RS-232/422/485serial ports,dual10/100/1000Mbps Ethernet ports,and one CAN port as well as dual Mini PCIe socket to support Wi-Fi/cellular modules.These versatile capabilities let users efficiently adapt the UC-8200to a variety of complex communications solutions.The UC-8200is built around a Cortex-A7dual core processor that has been optimized for use in energy monitoring systems,but is widely applicable to a variety of industrial solutions.With flexible interfacing options,this tiny embedded computer is a reliable and secure gateway for data acquisition and processing at field sites as well as a useful communications platform for many other large-scale deployments.Wide temperature LTE-enabled models are available for extended temperature applications.All units are thoroughly tested in a testing chamber, guaranteeing that the LTE-enabled computing platforms are suitable for wide-temperature applications.AppearanceUC-8210UC-8220SpecificationsComputerCPU Armv7Cortex-A7dual-core1GHzDRAM2GB DDR3LSupported OS Moxa Industrial Linux1(Debian9,kernel4.4),2027EOLMoxa Industrial Linux31(Debian11,kernel5.10),2031EOLSee /MILStorage Pre-installed8GB eMMCExpansion Slots MicroSD(SD3.0)socket x13OS is selectable via Moxa Computer Configuration System(CCS)for CTO models.For the model names,see the Ordering Information section of thedatasheet PDF file.Computer InterfaceEthernet Ports Auto-sensing10/100/1000Mbps ports(RJ45connector)x2 Serial Ports RS-232/422/485ports x2,software selectable(DB9male) CAN Ports CAN2.0A/B x1(DB9male)Digital Input DIs x4Digital Output DOs x4USB2.0USB2.0hosts x1,type-A connectorsWi-Fi Antenna Connector UC-8220Models:RP-SMA x2Cellular Antenna Connector UC-8220Models:SMA x2GPS Antenna Connector UC-8220Models:SMA x1Expansion Slots UC-8220-T-LX:mPCIe slot x2UC-8220-T-LX US/EU/AP Models:mPCIe slot x1SIM Format UC-8220Models:NanoNumber of SIMs UC-8220Models:2Buttons Programmable buttonTPM TPM v2.0Ethernet InterfaceMagnetic Isolation Protection 1.5kV(built-in)Security FunctionsHardware-based Security TPM2.0Hardware Root of Trust Secure BootIntrusion Detection Host-based Intrusion DetectionSecurity Tools Security Diagnostic ToolSecurity Event AuditingSecure UpdateDisk Protection LUKS Disk EncryptionRecovery One-step recovery to the last known secure stateDual-system design with automatic failbackReliability Network Keep AliveNetwork Failover and FailbackSerial InterfaceBaudrate300bps to921.6kbpsData Bits7,8Stop Bits1,2Parity None,Even,Odd,Space,MarkFlow Control RTS/CTS,XON/XOFFADDC(automatic data direction control)for RS-485RTS Toggle(RS-232only)Console Port1x4-pin header to DB9console portRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDCAN InterfaceNo.of Ports1Connector DB9maleBaudrate10to1000kbpsIndustrial Protocols CAN2.0ACAN2.0BIsolation2kV(built-in)Signals CAN_H,CAN_L,CAN_GND,CAN_SHLD,CAN_V+,GNDDigital InputsConnector Screw-fastened Euroblock terminalDry Contact Off:openOn:short to GNDIsolation3K VDCSensor Type Wet contact(NPN)Dry contactWet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage24VDC nominal,open collector to30VDCCellular InterfaceCellular Standards LTE Cat.4Band Options US Models:LTE Band2(1900MHz)/LTE Band4(1700MHz)/LTE Band5(850MHz)/LTE Band13(700MHz)/LTE Band17(700MHz)UMTS/HSPA850MHz/1900MHzCarrier Approval:Verizon,AT&TEU Models:LTE Band1(2100MHz)/LTE Band3(1800MHz)/LTE Band5(850MHz)/LTE Band7(2600MHz)/LTE Band8(900MHz)/LTE Band20(800MHz)UMTS/HSPA850MHz/900MHz/1900MHz/2100MHzAP Models:LTE Band1(2100MHz)/LTE Band3(1800MHz)/LTE Band5(850MHz)/LTE Band7(2600MHz)/LTE Band8(900MHz)/LTE Band28(700MHz)UMTS/HSPA850MHz/900MHz/1900MHz/2100MHzReceiver Types GPS/GLONASS/GalileoState-of-the-art GNSS solutionAccuracy Position:2.0m@CEP50Acquisition Hot starts:1.1secCold starts:29.94secSensitivity Cold starts:-145dBmTracking:-160dBmTime Pulse0.25Hz to10MHzLED IndicatorsSystem Power x2Programmable x1SIM card indicator x1Wireless Signal Strength Cellular/Wi-Fi x6Power ParametersNo.of Power Inputs Redundant dual inputsInput Voltage12to48VDCPower Consumption10WInput Current0.8A@12VDCReliabilityAlert Tools External RTC(real-time clock)Automatic Reboot Trigger External WDT(watchdog timer)Physical CharacteristicsDimensions UC-8220Models:141.5x120x39mm(5.7x4.72x1.54in)UC-8210Models:141.5x120x27mm(5.7x4.72x1.06in)141.5x120x27mm(5.7x4.72x1.06in)Weight UC-8210Models:560g(1.23lb)UC-8220Models:750g(1.65lb)Housing SECCMetalIP Rating IP30Installation DIN-rail mountingWall mounting(with optional kit)Environmental LimitsOperating Temperature-40to70°C(-40to158°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Shock IEC60068-2-27Vibration2Grms@IEC60068-2-64,random wave,5-500Hz,1hr per axis(without USB devicesattached)Standards and CertificationsEMC EN55032/35EN61000-6-2/-6-4EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:10V/mIEC61000-4-4EFT:Power:2kV;Signal:1kVIEC61000-4-6CS:10VIEC61000-4-8PFMFIEC61000-4-5Surge:Power:0.5kV;Signal:1kV Industrial Cybersecurity IEC62443-4-1IEC62443-4-2Hazardous Locations Class I Division2ATEXIECExCarrier Approvals VerizonAT&TSafety UL62368-1EN62368-1Green Product RoHS,CRoHS,WEEEMTBFTime UC-8210-T-LX-S:708,581hrsUC-8220-T-LX:650,836hrsUC-8220-T-LX-US-S/EU-S/AP-S:528,574hrs Standards Telcordia(Bellcore)Standard TR/SRWarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x UC-8200Series computerDocumentation1x quick installation guide1x warranty cardInstallation Kit1x DIN-rail kit(preinstalled)1x power jack6x M2.5mounting screws for the cellular module Cable1x console cableDimensions UC-8210UC-8220Ordering Information12UC-8210-T-LX-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8210-T-LX-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in––-40to85°CUC-8220-T-LXDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in Reserved Reserved-40to70°CUC-8220-T-LX-US-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-US-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inUS region LTEmodulepreinstalledReserved-40to70°CUC-8220-T-LX-EU-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-EU-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inEurope regionLTE modulepreinstalledReserved-40to70°CUC-8220-T-LX-AP-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-AP-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inAPAC regionLTE modulepreinstalledReserved-40to70°CUC-8210-T-LX-S(CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in––-40to85°CUC-8220-T-LX(CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual Core–Reserved Reserved-40to70°CUC-8220-T-LX-US-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inUS region LTEmodulepreinstalledReserved-40to70°C12UC-8220-T-LX-EU-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inEurope regionLTE modulepreinstalledReserved-40to70°CUC-8220-T-LX-AP-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inAPAC regionLTE modulepreinstalledReserved-40to70°CAccessories(sold separately)Power AdaptersPWR-12150-EU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,EU plug,-40to75°C operating temperature PWR-12150-UK-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,UK plug,-40to75°C operating temperature PWR-12150-USJP-SA-T Locking barrel plug,12VDC1.5A,100to240VAC,US/JP plug,-40to75°C operating temperature PWR-12150-AU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,AU plug,-40to75°C operating temperature PWR-12150-CN-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,CN plug,-40to75°C operating temperature Power WiringCBL-PJTB-10Non-locking barrel plug to bare-wire cableCablesCBL-F9DPF1x4-BK-100Console cable with4-pin connector,1mWi-Fi Wireless ModulesUC-8200-WLAN22-AC Wireless package for UC-8200V2.0or later with Wi-Fi module,2screws,2spacers,1heat sink,1pad AntennasANT-LTEUS-ASM-01GSM/GPRS/EDGE/UMTS/HSPA/LTE,1dBi,omnidirectional rubber-duck antennaANT-LTE-ASM-04BK704to960/1710to2620MHz,LTE omnidirectional stick antenna,4.5dBiANT-LTE-OSM-03-3m BK700-2700MHz,multiband antenna,specifically designed for2G,3G,and4G applications,3m cable ANT-LTE-ASM-05BK704-960/1710-2620MHz,LTE stick antenna,5dBiANT-LTE-OSM-06-3m BK MIMO Multiband antenna with screw-fastened mounting option for700-2700/2400-2500/5150-5850MHzfrequenciesANT-WDB-ARM-02022dBi at2.4GHz or2dBi at5GHz,RP-SMA(male),dual-band,omnidirectional antennaDIN-Rail Mounting KitsUC-8210DIN-rail Mounting Kit DIN-rail mounting kit for UC-8210with4M3screwsUC-8220DIN-rail Mounting Kit DIN-rail mounting kit for UC-8220with4M3screwsWall-Mounting KitsUC-8200Wall-mounting Kit Wall-mounting kit for UC-8200with4M3screws©Moxa Inc.All rights reserved.Updated Jul18,2023.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。

CS5340-CZZ;中文规格书,Datasheet资料

CS5340-CZZ;中文规格书,Datasheet资料

1Copyright © Cirrus Logic, Inc. 2004(All Rights Reserved)AN249CS5333 to CS5340 Conversionby Kevin L Tretter1.IntroductionThe CS5333 and CS5340 are complete stereo analog-to-digital converters for digital audio systems.These converters perform sampling, analog-to-digital conversion and anti-alias filtering, generating 24-bit values for both left and right channels. These small, low power converters are ideal for systems requiring wide dynamic range and low noise such as set-top boxes, A/V receivers, DVD-karaoke players, DVD re-corders, and automotive applications. The CS5333 is no longer recommended for new designs, and the CS5340 is the suggested replacement.This application note identifies the implementation differences between these two devices, including:-Key specifications -Pinout differences -Startup mode selections -System clocking -Input filter topology -Reference pin decoupling2.Key SpecificationsTable 1 shows a comparison of the key specifications of these two devices, and Table 2 shows the pin comparison between the CS5333 and the CS5340. Although these two devices are not pin compatible,they are very similar in terms of overall functionality and feature set. The CS5340 achieves higher analog performance and supports a wider range of output sample rates, including 192kHz. This additional per-formance is the main reason for the increased power consumption of the CS5340 relative to the CS5333.Table 1. Comparison of Key SpecificationsMAR ‘04AN249REV1The CS5333 and CS5340 are both available in a 16-pin TSSOP package. As can be seen from Table2, all but three pins correlate directly in terms of functionality. These three pins account for a difference in operational mode selection and a separate voltage supply pin for the CS5340 digital core.Table 2. Pin Compatibility Between the CS5333 and CS534023.Typical Connection DiagramsFigures 1 and 2 illustrate the typical connection diagram for the CS5333 and CS5340 respectively. The analog and digital core of the CS5333 are powered from VA, which can be set from 1.8V to 3.3V. The VL supply pin powers the digital interface logic from 1.8V to 3.3V and can be set independently from VA.Figure 1. CS5333 Typical Connection Diagram3The CS5340 has separate power supply pins for the analog and digital cores. The analog section is pow-ered from the VA supply and the digital section is powered off of the VD supply. Both of these supply pins can be powered from the same external source with a small series resistor between them for noise isola-tion. Both the analog and digital cores can operate independently from 3.3V to 5.0V. The VL pin of the CS5340 supplies the digital interface logic, supports a wide operating range from 1.8V to 5.0V, and can be powered independently from the VA and VD power supplies.Figure 2. CS5340 Typical Connection Diagram44.Master/Slave and Speed Mode Selection4.1CS5333In the CS5333, the selection for Master or Slave mode operation is determined by a resistor pull-up/pull-down on the SDATA pin (pin 4), as noted in Figure 1. If operating in Master mode, the Speed mode is selected by the DIV pin (pin 8). If DIV is resistively pulled low, the CS5333 will enter into Base Rate mode (Fs = 2kHz to 50kHz). If DIV is resistively pulled high to VL, the CS5333 will enter into High Rate mode (Fs = 50kHz to 100kHz). If the CS5333 is operating in Slave mode, the Speed mode is auto-detected and the DIV pin operates as an MCLK divide by two enable.4.2CS5340In the CS5340, Master or Slave mode operation and Speed mode is determined by the mode pins, M1 and M0 (pins 16 and 1 respectively), as shown in Table 3.Table 3. CS5340 Mode ControlPlease note that Base Rate mode is synonymous with Single Speed mode, and High Rate mode is syn-onymous with Double Speed mode.5.Digital Interface Format Select5.1CS5333The CS5333 supports both Left Justified and I2S digital interface formats. The interface is selectable by the DIF pin (pin 9). If this pin is held at a logic low upon startup, I2S interface format will be selected. If held at a logic high upon startup, Left Justified interface format will be selected.5.2CS5340The CS5340 also supports both Left Justified and I2S digital interface formats. The interface is selectable by a resistor pull-up/pull-down on the SDOUT pin (pin 4). If this pin is resistively pulled low upon startup, Left Justified interface format will be selected. If this pin is resistively pulled high to VL upon startup, I2S interface format will be selected.6.System ClockingThe clocking requirements for the CS5333 and CS5340 are the same for Master mode operation. How-ever, in Slave mode operation the CS5340 only supports a subset of the clocking supported in the CS5333. The CS5333 supports an MCLK/LRCK ratio of 256x, 384x, 512x, and 768x in Base Rate mode and 128x, 192x, 256x and 384x in High Rate mode. The CS5340 cannot support ratios of 192x, 384x, or 768x. See Table 4. Due to the auto-speed mode detect circuitry implemented in the CS5340, not all sam-ple rate ranges are supported in Slave mode. Please refer to the CS5340 datasheet for more information.Device Speed Mode Supported MCLK/LRCK RatiosCS5333Base Rate256, 384, 512, 768High Rate128, 192, 256, 384CS5340Single Speed256, 512Double Speed128, 256Table 4. Supported MCLK/LRCK Ratios, Slave Mode Operation57.Input Filter TopologyBoth the CS5333 and CS5340 implement a single-ended input architecture. Due to differences in the input sampling topologies within the converters, the input filter requirements are different between these two devices.A suggested input filter topology for the CS5333 is shown in Figure 3. This input network consists of an AC-coupling capacitor along with a single-pole lowpass filter.Figure 3. CS5333 Input FilterThe CS5333 will self-bias the analog input node to the optimal bias point (half of VA). The CS5333 imple-ments an internal buffer on the analog input, reducing the amount of switching current on the input sam-pling node. This reduction in switching current makes the CS5333 less sensitive to series resistance on the analog input lines.A suggested input filter topology for the CS5340 is shown in Figure 4.Figure 4. CS5340 Input FilterThis filter topology implements an external resistor-divider circuit to bias the output of the amplifier to the optimal bias point (half of VA). Due to the internal architecture, the CS5340 requires low impedance on the analog input lines. The topology shown in Figure 4 provides a sub-ohm input source impedance into the CS5340 and isolates the input to the amplifier. For more information on this input filter topology, please refer to the Application Note AN241.A passive input filter can be used with the CS5340, however, the full analog performance of the CS5340 will not be realized. Figure 5 illustrates a unity gain, passive input filter solution and the resulting distortion performance. Please note that in this case the dynamic range performance of the CS5340 will not be lim-ited by the input filter; only the distortion performance is affected.6Figure 5. CS5340 Passive Input Filter, Solution 17Some applications may require signal attenuation prior to the converter. The full-scale input voltage of the CS5340 will scale with the analog power supply voltage. For VA = 5.0V, the full-scale input voltage is approximately 2.8Vpp, or 1Vrms. Typical consumer audio line level outputs range from 1.5 to 2Vrms. Figure 6 shows a passive input filter for the CS5340 and the resulting THD+N over the audio bandwidth. This filter provides 6dB of signal attenuation. Due to the relatively high input impedance on the CS5340 analog inputs, the full distortion performance of the CS5340 cannot be realized. Also, the combination of the series resistor and the biasing resistor-divider circuit will determine the input impedance into the input filter. In the circuit shown in Figure 6, the input impedance is approximately 5kΩ. By doubling the resistor values, the input impedance will increase to 10kΩ. However, in this case the distortion performance will drop to approximately 70dB due to the increase in series resistance on the CS5340 analog inputs.Figure 6. CS5340 Passive Input Filter, Solution 288.Capacitor Size on the Reference Pin (FILT+)The CS5340 and CS5333 require external capacitance on the internal reference voltage pin. For the CS5333, the internal reference voltage is output on FILT+ (pin 11). On the CS5340, the FILT+ reference voltage is output on pin 15. The size of the decoupling capacitor on this reference pin will affect the low frequency distortion performance. The recommended solution for the CS5333 is a 1µF capacitor between the FILT+ pin and analog ground. The recommended solution for the CS5340 is to use a 0.1µF capacitor in parallel with a 1µF capacitor for cost sensitive applications. See Figure 7 which illustrates the typical low frequency distortion performance of the CS5340 with different size capacitors on the FILT+ reference pin (pin 15). This plot was taken implementing the recommended input filter shown in Figure 4.Figure 7. CS5340 THD+N versus Frequency9.ConclusionThe CS5340 is the recommended replacement for the CS5333, offering higher performance and 192kHz output sample rate capability. Special considerations must be made when upgrading designs to use the CS5340 in place of the CS5333. These considerations include pin compatibility, functional mode selec-tions, input filter design, and external capacitor requirements on the FILT+ reference pin.9Revision Date Change116 March 2004Initial ReleaseContacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: /IMPORTANT NOTICECirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). 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CS5340-CZZR中文资料

CS5340-CZZR中文资料


Single-Ended Analog Input
AINR Switch-Cap ADC
High-Pass Filter
Low-Latency Digital Filters
Serial Port
VL 1.8 V to 5 V
Auto-detect MCLK Divider
Master Clock
Slave Mode Auto-detect
2. PIN DESCRIPTION .............................................................................................................................. 13 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14 4. APPLICATIONS ................................................................................................................................... 15
192 kHz 101 dB Dynamic Range at 5 V -94 dB THD+N 90 mW Power Consumption High-Pass Filter to Remove DC Offsets Analog/Digital Core Supplies from 3.3 V to 5 V Supports Logic Levels between 1.8 V and 5 V Auto-detect Mode Selection in Slave Mode Auto-Detect MCLK Divider Pin Compatible with CS5341