Bus Operation – Asynchronous InterfaceThe asynchronous interface is active when the NAND Flash device powers on. The I/O bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS sig-nal, if present, is tri-stated when the asynchronous interface is active.Asynchronous interface bus modes are summarized below.Table 3: Asynchronous Interface Mode SelectionNotes: 1.DQS is tri-stated when the asynchronous interface is active.2.WP# should be biased to CMOS LOW or HIGH for standby.3.Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V IH or V IL .Asynchronous Enable/StandbyA chip enable (CE#) signal is used to enable or disable a target. When CE# is driven LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept commands, addresses, and data I/O. There may be more than one target in a NAND Flash package. Each target is controlled by its own chip enable; the first target (Target 0)is controlled by CE#; the second target (if present) is controlled by CE2#, etc.A target is disabled when CE# is driven HIGH, even when the target is busy. When disa-bled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionali-ty is also known as CE# "Don't Care". While the target is disabled, other devices can utilize the disabled NAND signals that are shared with the NAND Flash.A target enters low-power standby when it is disabled and is not busy. If the target is busy when it is disabled, the target enters standby after all of the die (LUNs) complete their operations. Standby helps reduce power consumption.Asynchronous Bus IdleA target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.During bus idle, all of the signals are enabled except DQS, which is not used when the asynchronous interface is active. No commands, addresses, and data are latched into the target; no data is output.16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous InterfaceREAD PAGE (00h-30h)The READ PAGE (00h–30h) command copies a page from the NAND Flash array to itsrespective cache register and enables data output. This command is accepted by the die(LUN) when it is ready (RDY = 1, ARDY = 1).To read a page from the NAND Flash array, write the 00h command to the commandregister, the write five address cycles to the address registers, and conclude with the 30hcommand. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for t R as data istransferred.To determine the progress of the data transfer, the host can monitor the target's R/B#signal or, alternatively, the status operations (70h, 78h) can be used. If the status opera-tions are used to monitor the LUN's status, when the die (LUN) is ready(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuingthe READ MODE (00h) command. When the host requests data output, output beginsat the column address specified.During data output the CHANGE READ COLUMN (05h-E0h) command can be issued.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) prior to the issue of the READ MODE (00h)command. This prevents bus contention.The READ PAGE (00h-30h) command is used as the final command of a multi-planeread operation. It is preceded by one or more READ PAGE MULTI-PLANE (00h-32h)commands. Data is transferred from the NAND Flash array for all of the addressedplanes to their respective cache registers. When the die (LUN) is ready(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the planeaddressed in the READ PAGE (00h-30h) command. When the host requests data output,output begins at the column address last specified in the READ PAGE (00h-30h) com-mand. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used toenable data output in the other cache registers. See Multi-Plane Operations for addition-al multi-plane addressing requirements.Figure 51: READ PAGE (00h-30h) OperationCycle typeDQ[7:0]RDY16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NANDRead Operations16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NANDActivating Interfaces。
地址：厦门市集美区软件园三期诚毅大街370号A06栋11层1/64F3X28-D 系列使用说明书文档版本密级V1.0.2产品名称：F3X28-D 共28页F3X28-D 系列使用说明书此说明书适用于下列型号产品：型号产品类别F3828-D 4G 模块F3828-DS 4G 模块+国网加密F3828-DG 4G 模块+GPS/北斗F3828-DGS 4G 模块+GPS/北斗+国网加密F3Z28-D 公专一体模块F3Z28-DS 公专一体模块+国网加密F3Z28-DG 公专一体模块+GPS/北斗F3Z28-DGS 公专一体模块+GPS/北斗+国网加密F3928-D 5G 模块F3928-DS 5G 模块+国网加密F3928-DG 5G 模块+GPS/北斗F3928-DGS 5G 模块+GPS/北斗+国网加密客户热线：400-8838-199网址：地址：厦门集美软件园三期A06栋11层文档修订记录日期版本说明作者2021.02.05V1.0.0初始版本HCW2021.04.12V1.0.1图片更新，供电范围更新HCW2021.4.30V1.0.2更新版本WWW2/64地址：厦门市集美区软件园三期诚毅大街370号A06栋11层地址：厦门市集美区软件园三期诚毅大街370号A06栋11层3/64著作权声明本文档所载的所有材料或内容受版权法的保护，所有版权由厦门四信通信科技有限公司拥有，但注明引用其他方的内容除外。
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• Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.• When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.(1) The products covered herein are designed and manufactured for the following application areas. When using theproducts covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph(3).• Office electronics• Instrumentation and measuring equipment• Machine tools• Audiovisual equipment• Home appliance• Communication equipment other than for trunk lines(2) Those contemplating using the products covered herein for the following equipment which demands highreliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment• Mainframe computers• Traffic control systems• Gas leak detectors and automatic cutoff devices• Rescue and security equipment• Other safety devices and safety equipment, etc.(3) Do not use the products covered herein for the following equipment which demands extremely high performancein terms of functionality, reliability, or accuracy.• Aerospace equipment• Communications equipment for trunk lines• Control equipment for the nuclear power industry• Medical equipment related to life support, etc.(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a salesrepresentative of the company.• Please direct all queries regarding the products covered herein to a sales representative of the company.PAGE 44-Lead SOP Pinout (3)Pin Descriptions (4)Memory Map (5)Identifier Codes and OTP Addressfor Read Operation (6)OTP Block Address Map for OTP Program (7)Bus Operation (8)Command Definitions (9)Functions of Block Lock and Block Lock-Down (11)Block Locking State Transitions uponCommand Write (11)Status Register Definition (12)Extended Status Register Definition (13)PAGE 1 Electrical Specifications (14)1.1 Absolute Maximum Ratings (14)1.2 Operating Conditions (14)1.2.1 Capacitance (15)1.2.2 AC Input/Output Test Conditions (15)1.2.3 DC Characteristics (16)1.2.4 AC Characteristics- Read-Only Operations (17)1.2.5 AC Characteristics- Write Operations (20)1.2.6 Reset Operations (22)1.2.7 Block Erase, Full Chip Erase,(Page Buffer) Program andOTP Program Performance (23)2 Related Document Information (24)CONTENTSLH28F640BFN-PTTLZ2 64Mbit (4Mbit×16) Page Mode Flash MEMORY64M density with 16Bit I/O InterfaceHigh Performance Reads• 90/35ns 8-Word Page ModeLow Power Operation• 2.7V Read and Write Operations• Automatic Power Savings Mode Reduces I CCRin Static ModeEnhanced Code + Data Storage• 5µs Typical Erase/Program SuspendsOTP (One Time Program) Block• 4-Word Factory-Programmed Area• 4-Word User-Programmable AreaHigh Performance Program with Page Buffer• 16-Word Page BufferOperating Temperature 0°C to +70°CFlexible Blocking Architecture• Eight 4K-word Parameter Blocks• One-hundred and twenty-seven 32K-word Main Blocks• Top Parameter LocationCMOS Process (P-type silicon substrate) Enhanced Data Protection Features• Individual Block Lock and Block Lock-Down with Zero-Latency• All blocks are locked at power-up or device reset.• Block E rase, Full Chip E rase, (Page Buffer) Word Program Lockout during Power TransitionsAutomated Erase/Program Algorithms• 3.0V Low-Power 11µs/Word (Typ.)ProgrammingCross-Compatible Command Support• Basic Command Set• Common Flash Interface (CFI)Extended Cycling Capability• Minimum 100,000 Block Erase Cycles44-Lead SOPETOX TM* Flash TechnologyNot designed or rated as radiation hardenedThe product, which is Page Mode Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at V CC=2.7V-3.6V. Its low voltage operation capability greatly extends battery life for portable applications.The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states.The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage.Fast program capability is provided through the use of high speed Page Buffer Program.Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.* ETOX is a trademark of Intel Corporation.Table 1.Pin DescriptionsSymbol Type Name and FunctionA0-A21INPUT ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21DQ0-DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code and identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle.CE#INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE#-high (V IH) deselects the device and reduces power consumption to standby levels.RST#INPUT RESET: When low (V IL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (V IH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down.OE#INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.WE#INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first).V CC SUPPLY DE VICE POWE R SUPPLY (2.7V-3.6V): With V CC≤V LKO, all write attempts to the flash memory are inhibited. Device operations at invalid V CC voltage (see DC Characteristics) produce spurious results and should not be attempted.GND SUPPLY GROUND: Do not float any ground pins.NOTES:1. Top parameter device has its parameter blocks at the highest address.2. DQ 15-DQ 2 are reserved for future implementation.3. OTP-LK=OTP Block Lock configuration.4. OTP=OTP Block data.Table 2.Identifier Codes and OTP Address for Read OperationCodeAddress [A 21-A 0]Data [DQ 15-DQ 0]NotesManufacturer Code Manufacturer Code 000000H 00B0H Device CodeTop Parameter Device Code 000001H 00B0H 1Block Lock Configuration CodeBlock is Unlocked Block Address + 2DQ 0 = 02Block is LockedDQ 0 = 12Block is not Locked-Down Block Address + 2DQ 1 = 02Block is Locked-DownDQ 1 = 12OTPOTP Lock000080HOTP-LK 3OTP 000081-000088HOTP4NOTES:1. See DC Characteristics for V IL or V IH voltages.2. X can be V IL or V IH for control pins and addresses.3. RST# at GND±0.2V ensures the lowest power consumption.4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when V CC =2.7V-3.6V.5. Refer to Table 4 for valid D IN during a write operation.6. Never hold OE# low and WE# low at the same timing.7. Refer to Appendix of LH28F640BF series for more information about query code.Table 3.Bus Operation (1, 2)Mode Notes RST#CE#OE#WE#Address DQ 0-15Read Array 6V IH V IL V IL V IH X D OUT Output Disable V IH V IL V IH V IH X High Z Standby V IH V IH X X X High Z Reset3V IL X X X X High Z Read Identifier Codes/OTP 6V IH V IL V IL V IH See Table 2See Table 2Read Query 6,7V IH V IL V IL V IH See AppendixSee Appendix Write4,5,6V IHV ILV IHV ILXD INNOTES:1. Bus operations are defined in Table 3.2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.X=Any valid address within the device.IA=Identifier codes address (See Table 2).QA=Query codes address. Refer to Appendix of LH28F640BF series for details.BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.OA=Address of OTP block to be read or programmed (See Figure 3).3. ID=Data read from identifier codes. (See Table 2).QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits.WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.N-1=N is the number of the words to be loaded into a page buffer.4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, and the data within OTP block (See Table 2).The Read Query command is available for reading CFI (Common Flash Interface) information.5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is V IH .6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of LH28F640BF series for details.8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be acceptedTable mand Definitions (10)CommandBusCycles Req ’d Notes First Bus CycleSecond Bus Cycle Oper (1)Addr (2)Data Oper (1)Addr (2)Data (3)Read Array1Write X FFH Read Identifier Codes/OTP ≥ 24Write X 90H Read IA or OA ID or OD Read Query ≥ 24Write X 98H Read QA QD Read Status Register 211Write BA or WA70H ReadBA or WASRDClear Status Register 1Write X 50H Block Erase 25Write BA 20H Write BA D0H Full Chip Erase 25,8Write X 30H Write X D0H Program25,6Write WA 40H or 10H Write WA WD Page Buffer Program ≥ 45,7Write WA E8H WriteWAN-1Block Erase and (Page Buffer) Program Suspend18Write BA or WA B0H Block Erase and (Page Buffer) Program Resume 18Write BA or WA D0H Set Block Lock Bit 2Write BA 60H Write BA 01H Clear Block Lock Bit 29Write BA 60H Write BA D0H Set Block Lock-down Bit 2Write BA 60H Write BA 2FH OTP Program28WriteOAC0HWriteOAODwhile the block erase operation is being suspended.9. Following the Clear Block Lock Bit command, the selected block is unlocked regardless of lock-down configuration.10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.11. When the status register data is read, input the address to which the erase or program operation is executed.NOTES:1. DQ 0=1: a block is locked; DQ 0=0: a block is unlocked.DQ 1=1: a block is locked-down; DQ 1=0: a block is not locked-down.2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations.3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,[01] regardless of the states before power-off or reset operation.4. OTP (One Time Program) block has the lock function which is different from those described above.NOTES:1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command.2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ 0=0), the corresponding block is locked-down and automatically locked at the same time.3. "No Change" means that the state remains unchanged after the command written.Table 5.Functions of Block Lock (4) and Block Lock-DownCurrent StateErase/Program Allowed (2)State DQ 1(1)DQ 0(1)State Name [00]00Unlocked Yes [01](3)01Locked No [10]10Unlocked Yes [11]11LockedNoTable 6.Block Locking State Transitions upon Command Write Current State Result after Lock Command Written (Next State)State DQ 1DQ 0Set Lock (1)Clear Lock (1)Set Lock-down (1)[00]00[01]No Change (3)[11](2)[01]01No Change [00][11][10]10[11]No Change [11](2)[11]11No Change[10]No ChangeTable 7.Status Register DefinitionR R R R R R R R 15141312111098 WSMS BESS BEFCES PBPOPS R PBPSS DPS R 76543210SR.15 - SR.8 = RESERVED FOR FUTUREENHANCEMENTS (R)SR.7 = WRITE STATE MACHINE STATUS (WSMS)1 = Ready0 = BusySR.6 = BLOCK ERASE SUSPEND STATUS (BESS)1 = Block Erase Suspended0 = Block Erase in Progress/CompletedSR.5 = BLOCK ERASE AND FULL CHIP ERASESTATUS (BEFCES)1 = Error in Block Erase or Full Chip Erase0 = Successful Block Erase or Full Chip EraseSR.4 = (PAGE BUFFER) PROGRAM ANDOTP PROGRAM STATUS (PBPOPS)1 = Error in (Page Buffer) Program or OTP Program0 = Successful (Page Buffer) Program or OTP Program SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.2 = (PAGE BUFFER) PROGRAM SUSPENDSTATUS (PBPSS)1 = (Page Buffer) Program Suspended0 = (Page Buffer) Program in Progress/CompletedSR.1 = DEVICE PROTECT STATUS (DPS)1 = Erase or Program Attempted on aLocked Block, Operation Abort0 = UnlockedSR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0".If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, attempt, an improper command sequence was entered.SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block E rase, Full Chip E rase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status.SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and should be masked out when polling the status register.Table 8.Extended Status Register DefinitionR R R R R R R R 15141312111098 SMS R R R R R R R 76543210XSR.15-8 = RESERVED FOR FUTUREENHANCEMENTS (R)XSR.7 = STATE MACHINE STATUS (SMS)1 = Page Buffer Program available0 = Page Buffer Program not availableXSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.1 Electrical Specifications 1.1 Absolute Maximum Ratings *Operating TemperatureDuring Read, Erase and Program......0°C to +70°C (1)Storage TemperatureDuring under Bias...............................-10°C to +80°C During non Bias................................-65°C to +125°C V oltage On Any Pin(except V CC )............................-0.5V to V CC +0.5V (2)V CC Supply V oltage...........................-0.2V to +3.9V (2)Output Short Circuit Current...........................100mA (3)*WARNING: Stressing the device beyond the "AbsoluteMaximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.NOTES:1. Operating temperature is for commercial temperature product defined by this specification.2. All specified voltages are with respect to GND.Minimum DC voltage is -0.5V on input/output pins and -0.2V on V CC pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is V CC +0.5V which,during transitions, may overshoot to V CC +2.0V for periods <20ns.3. Output shorted for no more than one second. No more than one output shorted at a time.1.2 Operating ConditionsNOTES:1. See DC Characteristics tables for voltage range-specific specification.ParameterSymbol Min.Typ.Max.Unit NotesOperating Temperature T A 0+25+70°C V CC Supply Voltage V CC2.73.03.6V 1Main Block Erase Cycling 100,000Cycles Parameter Block Erase Cycling100,000Cycles1.2.3 DC CharacteristicsNOTES:1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V CC =3.0V and T A =+25°C unless V CC is specified.2. I CCWS and I CCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device ’s current draw is the sum of I CCES and I CCR or I CCW . If read is executed while in (page buffer) program suspend mode, the device ’s current draw is the sum of I CCWS and I CCR .3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V CC ≤V LKO , and not guaranteed outside the specified voltage.4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (t AVQV ) provide new data when addresses are changed.5. Sampled, not 100% tested.V CC =2.7V-3.6VSymbol ParameterNotes Min.Typ.Max.Unit Test Conditions I LI Input Load Current 1-1.0+1.0µA V CC =V CC Max.,V IN /V OUT =V CC or GND I LO Output Leakage Current 1-1.0+1.0µA I CCS V CC Standby Current1625µAV CC =V CC Max.,CE#=RST#= V CC ±0.2V I CCAS V CC Automatic Power Savings Current 1,4420µA V CC =V CC Max.,CE#=GND±0.2V I CCDV CC Reset Power-Down Current 1420µA RST#=GND±0.2V I CCRAverage V CC Read CurrentNormal Mode11525mAV CC =V CC Max.,CE#=V IL ,OE#=V IH ,f=5MHzAverage V CC ReadCurrentPage Mode8 Word Read 1510mA I CCW V CC (Page Buffer) Program Current 1,52060mA I CCE V CC Block Erase, Full Chip Erase Current1,51030mA I CCWS I CCES V CC (Page Buffer) Program or Block Erase Suspend Current 1,215210µA CE#=V IHV IL Input Low Voltage 5-0.40.4V V IH Input High V oltage 5 2.4V CC + 0.4V V OL Output Low V oltage 50.2V V CC =V CC Min.,I OL =100µA V OH Output High V oltage 5V CC -0.2V V CC =V CC Min.,I OH =-100µAV LKOV CC Lockout Voltage31.5V1.2.4 AC Characteristics - Read-Only Operations(1)V CC=2.7V-3.6V, T A=0°C to +70°CSymbol Parameter Notes Min.Max.Unit t AV AV Read Cycle Time90ns t AVQV Address to Output Delay90ns t ELQV CE# to Output Delay390ns t APA Page Address Access Time35ns t GLQV OE# to Output Delay320ns t PHQV RST# High to Output Delay150ns t EHQZ, t GHQZ CE# or OE# to Output in High Z, Whichever Occurs First220ns t ELQX CE# to Output in Low Z20ns t GLQX OE# to Output in Low Z20ns t OH Output Hold from First Occurring Address, CE# or OE# change20ns NOTES:1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.2. Sampled, not 100% tested.3. OE# may be delayed up to t ELQV t GLQV after the falling edge of CE# without impact to t ELQV.1.2.5 AC Characteristics - Write Operations (1), (2)NOTES:1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.2. A write operation can be initiated and terminated with either CE# or WE#.3. Sampled, not 100% tested.4. Write pulse width (t WP ) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of CE# or WE# (whichever goes high first). Hence, t WP =t WLWH =t ELEH =t WLEH =t ELWH .5. Write pulse width high (t WPH ) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling edge of CE# or WE# (whichever goes low last). Hence, t WPH =t WHWL =t EHEL =t WHEL =t EHWL .6. t WHR0 (t EHR0) after the Read Query or Read Identifier Codes/OTP command=t A VQV +100ns.7. Refer to Table 4 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.V CC =2.7V-3.6V, T A =0°C to +70°CSymbol ParameterNotesMin.Max.Unit t AV AVWrite Cycle Time90ns t PHWL (t PHEL )RST# High Recovery to WE# (CE#) Going Low 3150ns t ELWL (t WLEL )CE# (WE#) Setup to WE# (CE#) Going Low 40ns t WLWH (t ELEH )WE# (CE#) Pulse Width460ns t DVWH (t DVEH )Data Setup to WE# (CE#) Going High 740ns t AVWH (t AVEH )Address Setup to WE# (CE#) Going High 750ns t WHEH (t EHWH )CE# (WE#) Hold from WE# (CE#) High 0ns t WHDX (t EHDX )Data Hold from WE# (CE#) High 0ns t WHAX (t EHAX )Address Hold from WE# (CE#) High 0ns t WHWL (t EHEL )WE# (CE#) Pulse Width High 530ns t WHGL (t EHGL )Write Recovery before Read 30ns t WHR0 (t EHR0)WE# (CE#) High to SR.7 Going "0"3, 6t A VQV +50ns1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance (3)NOTES:1. Typical values measured at V CC =3.0V and T A =+25°C. Assumes corresponding lock bits are not set. Subject to change based on device characterization.2. Excludes external system-level overhead.3. Sampled, but not 100% tested.4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than t ERES and its sequence is repeated, the block erase operation may not be finished.V CC =2.7V-3.6V, T A =0°C to +70°CSymbolParameterNotes Page BufferCommand is Used or not Used Min.Typ.(1)Max.(2)Unitt WPB 4K-Word Parameter Block Program Time 2Not Used 0.050.3s 2Used 0.030.12s t WMB 32K-Word Main Block Program Time 2Not Used 0.38 2.4s 2Used 0.24 1.0s t WHQV1/t EHQV1Word Program Time 2Not Used 11200µs 2Used 7100µs t WHOV1/t EHOV1OTP Program Time 2Not Used36400µs t WHQV2/t EHQV24K-Word Parameter Block Erase Time2-0.34s t WHQV3/t EHQV332K-Word Main Block Erase Time2-0.65s Full Chip Erase Time280700s t WHRH1/t EHRH1(Page Buffer) Program Suspend Latency Time to Read 4-510µs t WHRH2/t EHRH2Block Erase Suspend Latency Time to Read 4-520µst ERESLatency Time from Block Erase Resume Command to Block Erase Suspend Command5-500µs2 Related Document Information(1)Document No.Document NameFUM00701 LH28F640BF series AppendixNOTE:1. International customers should contact their local SHARP or distribution sales offices.A-1.1.1 Rise and Fall TimeSymbol Parameter Notes Min.Max.Unit t VR V CC Rise Time10.530000µs/V t R Input Signal Rise Time1, 21µs/V t F Input Signal Fall Time1, 21µs/VNOTES:1. Sampled, not 100% tested.2. This specification is applied for not only the device power-up but also the normal operations.A-2 RELATED DOCUMENT INFORMATION(1)Document No.Document Name AP-001-SD-E Flash Memory Family Software DriversAP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, V PP Electric Potential Switching CircuitNOTE:1. International customers should contact their local SHARP or distribution sales office.。
