M37736MHB中文资料

DESCRIPTIONThe M37733MHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on.Its strong points are the low power dissipation, the low supply voltage, and the small package.FEATURESq Number of basic instructions (103)q Memory size ROM ................................................. 124 KbytesRAM ................................................ 3968 bytes q Instruction execution timeThe fastest instruction at 12 MHz frequency ...................... 333 ns q Single power supply ...................................................... 2.7–5.5 V q Low power dissipation (At 3 V supply voltage, 12 MHz frequency)............................................ 9 mW (Typ.)q Interrupts ............................................................ 19 types, 7 levels q Multiple-function 16-bit timer ................................................. 5 + 3 q Serial I/O (UART or clock synchronous) . (3)q10-bit A-D converter .............................................. 8-channel inputs q12-bit watchdog timerq Programmable input/output(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) (68)q Clock generating circuit ........................................ 2 circuits built-in q Small package......................80-pin plastic molded fine-pitch QFP(80P6D-A;0.5 mm lead pitch) APPLICATIONControl devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on.Control devices for general industrial equipment such as communication equipment, and so on.FUNCTIONS OF M37733MHLXXXHPMemory sizeInput/Output ports Multi-function timersInterruptsClock generating circuit Power dissipation Parameter FunctionsNumber of basic instructions103Instruction execution time333 ns (the fastest instruction at external clock 12 MHz frequency) ROM124 KbytesRAM3968 bytesP0 – P2, P4 – P88-bit ! 8P34-bit ! 1TA0, TA1, TA2, TA3, TA416-bit ! 5TB0, TB1, TB216-bit ! 3Serial I/O(UART or clock synchronous serial I/O) ! 3A-D converter10-bit ! 1 (8 channels)Watchdog timer12-bit ! 13 external types, 16 internal typesEach interrupt can be set to the priority level (0 – 7.)2 circuits built-in (externally connected to a ceramic resonator or aquartz-crystal oscillator)Supply voltage 2.7 – 5.5 V9 mW (at 3 V supply voltage, external clock 12 MHz frequency)22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency)Input/Output voltage 5 VOutput current 5 mAMemory expansion Maximum 16 MbytesOperating temperature range–40 to 85 °CDevice structure CMOS high-performance silicon gate processPackage80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) Input/Output characteristicPIN DESCRIPTIONX IN Clock input Input X OUTClock output Output PinName Input/Output FunctionsVcc,Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss.Vss CNVssCNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode.RESETReset input Input When “L” level is applied to this pin, the microcomputer enters the reset state.These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal oscillator between X IN and X OUT . When an external clock is used, the clock source should be connected to the X IN pin, and the X OUT pin should be left open.EEnable output Output This pin functions as the enable signal output pin which indicates the access status in the internal bus. When output level of E signal is “L”, data/instruction read or data write is performed.BYTE External data InputIn the memory expansion mode or the microprocessor mode, this pin determines whether the bus widthexternal data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”selection input signal is input and an 8-bit width when “H” signal is input.AVcc,Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.AVss source input V REF Reference Input This is reference voltage input pin for the A-D converter.voltage input P00 – P07I/O port P0I/OIn the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset.In the memory expansion mode or the microprocessor mode, these pins output address (A 0 – A 7).P10 – P17I/O port P1I/OIn the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D 8 – D 15) is input/output or an address (A 8 – A 15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A 8 – A 15) is output.P20 – P27I/O port P2I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D 0 – D 7) is input/output or an address (A 16 – A 23) is output.P30 – P33I/O port P3I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, R/W , BHE , ALE, and HLDA signals are output.P40 – P47I/O port P4I/OIn the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port.P50 – P57I/O port P5I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI 0 – KI 3).P60 – P67I/O port P6I/O In addition to having the same functions as port P0 in the single-chip mode, these pins alsofunction as I/O pins for timer A4, input pins for external interrupt input (INT 0 – INT 2) and input pins for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin.P70 – P77I/O port P7I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76and P77 have the function as the output pin (X COUT ) and the input pin (X CIN ) of the sub-clock(32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the X COUT and X CIN pins,connect a resonator or an oscillator between the both.P80 – P87I/O port P8I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1.SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERN o t i c e :T S o me p a r a m e t r i BASIC FUNCTION BLOCKSThe M37733MHLXXXHP has the same functions as theM37733MHBXXXFP except for the package and the reset circuit.Refer to the section on the M37733MHBXXXFP.RESET CIRCUIT_____The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 2.7 – 5.5 V. Program execution starts at the address formed by setting address A 23 – A 16 to 0016, A 15 – A 8 to the contents of address FFFF 16, and A 7 – A 0 to the contents of address FFFE 16.Figure 3 shows an example of a reset circuit. When the stabilized clock is input from the external to the main-clock oscillation circuit,the reset input voltage must be 0.55 V or less when the power source voltage reaches 2.7 V. When a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized.The status of the internal registers during reset is the same as the M37733MHBXXXFP’s.ADDRESSING MODESThe M37733MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details.MACHINE INSTRUCTION LISTThe M37733MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details.DATA REQUIRED FOR MASK ROM ORDERINGPlease send the following data for mask orders.(1) M37733MHLXXXHP mask ROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets)N o t i c e :T S o me p a r a m e t r i SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERSymbolParameter ConditionsRatings Unit Vcc Power source voltage–0.3 to +7V AVcc Analog power source voltage–0.3 to +7V V I _____Input voltage RESET , CNVss, BYTE–0.3 to +12V Input voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,V REF , X INOutput voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,_X OUT , EP d Power dissipation Ta = 25 °C 200mW T opr Operating temperature –40 to +85°C T stgStorage temperature–65 to +150°CV IV O Limits Min.Typ.Max.f(X IN ) : Operating2.7 5.5f(X IN ) : Stopped, f(X CIN ) = 32.768 kHz2.75.5AVcc Analog power source voltage Vcc V Vss Power source voltage0V AVss Analog power source voltageVHigh-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)High-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode)Low-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P44 – P47, P50 – P53Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87I OL(avg)Low-level average output current P44 – P47, P50 – P5312mA f(X IN )Main-clock oscillation frequency (Note 4)12MHz f(X CIN)Sub-clock oscillation frequency32.76850kHzABSOLUTE MAXIMUM RATINGS–0.3 to Vcc + 0.3V–0.3 to Vcc + 0.3V Unit Symbol ParameterRECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –40 to +85 °C, unless otherwise noted)V Vcc Power source voltageNotes 1.Average output current is the average value of a 100 ms interval.2.The sum of I OL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of I OH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.3.Limits V IH and V IL for X CIN are applied when the sub clock external input selection bit = “1”.4.The maximum value of f(X IN ) = 6 MHz when the main clock division selection bit = “1”.0.8 Vcc 0.8 Vcc 0.5 Vcc000Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc –10–510165V V V V V V mAmAmA mA mA V IH V IH V IH V IL V IL V IL I OH(peak)I OH(avg)I OL(peak)I OL(peak)I OL(avg)High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33High-level output voltage P30 – P32High-level output voltage ELow-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level output voltage P44 – P47, P50 – P53Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33Low-level output voltage P30 – P32Low-level output voltage EHysteresis HOLD , RDY , TA0IN – TA4IN , TB0IN – TB2IN ,INT 0 – INT 2, AD TRG , CTS 0, CTS 1, CTS 2, CLK 0,CLK 1, CLK 2, KI 0 – KI 3Hysteresis RESET Hysteresis X INHysteresis X CIN (When external clock is input)High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87, X IN , RESET , CNVss, BYTELow-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P53, P60, P61, P65 – P67,P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTEUnit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted)Symbol ParameterTest conditions32.54.7V V OH V OH –0.5–0.18V OH3.14.82.63.44.82.6V OH V OL V VV V 20.51.81.5V V OL 0.451.90.430.41.60.40.4V VV0.40.10.20.10.10.060.10.06V CC = 5 V, I OH = –10 mA V CC = 3 V, I OH = –1 mAV CC = 5 V, I OH = –400 µA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OL = 10 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 16 mA V CC = 3 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 VV CC = 5 V, V I = 5 V V CC = 3 V, V I = 3 V V CC = 5 V, V I = 0 V V CC = 3 V, V I = 0 VV I = 0 V,without a pull-up transistor V I = 0 V,with a pull-up transistorWhen clock is stopped.10.70.50.40.40.260.40.26V CC = 5 V V CC = 3 V V CC = 5 VV CC = 3 V –0.25–0.08254–5–4–5–4–1.0 –0.35V V V V µAµAµAmA VV OL V OLV OL V T+ – V T–V T+ – V T–V T+ – V T–V T+ – V T–I IHI ILI ILV RAM Low-level input current P54 – P57, P62 – P64RAM hold voltage Limits Min.Typ.Max.V CC = 5 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 0.75 MHz),f(X CIN ) : Stopped,in operatingV CC = 3 V,f(X IN ) = 12 MHz (square waveform),f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 2)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,in operating (Note 3)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 4)Ta = 25 °C,when clock is stopped Ta = 85 °C,when clock is stoppedmAmAmAµAµAµAµA µAMax.960.812606120Limits Typ.4.530.46303UnitMin.Test conditionsSymbolParameterELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)When single-chip mode, output pins are open, andother pins are V SS .Power source currentI CCLimits Min.Typ.Max. —ResolutionV REF = V CC 10Bits —Absolute accuracy V REF = V CC ± 3LSB R LADDER Ladder resistance V REF = V CC1025k Ωt CONV Conversion time 19.6µs V REF Reference voltage 2.7V CC V V IAAnalog input voltageV REFVSymbol ParameterTest conditionsUnit A–D CONVERTER CHARACTERISTICS(V CC = AV CC = 5 V, V SS = AV SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note))Note. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MHz.Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stopbit = “1”.2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.4. This applies when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.Limits Min.Max.t c External clock input cycle time (Note 1)83ns t w(H)External clock input high-level pulse width (Note 2)33ns t w(L)External clock input low-level pulse width (Note 2)33ns t r External clock rise time 15ns t fExternal clock fall time15nsLimits Min.Max.t su(D–E)Data input setup time 50ns t su(RDY– φ1)RDY input setup time 80ns t su(HOLD– φ1)HOLD input setup time 80ns t h(E–D)Data input hold time 0ns t h( φ1–RDY)RDY input hold time 0ns t h( φ1–HOLD)HOLD input hold timensTIMING REQUIREMENTS (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note 1))Notes 1. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MH Z .2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.External clock inputUnit Symbol ParameterNotes 1. When the main clock division selection bit = “1”, the minimum value of t c = 166 ns.2. When the main clock division selection bit = “1”, values of t w(H) / t c and t w(L) / t c must be set to values from 0.45 through 0.55.Unit Symbol ParameterMemory expansion mode and microprocessor modeSingle-chip modeUnit Symbol ParameterLimits Min.Max.t su(P0D–E)Port P0 input setup time 200ns t su(P1D–E)Port P1 input setup time 200ns t su(P2D–E)Port P2 input setup time 200ns t su(P3D–E)Port P3 input setup time 200ns t su(P4D–E)Port P4 input setup time 200ns t su(P5D–E)Port P5 input setup time 200ns t su(P6D–E)Port P6 input setup time 200ns t su(P7D–E)Port P7 input setup time 200ns t su(P8D–E)Port P8 input setup time 200ns t h(E–P0D)Port P0 input hold time 0ns t h(E–P1D)Port P1 input hold time 0ns t h(E–P2D)Port P2 input hold time 0ns t h(E–P3D)Port P3 input hold time 0ns t h(E–P4D)Port P4 input hold time 0ns t h(E–P5D)Port P5 input hold time 0ns t h(E–P6D)Port P6 input hold time 0ns t h(E–P7D)Port P7 input hold time 0ns t h(E–P8D)Port P8 input hold timensLimits Min.Max.t c(TA)TAi IN input cycle time250ns t w(TAH)TAi IN input high-level pulse width 125ns t w(TAL)TAi IN input low-level pulse width125nsUnit Symbol ParameterTimer A input (Count input in event counter mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width (Note)333ns t w(TAL)TAi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer A input (Gating input in timer mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in one-shot pulse mode)Limits Min.Max.t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in pulse width modulation mode)Limits Min.Max.t c(UP)TAi OUT input cycle time3333ns t w(UPH)TAi OUT input high-level pulse width 1666ns t w(UPL)TAi OUT input low-level pulse width 1666ns t su(UP–T IN )TAi OUT input setup time 666ns t h(T IN –UP)TAi OUT input hold time666nsUnit Symbol ParameterTimer A input (Up-down input in event counter mode)Limits Min.Max.t c(TA) TAj IN input cycle time 2000ns t su(TAj IN –TAj OUT ) TAj IN input setup time 500ns t su(TAj OUT –TAj IN ) TAj OUT input setup time500nsUnit SymbolParameterTimer A input (Two-phase pulse input in event counter mode)Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Limits Min.Max.t c(CK)CLK i input cycle time333ns t w(CKH)CLK i input high-level pulse width 166ns t w(CKL)CLK i input low-level pulse width 166ns t d(C–Q)T X D i output delay time 100ns t h(C–Q)T X D i hold time0ns t su(D–C)R X D i input setup time 65ns t h(C–D)R X D i input hold time75nsLimits Min.Max.t c(TB)TBi IN input cycle time (one edge count)250ns t w(TBH)TBi IN input high-level pulse width (one edge count)125ns t w(TBL)TBi IN input low-level pulse width (one edge count)125ns t c(TB)TBi IN input cycle time (both edges count)500ns t w(TBH)TBi IN input high-level pulse width (both edges count)250ns t w(TBL)TBi IN input low-level pulse width (both edges count)250nsUnit Symbol ParameterTimer B input (Count input in event counter mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse period measurement mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse width measurement mode)Unit Symbol ParameterA-D trigger inputUnit Symbol ParameterSerial I/OUnit Symbol ParameterLimits Min.Max.t w(INH)INT i input high-level pulse width 250ns t w(INL)INT i input low-level pulse width 250ns t w(KIL)KI i input low-level pulse width250nsLimits Min.Max.t c(AD)AD TRG input cycle time (minimum allowable trigger)1333ns t w(ADL)AD TRG input low-level pulse width166nsNote. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.External interrupt INT i input, key input interrupt KI i inputDATA FORMULASTimer A input (Gating input in timer mode)8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)LimitsMin. Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timet w(TAH)TAi IN input high-level pulse width t w (TAL )TAi IN input low-level pulse widthns ns ns8 ! 1092 • f(f 2)Timer A input (External trigger input in one-shot pulse mode)LimitsMin.Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timensTimer B input (In pulse period measurement mode or pulse width measurement mode)Limits Min.Max.Symbol ParameterUnit ns ns nst c(TB)TBi IN input cycle timet w(TBH)TBi IN input high-level pulse width t w(TBL)TBi IN input low-level pulse width8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)Note. f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.SWITCHING CHARACTERISTICS(V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85°C, f(X IN) = 12 MHz, unless otherwise noted (Note))2Fig. 2 Measuring circuit for ports P0 – P8 and φ 1Memory expansion mode and microprocessor modeCC SS IN2.No wait : Wait bit = “1”.Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.Address output delay timeAddress output delay timeAddress hold timeALE pulse widthAddress output set up timeAddress hold timeALE output delay timeData output delay time Data hold timeE pulse widthFloating start delay time Floating release delay timeNo wait Wait 1Wait 0Memory expansion mode and microprocessor modeBus timing data formulas (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz (Max., Note), unless otherwise noted)90101 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)ns ns ns ns ns ns ns ns ns ns No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 01 ! 1092 · f(f 2)ns ns nsns ns ns 941 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)4 ! 1092 · f(f 2)ns ns 1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)– 63– 68– 63– 88– 43– 43– 43– 73– 73– 43– 43– 43– 35– 35– 30– 63– 68– 63– 68– 50– 50Unit SymbolParameterLimitsWait modeMin.Max.t d(An–E)t d(A–E)t h(E–An)t w(ALE)t su(A–ALE)t h(ALE–A)t d(ALE–E)t d(E–DQ)t h(E–DQ)t w(EL)t pxz(E–DZ)t pzx(E–DZ)No wait Wait 1Wait 0BHE output delay timeR/W output delay timet d(BHE–E)t d(R/W–E)t h(E–BHE)t h(E–R/W)t d(E– φ 1)φ 1 output delay timeR/W hold timeBHE hold time030ns ns ns ns ns ns nsnsNotes 1.This applies when the main-clock division selection bit = “0”.2.f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.TIMING DIAGRAMt w(H)t d(E–P0Q)t d(E–P2Q)t d(E–P3Q)t d(E–P4Q)t d(E–P5Q)t d(E–P6Q)t d(E–P7Q)t d(E–P8Q)Port P0 outputPort P0 inputPort P1 outputPort P1 inputPort P2 outputPort P2 inputPort P3 outputPort P3 inputEX INPort P4 outputPort P4 inputPort P5 outputPort P5 inputPort P6 outputPort P6 inputPort P7 outputPort P7 inputPort P8 outputPort P8 inputt su(P0D–E)t h(E–P0D)t d(E–P1Q)t r t f t w(L)t ct su(P1D–E)t h(E–P1D)t su(P2D–E)t h(E–P2D)t su(P3D–E)t h(E–P3D)t su(P4D–E)t h(E–P4D)t su(P5D–E)t h(E–P5D)t su(P6D–E)t h(E–P6D)t su(P7D–E)t h(E–P7D)t su(P8D–E)t h(E–P8D)TAi IN input TAi OUT inputt c(TA)t w(TAH)t w(TAL)t c(UP)t w(UPH)t w(UPL)t h(T IN–UP)t su(UP–T IN) TAi OUT input(Up-down input)TAi IN input(when count by falling)TAi IN input(when count by rising)In event count modeTAj IN input TAj OUT inputt c(TA)t su(TAj IN–TAj OUT)t su(TAj IN–TAj OUT)t su(TAj OUT–TAj IN)t su(TAj OUT–TAj IN)In event counter mode(When two-phase pulse input is selected)t c(TB)t w(TBH)t w(TBL) TBi IN inputt c(AD)t w(ADL)t c(CK)t w(CKH)t w(CKL)t w(INL) t w(KNL)t d(C–Q)t SU(D–C)t h(C–D) t w(INH)AD TRG inputCLK iTxD iRxD iINTi inputKli inputt h(C–Q)。

4,000 h @ +105 °C∆ Capacitance ±15% ESR 175% of limit DCL 100% of limit 1,000 h @ 105 °C∆ Capacitance ±15% ESR 150% of limit DCL 200% of limit10 to 55 Hz, 0.06” and 10 g, 2 h ea of 3 planesType 361R capacitors are for industrial applications from –40 °C to +105 °C. They deliver excellent ripple capability and low ESR and ESL. Also available with three mounting leads. For three leads, change Type designation from 361R to 366R.Highlights• Excellent Ripple Capability • Low ESR and ESL • High ValueSpecificationsOperating Temperature:Rated Voltage:Capacitance:Leakage Current:Ripple Current Multipliers:Load Life:Shelf Life:Vibration:–40 °C to +105 °C 6.3 to 450 Vdc7 to 18,000 µF ± 20%≤0.002 CV µF +25 °C, 6.3 to 160 Vdc ≤0.02 CV µF +25 °C, 200 to 450 Vdc Ambient Temperature45 °C 55 °C 65 °C 75 °C 85 °C 95 °C 105 °C 2.001.601.401.251.000.790.550 Hz60 Hz 120 Hz 360 Hz 1 kHz 5 kHz 10 kHz & up 6.3 & 10 V 0.910.93 1.00 1.06 1.08 1.09 1.0916 to 25 V0.850.88 1.00 1.12 1.18 1.21 1.2235 V & up0.770.821.001.211.321.371.38Outline DrawingsComplies with the EU Directive 2002/95/EC requirement restricting the use of Lead (Pb), Mercury (Hg), Cadmium (Cd), Hexavalent chromium (Cr(VI)), PolyBrominated Biphenyls (PBB) andPolyBrominated Diphenyl Ethers (PBDE).Part Numbering System361R TypeEEpoxy End Seal2InsulationLVCase Code6R3VoltageMTolerance183Capacitance(blank) = no epoxyE = Epoxy0 = None2 = PVC6R3 = 6.3 Vdc063 = 63 VdcM = ±20%U = –10 + 75%100 = 10 µF101 = 100 µF183 = 18000 µF361R or 366RNominal Insulated Insulated S T Lead Diam. Weight Case D x L D x L Epoxy Seal ± 0.6± 0.5mm AWG g Code(mm)(mm)(mm)(mm) (mm)EG12.5 x 20.0 13.0 x 21.5 13.0 x 23.0 5.0 2.50.8120 3.8 EK12.5 x 25.0 13.0 x 26.5 13.0 x 29.0 5.0 2.50.8120 4.5 EM12.5 x 26.5 13.0 x 28.0 13.0 x 29.5 5.0 2.50.8120 4.7 EN12.5 x 33.5 13.0 x 34.2 13.0 x 36.0 5.0 2.50.8120 5.8 ER12.5 x 42.5 13.0 x 43.7 13.0 x 45.5 5.0 2.50.81207.3 FK16.0 x 25.0 16.5 x 26.2 16.5 x 27.9 7.5 3.750.81207.2 FF16.0 x 32.0 16.5 x 33.5 16.5 x 36.0 7.5 3.750.81209.4 FN 16.0 x 33.5 16.5 x 34.2 16.5 x 36.0 7.5 3.750.81209.5 FQ 16.0 x 36.0 16.5 x 37.5 16.5 x 40.0 7.5 3.750.812010.6 FV 16.0 x 40.0 16.5 x 41.7 16.5 x 42.4 7.5 3.750.812011.9 LQ 18.0 x 36.0 18.5 x 37.5 18.5 x 40.0 7.5 3.750.812013.4 LV 18.0 x 40.0 18.5 x 42.0 18.5 x 43.0 7.5 3.750.812014.9 HH 22.0 x 22.0 22.5 x 23.5 22.5 x 26.0 10.0 5.00.812011.0 HK 22.0 x 25.0 22.5 x 26.2 22.5 x 27.9 10.0 5.00.812013.5 HG 22.0 x 30.0 22.5 x 32.5 22.5 x 34.0 10.0 5.00.812015.1Typical Performance CurvesL incl. Sleeve & Epoxy Seal - MillimetersESR Max. 120 Hz 25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)ESR Max.120 Hz25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)Cap. (µF)CatalogPart NumberCap.(µF)CatalogPart Number6.3 Vdc (8 Vdc Surge) 20 Vdc (25 Vdc Surge)2200361R222M6R3EG2 0.205 1.13012.5 x 20 1000361R102M020EG2 0.2000.97012.5 x 20 3300361R332M6R3EK2 0.140 1.44012.5 x 25 1500361R152M020EK2 0.133 1.30012.5 x 25 3900361R392M6R3EM2 0.131 1.38012.5 x 26.5 2200361R222M020EM2 0.103 1.51012.5 x 26.5 4700361R472M6R3EN2 0.098 1.84012.5 x 33.5 2700361R272M020EN2 0.084 1.84012.5 x 33.5 6800361R682M6R3ER2 0.075 2.16012.5 x 42.5 3300361R332M020FK2 0.076 2.00016 x 25 6800361R682M6R3FK2 0.084 2.00016 x 25 3300361R332M020HH2 0.076 2.32022 x 22 6800361R682M6R3HH2 0.091 2.20022 x 22 3900361R392M020ER2 0.065 2.32012.5 x 42.5 8200361R822M6R3HK2 0.075 2.33022 x 25 3900361R392M020HK2 0.065 2.50022 x 25 10000361R103M6R3FF2 0.068 2.33016 x 32 4700361R472M020FF2 0.060 2.48016 x 32 10000361R103M6R3HG2 0.046 3.29022 x 30 5600361R562M020FQ2 0.055 2.72016 x 36 12000361R123M6R3FQ2 0.062 2.55016 x 36 6800361R682M020FV2 0.053 2.90016 x 40 12000361R123M6R3FV2 0.058 2.75016 x 40 6800361R682M020HG2 0.047 3.33022 x 30 15000361R153M6R3HV2 0.044 3.42022 x 40 8200361R822M020LQ2 0.047 3.18018 x 36 15000361R153M6R3LQ2 0.053 2.99018 x 36 10000361R103M020HV2 0.044 3.75022 x 40 18000361R183M6R3LV2 0.049 3.24018 x 40 10000361R103M020LV2 0.044 3.28018 x 4010 Vdc (12.5 Vdc Surge)25 Vdc (32 Vdc Surge)1500361R152M010EG2 0.2100.94712.5 x 20 820361R821M025EG2 0.2800.86012.5 x 20 2200361R222M010EK2 0.158 1.33012.5 x 25 1000361R102M025EK2 0.230 1.08012.5 x 25 2700361R272M010EM2 0.144 1.42012.5 x 26.5 1200361R122M025EM2 0.190 1.15012.5 x 26.5 3300361R332M010EN2 0.115 1.76012.5 x 33.5 1800361R182M025EN2 0.128 1.55012.5 x 33.5 4700361R472M010ER2 0.083 2.25012.5 x 42.5 2200361R222M025FK2 0.121 1.66016 x 25 4700361R472M010FK2 0.093 2.00016 x 25 2200361R222M025HH2 0.121 1.84022 x 22 4700361R472M010HH2 0.094 2.17022 x 22 2700361R272M025ER2 0.096 2.00012.5 x 42.5 5600361R562M010HK2 0.074 2.54022 x 25 3300361R332M025FF2 0.091 2.08016 x 32 6800361R682M010FF2 0.073 2.44016 x 32 3300361R332M025HK2 0.091 2.23022 x 25 8200361R822M010FQ2 0.063 2.95016 x 36 3900361R392M025FK2 0.081 2.36016 x 36 8200361R822M010HG2 0.052 3.17022 x 30 4700361R472M025FV2 0.071 2.56016 x 40 10000361R103M010FV2 0.059 3.00016 x 40 4700361R472M025HG2 0.071 2.75022 x 30 12000361R123M010HV2 0.046 3.39022 x 40 4700361R472M025LQ2 0.071 2.71018 x 36 12000361R123M010LQ2 0.056 3.05018 x 36 5600361R562M025LV2 0.065 2.83018 x 40 15000361R153M010LV2 0.051 3.40018 x 40 6800361R682M025HV2 0.053 3.61022 x 4016 Vdc (20 Vdc Surge) 35 Vdc (44 Vdc Surge)1000361R102M016EG2 0.2650.94212.5 x 20 680361R681M035EG2 0.2870.85012.5 x 20 1800361R182M016EK2 0.156 1.35012.5 x 25 1000361R102M035EK2 0.199 1.20012.5 x 25 2200361R222M016EM2 0.147 1.41012.5 x 26.5 1200361R122M035EM2 0.190 1.25012.5 x 26.5 3300361R332M016EN2 0.108 1.79012.5 x 33.5 1500361R152M035EN2 0.133 1.57012.5 x 33.5 3300361R332M016FK2 0.100 1.88016 x 25 1800361R182M035FK2 0.133 1.62016 x 25 3300361R332M016HH2 0.100 2.08022 x 22 1800361R182M035HH2 0.110 1.84022 x 22 4700361R472M016ER2 0.084 2.20012.5 x 42.5 2200361R222M035ER2 0.106 1.90012.5 x 42.5 4700361R472M016FF2 0.077 2.28016 x 32 2200361R222M035FF2 0.106 2.00016 x 32 4700361R472M016HK2 0.082 2.43022 x 25 2700361R272M035FQ2 0.086 2.33016 x 36 6800361R682M016FQ2 0.066 2.67016 x 36 2700361R272M035HK2 0.086 2.18022 x 25 6800361R682M016FV2 0.064 2.70016 x 40 3300361R332M035FV2 0.080 2.38016 x 40 6800361R682M016HG2 0.014 3.11022 x 30 3300361R332M035HG2 0.081 2.57022 x 30 7800361R782M016LQ2 0.060 2.80018 x 36 3300361R332M035LQ2 0.080 2.40018 x 36 9000361R902M016HV2 0.011 3.59022 x 40 4700361R472M035HV2 0.064 3.27022 x 40 10000361R103M016LV2 0.053 3.00018 x 40 4700361R472M035LV2 0.064 2.70018 x 40ESR Max. 120 Hz 25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)ESR Max.120 Hz25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)Cap. (µF)CatalogPart NumberCap.(µF)CatalogPart Number50 Vdc (63 Vdc Surge) 100 Vdc (125 Vdc Surge)330361R331M050EG2 0.4430.76012.5 x 20 100361R101M100EG2 1.6500.35512.5 x 20 470361R471M050EK2 0.3430.96012.5 x 25 120361R121M100EK2 1.3200.45012.5 x 25 560361R561M050EM2 0.266 1.05012.5 x 26.5 150361R151M100EM2 1.1000.50012.5 x 26.5 820361R821M050EN2 0.180 1.38012.5 x 33.5 220361R221M100EN2 0.7500.66612.5 x 33.5 820361R821M050HH2 0.190 1.56022 x 22 220361R221M100HH2 0.7500.76022 x 22 1000361R102M050FK2 0.156 1.53016 x 25 270361R271M100ER2 0.6100.75012.5 x 42.5 1200361R122M050ER2 0.125 1.81012.5 x 42.5 270361R271M100HK2 0.5200.95022 x 25 1500361R152M050FF2 0.101 2.14016 x 32 330361R331M100FK2 0.5000.87516 x 25 1500361R152M050HK2 0.106 2.16022 x 25 390361R391M100FF2 0.420 1.01016 x 32 1800361R182M050FQ2 0.083 2.44016 x 36 470361R471M100FQ2 0.350 1.15016 x 36 1800361R182M050HG2 0.084 2.49022 x 30 470361R471M100FV2 0.350 1.25016 x 40 2200361R222M050LQ2 0.081 2.64018 x 36 470361R471M100HG2 0.351 1.25022 x 30 2200361R222M050FV2 0.081 2.60016 x 40 560361R561M100LQ2 0.290 1.37018 x 36 2700361R272M050HV2 0.067 3.19022 x 40 680361R681M100HV2 0.241 1.69022 x 40 2700361R272M050LV2 0.065 3.04018 x 40 680361R681M100LV2 0.240 1.57018 x 4063 Vdc (79 Vdc Surge) 160 Vdc (185 Vdc Surge)330361R331M063EG2 0.4500.76012.5 x 20 33361R330M160EG2 5.0000.20012.5 x 20 470361R471M063EK2 0.3180.96012.5 x 25 47361R470M160EK2 3.5000.25012.5 x 25 470361R471M063EM2 0.3180.98012.5 x 26.5 56361R560M160EM2 2.9500.28012.5 x 26.5 560361R561M063EN2 0.268 1.15012.5 x 33.5 82361R820M160EN2 2.0000.38012.5 x 33.5 680361R681M063ER2 0.183 1.54012.5 x 42.5 100361R101M160ER2 1.6500.46012.5 x 42.5 820361R821M063FK2 0.220 1.31016 x 25 100361R101M160FK2 1.6500.43016 x 25 820361R821M063HH2 0.220 1.42022 x 22 100361R101M160HH2 1.6500.47522 x 22 1200361R122M063FF2 0.150 1.70016 x 32 150361R151M160FF2 1.1000.58016 x 32 1200361R122M063HK2 0.150 1.81022 x 25 150361R151M160HK2 1.1000.61022 x 25 1500361R152M063FQ2 0.125 1.98016 x 36 180361R181M160FQ2 0.9200.66516 x 36 1500361R152M063HG2 0.099 2.31022 x 30 220361R221M160FV2 0.7500.77016 x 40 1800361R182M063FV2 0.100 2.30016 x 40 220361R221M160HG2 0.7510.84022 x 30 1800361R182M063LQ2 0.100 2.58018 x 36 220361R221M160LQ2 0.7500.80018 x 36 2200361R222M063HV2 0.072 2.99022 x 40 270361R271M160LV2 0.6100.92018 x 40 2200361R222M063LV2 0.083 2.70018 x 40 330361R331M160HV2 0.5120.99022 x 4075 Vdc (90 Vdc Surge) 200 Vdc (225 Vdc Surge)150361R151M075EG2 1.0700.45012.5 x 20 27361R270M200EG2 5.9000.17512.5 x 20 220361R221M075EK2 0.7270.58012.5 x 25 47361R470M200EK2 3.6000.25012.5 x 25 270361R271M075EM2 0.6000.65012.5 x 26.5 56361R560M200EM2 3.0000.28012.5 x 26.5 390361R391M075EN2 0.4100.87012.5 x 33.5 68361R680M200EN2 2.5000.34012.5 x 33.5 470361R471M075FK2 0.340 1.00016 x 25 82361R820M200FK2 2.0000.39016 x 25 470361R471M075HH2 0.340 1.04022 x 22 82361R820M200HH2 2.0000.43022 x 22 560361R561M075ER2 0.285 1.16012.5 x 42.5 100361R101M200ER2 1.6500.45012.5 x 42.5 680361R681M075FF2 0.235 1.32016 x 32 120361R121M200FF2 1.3800.52016 x 32 680361R681M075HK2 0.235 1.31022 x 25 120361R121M200HK2 1.3800.54522 x 25 820361R821M075FQ2 0.195 1.52016 x 36 150361R151M200FQ2 1.1000.60016 x 36 1000361R102M075FV2 0.160 1.66016 x 40 180361R181M200HG2 1.0000.73022 x 30 1000361R102M075HG2 0.161 1.81022 x 30 220361R221M200FV2 0.7600.76016 x 40 1000361R102M075LQ2 0.160 1.70018 x 36 220361R221M200LQ2 0.7600.79018 x 36 1200361R122M075LV2 0.133 1.90018 x 40 270361R271M200HV2 0.7810.94022 x 40 1500361R152M075HV2 0.107 2.53022 x 40 270361R271M200LV2 0.6200.91018 x 40ESR Max. 120 Hz 25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)ESR Max.120 Hz25ºC (Ω)Ripple A120 Hz85ºC (A)Nom SizeD X L(mm)Cap. (µF)CatalogPart NumberCap.(µF)CatalogPart Number250 Vdc (300 Vdc Surge) 33361R330M350HH2 5.0000.27522 x 2218361R180M250EG2 9.2000.14512.5 x 20 39361R390M350FF2 4.2500.29516 x 32 27361R270M250EK2 6.1000.19012.5 x 25 47361R470M350FQ2 3.5000.34016 x 36 33361R330M250EM2 5.0000.21512.5 x 26.5 47361R470M350HK2 3.5000.34022 x 25 47361R470M250EN2 3.5000.28512.5 x 33.5 56361R560M350FV2 2.9500.38516 x 40 47361R470M250FK2 3.5000.29516 x 25 56361R560M350HG2 2.9500.42022 x 30 56361R560M250ER2 2.9500.34512.5 x 42.5 68361R680M350LQ2 2.4200.44518 x 36 56361R560M250HH2 2.9500.35022 x 22 82361R820M350HV2 2.0000.59022 x 40 68361R680M250FF2 2.4200.39016 x 32 82361R820M350LV2 2.0000.50018 x 40 82361R820M250FQ2 2.0000.45016 x 36 400 Vdc (450 Vdc Surge)82361R820M250HK2 2.0000.45022 x 25 8361R080M400EK2 20.000.10512.5 x 25 100361R101M250FV2 1.6500.51516 x 40 12361R120M400EM2 13.800.12512.5 x 26.5 120361R121M250HG2 1.3800.62022 x 30 18361R180M400EN2 9.1000.17512.5 x 33.5 120361R121M250LQ2 1.3800.58518 x 36 22361R220M400FK2 7.5000.20016 x 25 150361R151M250LV2 1.1000.68518 x 40 27361R270M400ER2 6.1000.23512.5 x 42.5 180361R181M250HV2 0.9210.88022 x 40 33361R330M400FF2 5.0000.27516 x 32 300 Vdc (365 Vdc Surge)33361R330M400HH2 5.0000.27522 x 22 12361R120M300EG2 13.800.12012.5 x 20 39361R390M400FQ2 4.2000.31516 x 36 18361R180M300EK2 9.1500.15512.5 x 25 39361R390M400HK2 4.2000.31522 x 25 22361R220M300EM2 7.5000.17512.5 x 26.5 47361R470M400FV2 3.5000.35516 x 40 33361R330M300EN2 5.0000.24012.5 x 33.5 47361R470M400HG2 3.5100.39022 x 30 33361R330M300FK2 5.0000.24516 x 25 56361R560M400LQ2 2.9500.40018 x 36 39361R390M300HH2 4.2500.29522 x 22 68361R680M400HV2 2.4200.53022 x 40 47361R470M300ER2 3.5000.31512.5 x 42.5 68361R680M400LV2 2.4200.46518 x 40 47361R470M300FF2 3.5000.32516 x 32 450 Vdc (500 Vdc Surge)56361R560M300FQ2 2.9500.37516 x 36 7361R070M450EK2 20.000.10012.5 x 25 56361R560M300HK2 2.9500.37522 x 25 10361R100M450EM2 16.500.12012.5 x 26.5 68361R680M300FV2 2.4200.43016 x 40 15361R150M450EN2 11.000.16512.5 x 33.5 68361R680M300HG2 2.4200.48022 x 30 18361R180M450FK2 9.1000.18516 x 25 82361R820M300LQ2 2.0000.48518 x 36 22361R220M450ER2 7.5000.21512.5 x 42.5 100361R101M300HV2 1.6500.65022 x 40 27361R270M450FF2 6.1000.24516 x 32 100361R101M300LV2 1.6500.55518 x 40 27361R270M450HH2 6.1000.24522 x 22 350 Vdc (400 Vdc Surge) 33361R330M450FQ2 5.0000.28516 x 36 10361R100M350EK2 16.500.11512.5 x 25 33361R330M450HK2 5.0000.30022 x 25 15361R150M350EM2 11.000.14512.5 x 26.5 39361R390M450FV2 4.2000.32516 x 40 22361R220M350EN2 7.5000.19512.5 x 33.5 39361R390M450HG2 4.2000.35022 x 30 27361R270M350FK2 6.1000.22516 x 25 47361R470M450LQ2 3.5000.36518 x 36 33361R330M350ER2 5.0000.26512.5 x 42.5 56361R560M450LV2 2.9500.41518 x 4068361R680M450HV2 2.4500.53022 x 40。

DLL-Off to DLL-On ProcedureTo switch from DLL-off to DLL-on (with required frequency change) during self refresh:1.Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAMODT resistors (R TT(NOM)) must be in High-Z before self refresh mode is entered.)2.Enter self refresh mode; wait until t CKSRE/t CKSRE_PAR are satisfied.3.Change frequency (following the guidelines in the Input Clock Frequency Changesection).4.Wait until a stable clock is available for at least t CKSRX at device inputs.5.Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-tered HIGH until t DLLK timing from the subsequent DLL RESET command is sat-isfied. In addition, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW or HIGH until t DLLK timing from the subsequent DLL RESET command is satisfied. If R TT(NOM) disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care."6.Wait t XS or t XS_ABORT, depending on bit 9 in MR4, then set MR1 bit A0 to 0 to en-able the DLL.7.Wait t MRD, then set MR0 bit A8 to 1 to start DLL reset.8.Wait t MRD, then set mode registers with appropriate values; an update of CL,CWL, and WR may be necessary. After t MOD is satisfied from any proceeding MRS command, a ZQCL command can also be issued during or after t DLLK.9.Wait for t MOD to complete. Remember to wait t DLLK after DLL RESET before ap-plying any command requiring a locked DLL. In addition, wait for t ZQoper in case a ZQCL command was issued.The device is ready for the next command.Figure 19: DLL Switch Sequence from DLL-Off to DLL-OnCK_cCK_tTa Tb0Tb1Tc Td Te0Te1Tf TgTh Don’t CareTime Break CKEEnter self refresh Exit self refreshODTAddressNotes: 1.Starting in the idle state.2.Enter SR.3.Change frequency.4.Clock must be stable t CKSRX.5.Exit SR.6.Set DLL to on by setting MR1 to A0 = 0.7.Update mode registers.8.Issue any valid command.Input Clock Frequency ChangeAfter the device is initialized, it requires the clock to be stable during almost all states of normal operation. This means that after the clock frequency has been set and is in the stable state, the clock period is not allowed to deviate except for what is allowed by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequen-cy can be changed from one stable clock rate to another stable clock rate only when in self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequen-cy.After the device has been successfully placed in self refresh mode and t CKSRE/t CKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Follow-ing a "Don’t Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to t CKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifica-tions must still be met as outlined in SELF REFRESH Operation.For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5,and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode,READ and WRITE preamble, Command Address Latency, and data rate values.When the clock rate is being increased (faster), the MR settings that require additional clocks should be updated prior to the clock rate being increased. In particular, the PL latency must be disabled when the clock rate changes, ie. while in self refresh mode. For example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6.The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self re-fresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].If the MR settings that require additional clocks are updated after the clock rate has been increased, for example. after exiting self refresh mode, the required MR settings must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is RESET. If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration,the updating of the required MR settings may be deferred to the next time the DRAM enters the IDLE state.If MR6 is issued prior to self refresh entry for the new data rate value, DLL will relock automatically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0must be issued to reset the DLL.The device input clock frequency can change only within the minimum and maximum operating frequency specified for the particular speed grade. Any frequency change be-low the minimum operating frequency would require the use of DLL-on mode to DLL-off mode transition sequence (see DLL-On/Off Switching Procedures).4Gb: x8, x16 Automotive DDR4 SDRAM Input Clock Frequency ChangeWrite LevelingFor better signal integrity, DDR4 memory modules use fly-by topology for the com-mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re-duced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain t DQSS, t DSS, and t DSH specifications. Therefore, the device supports a write leveling feature to allow the controller to compensate for skew. This feature may not be required under some system conditions, provided the host can maintain the t DQSS, t DSS, and t DSH specifications.The memory controller can use the write leveling feature and feedback from the device to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con-troller involved in the leveling must have an adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab-lished though this exercise would ensure the t DQSS specification. Besides t DQSS, t DSS and t DSH specifications also need to be fulfilled. One way to achieve this is to combine the actual t DQSS in the application with an appropriate duty cycle and jitter on the DQS signals. Depending on the actual t DQSS in the application, the actual values for t DQSL and t DQSH may have to be better than the absolute limits provided in the AC Timing Parameters section in order to satisfy t DSS and t DSH specifications. A conceptual tim-ing of this scheme is shown below.Figure 20: Write Leveling Concept, Example 1diff_DQSdiff_DQSDQ diff_DQSDQ T0T1T2T3T4T5CK_cCK_tT6T7CK_c CK_tSource Destination DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.All data bits carry the leveling feedback to the controller across the DRAM configura-tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently.Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to-clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)-to-clock relationship.4Gb: x8, x16 Automotive DDR4 SDRAM Write Leveling。

i s c l a i me r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t ef o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i ng s u i t a b i l i t y o r r e l i a b i l i t y o f th e s e p r o d u c t s f o r s p e ci f i c u s e r a p p l i c a t i o n sMainRange of productModicon TM3Product or component typeInput/Output analog module Range compatibility Modicon M251Modicon M241Modicon M221Analogue input number 4Analogue input type Current, analogue input range: 4...20 mACurrent, analogue input range: 0...20 mAVoltage, analogue input range: 0...10 VVoltage, analogue input range: - 10...10 VAnalogue output number 2Analogue output type4...20 mA current0...20 mA current0...10 V voltage- 10...10 V voltage ComplementaryAnalogue input resolution11 bits + sign 12 bits Permissible continuous overload13 V voltage 40 mA current Input impedance<= 50 Ohm current >= 1 MOhm voltage Analogue output resolution11 bits + sign 12 bits LSB value 2.44 mV, analogue input: 0...10 V voltage4.88 mV, analogue input: - 10...10 V voltage4.88 µA, analogue input: 0...20 mA current3.91 µA, analogue input:4...20 mA currentLoad type ResistiveLoad impedance ohmic1 kOhm voltage300 Ohm currentOutput ripple20 mVCross talk<= 1 LSB[Us] rated supply voltage24 V DCSupply voltage limits20.4...28.8 VType of cable<= 30 m twisted shielded pairs cable for input/output circuitCurrent consumption45 mA at 5 V DC (no load) via bus connector55 mA at 5 V DC (full load) via bus connector55 mA at 24 V DC (no load) via external supply100 mA at 24 V DC (full load) via external supplyLocal signalling 1 LED green for PWRElectrical connection10 x 1.5 mm² removable screw terminal block with pitch 3.81 mm adjustment for inputs10 x 1.5 mm² removable screw terminal block with pitch 3.81 mm adjustment for inputs, outputs andsupplyInsulation500 V AC between output and internal logic500 V AC between input and internal logic1500 V AC between input and supply1500 V AC between output and supplyMarking CESurge withstand 1 kV for power supply with common mode protection conforming to EN/IEC 61000-4-50.5 kV for power supply with differential mode protection conforming to EN/IEC 61000-4-51 kV for I/O with common mode protection conforming to EN/IEC 61000-4-50.5 kV for I/O with differential mode protection conforming to EN/IEC 61000-4-5Mounting support Top hat type TH35-15 rail conforming to IEC 60715Top hat type TH35-7.5 rail conforming to IEC 60715Plate or panel with fixing kitHeight90 mmDepth70 mmWidth23.6 mmProduct weight0.11 kgEnvironmentStandards EN/IEC 61131-2EN/IEC 61010-2-201Resistance to electrostatic discharge 4 kV on contact conforming to EN/IEC 61000-4-28 kV in air conforming to EN/IEC 61000-4-2Resistance to electromagnetic fields10 V/m at 80 MHz...1 GHz conforming to EN/IEC 61000-4-33 V/m at 1.4 GHz...2 GHz conforming to EN/IEC 61000-4-31 V/m at2 GHz...3 GHz conforming to EN/IEC 61000-4-3Resistance to magnetic fields30 A/m at 50...60 Hz conforming to EN/IEC 61000-4-8Resistance to fast transients 1 kV I/O conforming to EN/IEC 61000-4-4Resistance to conducted disturbances, induced by radio frequency fields 10 V at 0.15...80 MHz conforming to EN/IEC 61000-4-63 V at spot frequency (2, 3, 4, 6.2, 8.2, 12.6, 16.5, 18.8, 22, 25 MHz) conforming to Marine specification (LR, ABS, DNV, GL)Electromagnetic emission Radiated emissions, test level: 40 dBμV/m QP class A (10 m at 30...230 MHz) conforming to EN/IEC55011Radiated emissions, test level: 47 dBμV/m QP class A (10 m at 230 MHz...1 GHz) conforming to EN/IEC 55011Immunity to microbreaks10 msAmbient air temperature for operation-10...55 °C (horizontal installation)-10...35 °C (vertical installation)2Offer Sustainability Sustainable offer statusGreen Premium product RoHS (date code: YYWW)Compliant - since 1415 - Schneider Electric declaration of conformity Schneider Electric declaration of conformity REAChReference not containing SVHC above the threshold Reference not containing SVHC above the threshold Product environmental profile Available Product environmental Product end of life instructionsAvailableEnd of life manual(*)8.5 mm/0.33 in when the clamp is pulled out.Incorrect Mounting(1)Install a mounting strip Mounting Hole LayoutWiring Diagram (Current / Voltage)(*)Type T fuse (1)Current/Voltage analog output device (2)Current/Voltage analog input device。