M37733EHBXXXFP中文资料

DESCRIPTIONThe M37733MHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on.Its strong points are the low power dissipation, the low supply voltage, and the small package.FEATURESq Number of basic instructions (103)q Memory size ROM ................................................. 124 KbytesRAM ................................................ 3968 bytes q Instruction execution timeThe fastest instruction at 12 MHz frequency ...................... 333 ns q Single power supply ...................................................... 2.7–5.5 V q Low power dissipation (At 3 V supply voltage, 12 MHz frequency)............................................ 9 mW (Typ.)q Interrupts ............................................................ 19 types, 7 levels q Multiple-function 16-bit timer ................................................. 5 + 3 q Serial I/O (UART or clock synchronous) . (3)q10-bit A-D converter .............................................. 8-channel inputs q12-bit watchdog timerq Programmable input/output(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) (68)q Clock generating circuit ........................................ 2 circuits built-in q Small package......................80-pin plastic molded fine-pitch QFP(80P6D-A;0.5 mm lead pitch) APPLICATIONControl devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on.Control devices for general industrial equipment such as communication equipment, and so on.FUNCTIONS OF M37733MHLXXXHPMemory sizeInput/Output ports Multi-function timersInterruptsClock generating circuit Power dissipation Parameter FunctionsNumber of basic instructions103Instruction execution time333 ns (the fastest instruction at external clock 12 MHz frequency) ROM124 KbytesRAM3968 bytesP0 – P2, P4 – P88-bit ! 8P34-bit ! 1TA0, TA1, TA2, TA3, TA416-bit ! 5TB0, TB1, TB216-bit ! 3Serial I/O(UART or clock synchronous serial I/O) ! 3A-D converter10-bit ! 1 (8 channels)Watchdog timer12-bit ! 13 external types, 16 internal typesEach interrupt can be set to the priority level (0 – 7.)2 circuits built-in (externally connected to a ceramic resonator or aquartz-crystal oscillator)Supply voltage 2.7 – 5.5 V9 mW (at 3 V supply voltage, external clock 12 MHz frequency)22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency)Input/Output voltage 5 VOutput current 5 mAMemory expansion Maximum 16 MbytesOperating temperature range–40 to 85 °CDevice structure CMOS high-performance silicon gate processPackage80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) Input/Output characteristicPIN DESCRIPTIONX IN Clock input Input X OUTClock output Output PinName Input/Output FunctionsVcc,Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss.Vss CNVssCNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode.RESETReset input Input When “L” level is applied to this pin, the microcomputer enters the reset state.These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal oscillator between X IN and X OUT . When an external clock is used, the clock source should be connected to the X IN pin, and the X OUT pin should be left open.EEnable output Output This pin functions as the enable signal output pin which indicates the access status in the internal bus. When output level of E signal is “L”, data/instruction read or data write is performed.BYTE External data InputIn the memory expansion mode or the microprocessor mode, this pin determines whether the bus widthexternal data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”selection input signal is input and an 8-bit width when “H” signal is input.AVcc,Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.AVss source input V REF Reference Input This is reference voltage input pin for the A-D converter.voltage input P00 – P07I/O port P0I/OIn the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset.In the memory expansion mode or the microprocessor mode, these pins output address (A 0 – A 7).P10 – P17I/O port P1I/OIn the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D 8 – D 15) is input/output or an address (A 8 – A 15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A 8 – A 15) is output.P20 – P27I/O port P2I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D 0 – D 7) is input/output or an address (A 16 – A 23) is output.P30 – P33I/O port P3I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion mode or the microprocessor mode, R/W , BHE , ALE, and HLDA signals are output.P40 – P47I/O port P4I/OIn the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port.P50 – P57I/O port P5I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI 0 – KI 3).P60 – P67I/O port P6I/O In addition to having the same functions as port P0 in the single-chip mode, these pins alsofunction as I/O pins for timer A4, input pins for external interrupt input (INT 0 – INT 2) and input pins for timers B0 to B2. P67 also functions as sub-clock φ SUB output pin.P70 – P77I/O port P7I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76and P77 have the function as the output pin (X COUT ) and the input pin (X CIN ) of the sub-clock(32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the X COUT and X CIN pins,connect a resonator or an oscillator between the both.P80 – P87I/O port P8I/OIn addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1.SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERN o t i c e :T S o me p a r a m e t r i BASIC FUNCTION BLOCKSThe M37733MHLXXXHP has the same functions as theM37733MHBXXXFP except for the package and the reset circuit.Refer to the section on the M37733MHBXXXFP.RESET CIRCUIT_____The microcomputer is released from the reset state when the RESET pin is returned to “H” level after holding it at “L” level with the power source voltage at 2.7 – 5.5 V. Program execution starts at the address formed by setting address A 23 – A 16 to 0016, A 15 – A 8 to the contents of address FFFF 16, and A 7 – A 0 to the contents of address FFFE 16.Figure 3 shows an example of a reset circuit. When the stabilized clock is input from the external to the main-clock oscillation circuit,the reset input voltage must be 0.55 V or less when the power source voltage reaches 2.7 V. When a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from “L” to “H” after the main-clock oscillation is fully stabilized.The status of the internal registers during reset is the same as the M37733MHBXXXFP’s.ADDRESSING MODESThe M37733MHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details.MACHINE INSTRUCTION LISTThe M37733MHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details.DATA REQUIRED FOR MASK ROM ORDERINGPlease send the following data for mask orders.(1) M37733MHLXXXHP mask ROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets)N o t i c e :T S o me p a r a m e t r i SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERSymbolParameter ConditionsRatings Unit Vcc Power source voltage–0.3 to +7V AVcc Analog power source voltage–0.3 to +7V V I _____Input voltage RESET , CNVss, BYTE–0.3 to +12V Input voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,V REF , X INOutput voltage P00 – P07, P10 – P17, P20 – P27,P30 – P33, P40 – P47, P50 – P57,P60 – P67, P70 – P77, P80 – P87,_X OUT , EP d Power dissipation Ta = 25 °C 200mW T opr Operating temperature –40 to +85°C T stgStorage temperature–65 to +150°CV IV O Limits Min.Typ.Max.f(X IN ) : Operating2.7 5.5f(X IN ) : Stopped, f(X CIN ) = 32.768 kHz2.75.5AVcc Analog power source voltage Vcc V Vss Power source voltage0V AVss Analog power source voltageVHigh-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)High-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTE, X CIN (Note 3)Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode)Low-level input voltage P10 – P17, P20 – P27(in memory expansion mode and microprocessor mode)High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level peak output current P44 – P47, P50 – P53Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87I OL(avg)Low-level average output current P44 – P47, P50 – P5312mA f(X IN )Main-clock oscillation frequency (Note 4)12MHz f(X CIN)Sub-clock oscillation frequency32.76850kHzABSOLUTE MAXIMUM RATINGS–0.3 to Vcc + 0.3V–0.3 to Vcc + 0.3V Unit Symbol ParameterRECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –40 to +85 °C, unless otherwise noted)V Vcc Power source voltageNotes 1.Average output current is the average value of a 100 ms interval.2.The sum of I OL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,the sum of I OL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of I OH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.3.Limits V IH and V IL for X CIN are applied when the sub clock external input selection bit = “1”.4.The maximum value of f(X IN ) = 6 MHz when the main clock division selection bit = “1”.0.8 Vcc 0.8 Vcc 0.5 Vcc000Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc –10–510165V V V V V V mAmAmA mA mA V IH V IH V IH V IL V IL V IL I OH(peak)I OH(avg)I OL(peak)I OL(peak)I OL(avg)High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33High-level output voltage P30 – P32High-level output voltage ELow-level output voltage P00 – P07, P10 – P17, P20 – P27, P33,P40 – P43, P54 – P57, P60 – P67, P70 – P77,P80 – P87Low-level output voltage P44 – P47, P50 – P53Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33Low-level output voltage P30 – P32Low-level output voltage EHysteresis HOLD , RDY , TA0IN – TA4IN , TB0IN – TB2IN ,INT 0 – INT 2, AD TRG , CTS 0, CTS 1, CTS 2, CLK 0,CLK 1, CLK 2, KI 0 – KI 3Hysteresis RESET Hysteresis X INHysteresis X CIN (When external clock is input)High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P57, P60 – P67, P70 – P77,P80 – P87, X IN , RESET , CNVss, BYTELow-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33,P40 – P47, P50 – P53, P60, P61, P65 – P67,P70 – P77, P80 – P87, X IN , RESET , CNVss, BYTEUnit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted)Symbol ParameterTest conditions32.54.7V V OH V OH –0.5–0.18V OH3.14.82.63.44.82.6V OH V OL V VV V 20.51.81.5V V OL 0.451.90.430.41.60.40.4V VV0.40.10.20.10.10.060.10.06V CC = 5 V, I OH = –10 mA V CC = 3 V, I OH = –1 mAV CC = 5 V, I OH = –400 µA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OH = –10 mA V CC = 5 V, I OH = –400 µA V CC = 3 V, I OH = –1 mA V CC = 5 V, I OL = 10 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 16 mA V CC = 3 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V, I OL = 10 mA V CC = 5 V, I OL = 2 mA V CC = 3 V, I OL = 1 mA V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 V V CC = 5 V V CC = 3 VV CC = 5 V, V I = 5 V V CC = 3 V, V I = 3 V V CC = 5 V, V I = 0 V V CC = 3 V, V I = 0 VV I = 0 V,without a pull-up transistor V I = 0 V,with a pull-up transistorWhen clock is stopped.10.70.50.40.40.260.40.26V CC = 5 V V CC = 3 V V CC = 5 VV CC = 3 V –0.25–0.08254–5–4–5–4–1.0 –0.35V V V V µAµAµAmA VV OL V OLV OL V T+ – V T–V T+ – V T–V T+ – V T–V T+ – V T–I IHI ILI ILV RAM Low-level input current P54 – P57, P62 – P64RAM hold voltage Limits Min.Typ.Max.V CC = 5 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 6 MHz),f(X CIN ) = 32.768 kHz,in operating (Note 1)V CC = 3 V,f(X IN ) = 12 MHz (square waveform),(f(f 2) = 0.75 MHz),f(X CIN ) : Stopped,in operatingV CC = 3 V,f(X IN ) = 12 MHz (square waveform),f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 2)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,in operating (Note 3)V CC = 3 V,f(X IN ) : Stopped,f(X CIN ) = 32.768 kHz,when a WIT instruction is executed (Note 4)Ta = 25 °C,when clock is stopped Ta = 85 °C,when clock is stoppedmAmAmAµAµAµAµA µAMax.960.812606120Limits Typ.4.530.46303UnitMin.Test conditionsSymbolParameterELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)When single-chip mode, output pins are open, andother pins are V SS .Power source currentI CCLimits Min.Typ.Max. —ResolutionV REF = V CC 10Bits —Absolute accuracy V REF = V CC ± 3LSB R LADDER Ladder resistance V REF = V CC1025k Ωt CONV Conversion time 19.6µs V REF Reference voltage 2.7V CC V V IAAnalog input voltageV REFVSymbol ParameterTest conditionsUnit A–D CONVERTER CHARACTERISTICS(V CC = AV CC = 5 V, V SS = AV SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note))Note. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MHz.Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stopbit = “1”.2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.4. This applies when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.Limits Min.Max.t c External clock input cycle time (Note 1)83ns t w(H)External clock input high-level pulse width (Note 2)33ns t w(L)External clock input low-level pulse width (Note 2)33ns t r External clock rise time 15ns t fExternal clock fall time15nsLimits Min.Max.t su(D–E)Data input setup time 50ns t su(RDY– φ1)RDY input setup time 80ns t su(HOLD– φ1)HOLD input setup time 80ns t h(E–D)Data input hold time 0ns t h( φ1–RDY)RDY input hold time 0ns t h( φ1–HOLD)HOLD input hold timensTIMING REQUIREMENTS (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz, unless otherwise noted (Note 1))Notes 1. This applies when the main clock division selection bit = “0” and f(f 2) = 6 MH Z .2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.External clock inputUnit Symbol ParameterNotes 1. When the main clock division selection bit = “1”, the minimum value of t c = 166 ns.2. When the main clock division selection bit = “1”, values of t w(H) / t c and t w(L) / t c must be set to values from 0.45 through 0.55.Unit Symbol ParameterMemory expansion mode and microprocessor modeSingle-chip modeUnit Symbol ParameterLimits Min.Max.t su(P0D–E)Port P0 input setup time 200ns t su(P1D–E)Port P1 input setup time 200ns t su(P2D–E)Port P2 input setup time 200ns t su(P3D–E)Port P3 input setup time 200ns t su(P4D–E)Port P4 input setup time 200ns t su(P5D–E)Port P5 input setup time 200ns t su(P6D–E)Port P6 input setup time 200ns t su(P7D–E)Port P7 input setup time 200ns t su(P8D–E)Port P8 input setup time 200ns t h(E–P0D)Port P0 input hold time 0ns t h(E–P1D)Port P1 input hold time 0ns t h(E–P2D)Port P2 input hold time 0ns t h(E–P3D)Port P3 input hold time 0ns t h(E–P4D)Port P4 input hold time 0ns t h(E–P5D)Port P5 input hold time 0ns t h(E–P6D)Port P6 input hold time 0ns t h(E–P7D)Port P7 input hold time 0ns t h(E–P8D)Port P8 input hold timensLimits Min.Max.t c(TA)TAi IN input cycle time250ns t w(TAH)TAi IN input high-level pulse width 125ns t w(TAL)TAi IN input low-level pulse width125nsUnit Symbol ParameterTimer A input (Count input in event counter mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width (Note)333ns t w(TAL)TAi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer A input (Gating input in timer mode)Limits Min.Max.t c(TA)TAi IN input cycle time (Note)666ns t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in one-shot pulse mode)Limits Min.Max.t w(TAH)TAi IN input high-level pulse width 166ns t w(TAL)TAi IN input low-level pulse width166nsUnit Symbol ParameterTimer A input (External trigger input in pulse width modulation mode)Limits Min.Max.t c(UP)TAi OUT input cycle time3333ns t w(UPH)TAi OUT input high-level pulse width 1666ns t w(UPL)TAi OUT input low-level pulse width 1666ns t su(UP–T IN )TAi OUT input setup time 666ns t h(T IN –UP)TAi OUT input hold time666nsUnit Symbol ParameterTimer A input (Up-down input in event counter mode)Limits Min.Max.t c(TA) TAj IN input cycle time 2000ns t su(TAj IN –TAj OUT ) TAj IN input setup time 500ns t su(TAj OUT –TAj IN ) TAj OUT input setup time500nsUnit SymbolParameterTimer A input (Two-phase pulse input in event counter mode)Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Limits Min.Max.t c(CK)CLK i input cycle time333ns t w(CKH)CLK i input high-level pulse width 166ns t w(CKL)CLK i input low-level pulse width 166ns t d(C–Q)T X D i output delay time 100ns t h(C–Q)T X D i hold time0ns t su(D–C)R X D i input setup time 65ns t h(C–D)R X D i input hold time75nsLimits Min.Max.t c(TB)TBi IN input cycle time (one edge count)250ns t w(TBH)TBi IN input high-level pulse width (one edge count)125ns t w(TBL)TBi IN input low-level pulse width (one edge count)125ns t c(TB)TBi IN input cycle time (both edges count)500ns t w(TBH)TBi IN input high-level pulse width (both edges count)250ns t w(TBL)TBi IN input low-level pulse width (both edges count)250nsUnit Symbol ParameterTimer B input (Count input in event counter mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse period measurement mode)Limits Min.Max.t c(TB)TBi IN input cycle time (Note)666ns t w(TBH)TBi IN input high-level pulse width (Note)333ns t w(TBL)TBi IN input low-level pulse width (Note)333nsUnit Symbol ParameterTimer B input (Pulse width measurement mode)Unit Symbol ParameterA-D trigger inputUnit Symbol ParameterSerial I/OUnit Symbol ParameterLimits Min.Max.t w(INH)INT i input high-level pulse width 250ns t w(INL)INT i input low-level pulse width 250ns t w(KIL)KI i input low-level pulse width250nsLimits Min.Max.t c(AD)AD TRG input cycle time (minimum allowable trigger)1333ns t w(ADL)AD TRG input low-level pulse width166nsNote. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.Note. Limits change depending on f(X IN ). Refer to “DATA FORMULAS”.External interrupt INT i input, key input interrupt KI i inputDATA FORMULASTimer A input (Gating input in timer mode)8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)LimitsMin. Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timet w(TAH)TAi IN input high-level pulse width t w (TAL )TAi IN input low-level pulse widthns ns ns8 ! 1092 • f(f 2)Timer A input (External trigger input in one-shot pulse mode)LimitsMin.Max.Symbol ParameterUnit t c(TA)TAi IN input cycle timensTimer B input (In pulse period measurement mode or pulse width measurement mode)Limits Min.Max.Symbol ParameterUnit ns ns nst c(TB)TBi IN input cycle timet w(TBH)TBi IN input high-level pulse width t w(TBL)TBi IN input low-level pulse width8 ! 1092 • f(f 2)4 ! 1092 • f(f 2)4 ! 1092 • f(f 2)Note. f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.SWITCHING CHARACTERISTICS(V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85°C, f(X IN) = 12 MHz, unless otherwise noted (Note))2Fig. 2 Measuring circuit for ports P0 – P8 and φ 1Memory expansion mode and microprocessor modeCC SS IN2.No wait : Wait bit = “1”.Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.Address output delay timeAddress output delay timeAddress hold timeALE pulse widthAddress output set up timeAddress hold timeALE output delay timeData output delay time Data hold timeE pulse widthFloating start delay time Floating release delay timeNo wait Wait 1Wait 0Memory expansion mode and microprocessor modeBus timing data formulas (V CC = 2.7 – 5.5 V, V SS = 0 V, Ta = –40 to +85 °C, f(X IN ) = 12 MHz (Max., Note), unless otherwise noted)90101 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)ns ns ns ns ns ns ns ns ns ns No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 0No wait Wait 1Wait 01 ! 1092 · f(f 2)ns ns nsns ns ns 941 ! 1092 · f(f 2)1 ! 1092 · f(f 2)2 ! 1092 · f(f 2)4 ! 1092 · f(f 2)ns ns 1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)3 ! 1092 · f(f 2)1 ! 1092 · f(f 2)1 ! 1092 · f(f 2)– 63– 68– 63– 88– 43– 43– 43– 73– 73– 43– 43– 43– 35– 35– 30– 63– 68– 63– 68– 50– 50Unit SymbolParameterLimitsWait modeMin.Max.t d(An–E)t d(A–E)t h(E–An)t w(ALE)t su(A–ALE)t h(ALE–A)t d(ALE–E)t d(E–DQ)t h(E–DQ)t w(EL)t pxz(E–DZ)t pzx(E–DZ)No wait Wait 1Wait 0BHE output delay timeR/W output delay timet d(BHE–E)t d(R/W–E)t h(E–BHE)t h(E–R/W)t d(E– φ 1)φ 1 output delay timeR/W hold timeBHE hold time030ns ns ns ns ns ns nsnsNotes 1.This applies when the main-clock division selection bit = “0”.2.f(f 2) represents the clock f 2 frequency.For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.TIMING DIAGRAMt w(H)t d(E–P0Q)t d(E–P2Q)t d(E–P3Q)t d(E–P4Q)t d(E–P5Q)t d(E–P6Q)t d(E–P7Q)t d(E–P8Q)Port P0 outputPort P0 inputPort P1 outputPort P1 inputPort P2 outputPort P2 inputPort P3 outputPort P3 inputEX INPort P4 outputPort P4 inputPort P5 outputPort P5 inputPort P6 outputPort P6 inputPort P7 outputPort P7 inputPort P8 outputPort P8 inputt su(P0D–E)t h(E–P0D)t d(E–P1Q)t r t f t w(L)t ct su(P1D–E)t h(E–P1D)t su(P2D–E)t h(E–P2D)t su(P3D–E)t h(E–P3D)t su(P4D–E)t h(E–P4D)t su(P5D–E)t h(E–P5D)t su(P6D–E)t h(E–P6D)t su(P7D–E)t h(E–P7D)t su(P8D–E)t h(E–P8D)TAi IN input TAi OUT inputt c(TA)t w(TAH)t w(TAL)t c(UP)t w(UPH)t w(UPL)t h(T IN–UP)t su(UP–T IN) TAi OUT input(Up-down input)TAi IN input(when count by falling)TAi IN input(when count by rising)In event count modeTAj IN input TAj OUT inputt c(TA)t su(TAj IN–TAj OUT)t su(TAj IN–TAj OUT)t su(TAj OUT–TAj IN)t su(TAj OUT–TAj IN)In event counter mode(When two-phase pulse input is selected)t c(TB)t w(TBH)t w(TBL) TBi IN inputt c(AD)t w(ADL)t c(CK)t w(CKH)t w(CKL)t w(INL) t w(KNL)t d(C–Q)t SU(D–C)t h(C–D) t w(INH)AD TRG inputCLK iTxD iRxD iINTi inputKli inputt h(C–Q)。

Siemens Industry, Inc.M3FB…LX… SeriesTechnical InstructionsDocument No. CA2N4721E-P25December 4, 2019Modulating Control Valve for Hot Gas ControlDescription Modulating control valves with magnetic actuator for hot gas applications for capacity control of refrigeration units and for heat recovery systems. Features• Quick positioning time (less than 1 second).• High stroke resolution (> 1:200) and control accuracy. • Hermetically sealed. • Versatile electrical interface.• Port AB → A closed when de-energized. •Heavy-duty and maintenance-free.ApplicationThe M3FB...LX... three-way or straight-through valves with magnetic actuator are used for modulating capacity control of refrigeration units and for heat recovery. They may be used as hot gas diverting or straight-through valves.Suitable for organic safety refrigerants such as R22, R134a, R404A, R407C and R507. Not suitable for flammable refrigerants or ammonia (R717).Product NumbersSee Table 1.Warning/Caution NotationsWARNING:Personal injury or loss of life may occur if you do not perform a procedure as specified.CAUTION:Equipment damage may occur if you do not follow a procedure as specified.Technical Instructions M3FB…LX… Series Modulating Control Valve Document Number CA2N4721E-P25 for Hot Gas Control December 4, 2019Ordering The valve body and magnetic actuator form one integral unit and cannot be separated.The M3FB...LX... valve and the ZM.../A module must be ordered separately.When placing an order, specify the quantity, product number and product description.Example :1 M3FB15LX/A control valve and 1 ZM101/A module.Key :∆p max= Maximum admissible differential pressure across the valve’s control path (AB →A valve) for the entire actuating range.S NA= Rated apparent power for transformer selection.P med= Typical power consumption.Cv = Flow rate tolerance ±10%.Technical Design The armature or magnetic core is designed as a floating component within the pressuresystem, so that no external shaft gland is required. Therefore, leakage losses commonwith moving parts are avoided. The valve cross-section allows for easy flow whetherthe valve is fully or only partially open. This reduces pressure losses and ensures quietoperation.The valves are fitted with extended female solder unions, making pipe connectionseasy.Mechanical Design The control signal is converted in the ZM.../A module into a phase cut signal, whichgenerates a magnetic field in the coil. This causes the only moving part, the armature,to change its position in accordance with the interacting forces (magnetic field, counter-spring, hydraulics, and so on). The armature responds rapidly to any change in signal,transferring the corresponding movement directly to the control disc, enabling fastchanges in load to be corrected quickly and accurately.The valve is normally closed. A spring closes the valve automatically if the power isswitched off or fails.Page 2Siemens Industry, Inc.M3FB…LX… Series Modulating Control Valve Technical Instructions for Hot Gas Control Document Number CA2N4721E-P25December 4, 2019Sizing See Table 2.NOTE: Correct valve sizing (to ensure a sufficiently large pressure drop ∆p v100 acrossthe fully open valve) is the key to the correct operation of a refrigeration unit.All the components must be coordinated, and this can be ensured only by therefrigeration specialist.The application examples that follow show the recommended pressure dropin each case.Refrigeration capacity in tonsNominal capacity in tons at evaporation temperature t o = 41°F (5°C)Table 2. Selection Table for Hot-Gas Applications.∆p v100 = Pressure drop across the fully open valve.Siemens Industry, Inc. Page 3Technical InstructionsM3FB…LX… Series Modulating Control ValveDocument Number CA2N4721E-P25 for Hot Gas ControlDecember 4, 2019Page 4Siemens Industry, Inc.Key :t o Evaporation temperature [°F] t c Condensation temperature [°F]t fl Liquid temp. ( t c – degree of sub-cooling) [°F]Q o Refrigeration capacity [tons] m Mass flow of refrigerant [lbs/h] C v s Flow rate [ft 3/h]p v Admissible pressure differential [psi]Figure 1. Selection Chart for Hot-Gas Applications.M3FB…LX… Series Modulating Control Valve Technical Instructionsfor Hot Gas Control Document Number CA2N4721E-P25December 4, 2019Siemens Industry, Inc.Page 5Mounting NotesMounting instructions are enclosed with the valve (Document Number 35548). Wiring instructions are included with the ZM Terminal Housing Module (Document Number 35541).The refrigerant valves can be mounted in any orientation, but upright mounting is preferable.Figure 2. Acceptable Mounting Positions.Arrange the piping so that the valve is not located at a low point where oil could collect. The pipes should be fitted so that the alignment does not distort the valve connections. Support the valve body so that it cannot vibrate. Vibration can lead to burst piping connections. Before soldering the pipes, ensure that the direction of flow through the valve is correct.Figure 3. Piping Alignment.The pipes must be soldered with care. The flame should be large enough to ensure that the junction heats up quickly and the valve does not get too hot. The flame should be directed away from the valve. Cool the valve body with a wet cloth while soldering. Port 2 must be sealed off when the valve is used in a straight-through application.CAUTION:Always switch off the power supply before connecting or disconnecting the ZM... module.Maintenance NotesThe M3FB…LX… valves are maintenance -free. The low friction and robust design ensure long product life. The valve cannot be repaired; it must be replaced as a complete unit.SpecificationsElectricalElectrical interface Only allowed with low voltage(Class 2)Supply voltage 24 Vac for 0 to 10 Vdc and 4 to 20 mA Maximum voltage tolerance +15/–10% Frequency 50 to 60 Hz Control signalsZM101/A 0 to 10 Vdc or 0 to 20V phase cut ZM121/A 4 to 20 mA or 0 to 20V phase cut Input resistance0 to 10 Vdc > 100K ohm 4 to 20 mA< 150 ohmConnection terminalsScrew terminals for 12 AWG wireTechnical InstructionsM3FB…LX… Series Modulating Control ValveDocument Number CA2N4721E-P25 for Hot Gas ControlDecember 4, 2019Page 6 Siemens Industry, Inc.Specifications, ContinuedProduct Specific DataPermissible operating pressure p e max Maximum 623 psi (43 bar) Pressure differential ∆p v max AB → A See Table 1AB → B 116 psi (8 bar)Leakage (at 14.5 psi [1 bar]) AB → A Max. 0.05% C VAB → B Max. 0.5% k CvPermissible media Organic safety refrigerants (R22,R134a, R404a, R40TC, R410A, R507, and so on). Not suitable for ammonia(R717) or flammable refrigerants. Temperature of medium-40°F to 248°F (-40°C to 120°C)Valve characteristic (stroke, k v ) Linear, optimized in low opening range Resolution ∆H / H 100 >1 : 200 (H = stroke)Type of operationModulatingPosition when de-energized AB → A closed OrientationAnyPositioning time <1 secondPipe connectionsInternally soldered Materials (Valve Body)Housing components Steel and CrNi steel Seat/inner valve Brass/CrNi steel Pipe connections CrNi steelGeneral Ambient Conditions Ambient temperature -13°F to 131°F (–25°C to 55°C) Humidity 10 to 100% rhSafetyConformity Meets the requirements for CEmarking.Connection TerminalsWARNING : ZM.../A module used with 0 to 20V phase cut signals:• Do not connect 24 Vac to Terminals 1 and 2.• Connect Terminal 5, (marked " – ") to Terminal 2 on type NKOA terminal modules. ZM101/A (0 to 10 Vdc or 0 to 20V phase cut)ZM121/A (4 to 20 mA or 0 to 20V phase cut)Figure 4. Connection Terminals.M3FB…LX… Series Modulating Control Valve Technical Instructionsfor Hot Gas Control Document Number CA2N4721E-P25December 4, 2019Siemens Industry, Inc. Page 7Application ExamplesThe diagrams shown here are examples only, without installation-specific details. Three-way Hot-gas Bypass Control• For accurate control of evaporators, from 0 to 100% refrigeration capacity. •Suitable for test rooms, laboratory systems, small chilled water units and DXevaporators with a refrigeration capacity of up to approximately 11.4 tons (40 kW). •Recommended pressure drop ∆p v100 across the fully-open valve (control path AB → A): between 7.2 and 14.5 psi (see Figure 1).Example:Refrigeration capacity Qo RefrigerantCondensation temperature tc Evaporation temperature to Liquid temperature tfl Selected valvePressure differential ∆pv across valve6.8 tonsR22104°F (40°C) 41°F (5°C) 95°F (35°C) M3FB15LX/A10.2 psi (0.7 bar)Figure 5. Three-way Hot-Gas Bypass Control Application.Indirect Hot-gas Bypass The control valve throttles the capacity of a compressor stage. The hot gas is injecteddirectly into the evaporator allowing capacity control from 100% to approximately 0%.•Suitable for use in large refrigeration systems in air conditioning applications to prevent unacceptable fluctuations in temperature between compressor stages. •The pressure differential ∆p v100 across the fully-open valve is determined by the condensation pressure at low load minus the pressure upstream of the evaporator. •If details are not provided, the pressure differential ∆pv100 can be assumed to be 58 psi (4 bar).Example :Refrigeration capacity Qo of one compressor stage RefrigerantCondensation temperature full load/low loadEvaporation temperature fullload/low loadLiquid temperature tfl Pressure differential ∆pv (from R22 vapor table) Selected valve Actual capacity8.5 tons R22 113/95°F (45/35°C) 41/59°F (5/15°C) 104/86°F (40/30°C) 81 psi (5.6 bar) M3FB15LX/A Approx. 40 kW M3FB15LX/A Approx. 40 kWFigure 6. Indirect Hot-gas Bypass Application.Technical InstructionsM3FB…LX… Series Modulating Control ValveDocument Number CA2N4721E-P25 for Hot Gas ControlDecember 4, 2019Page 8 Siemens Industry, Inc.Application Examples, ContinuedDirect Hot-gas BypassThe control valve throttles the capacity of a compressor stage. The gas is fed to the suction side of the compressor and cooled by a re-injection valve. Capacity control ranges from 100% to approximately 10%. •Suitable for large refrigeration systems for air conditioning with severalcompressors or compressor stages, and where the evaporator and compressor are some distance apart (attention must be paid to oil return).•The pressure differential ∆p v100 across the fully-open valve is determined by the condensation pressure at low load minus the suction pressure.•If no details are provided, the pressure differential ∆p v100 can be assumed to be 87 psi (6 bar).Example:Refrigerant capacity of one compressor stage RefrigerantCondensation temperature full load/low loadEvaporation temperature full load/low loadLiquid temperature t flPressure differential ∆p v100 (from R22 vapor table) Selected valve11.4 tons R22113°F/95°F (45°C/35°C) 36°F/-50°F (2°C/10°C) 104°F/86°F (40°C/30°C) 94 psi (6.5 bar)M3FB15LX/AFigure 7. Direct Hot-gas Bypass Application.Heat recoveryThe hot-gas diverting valve may be used for modulating recovery of the heat from the condenser, even in the event of high pressure differentials. Recommended pressure drop ∆p v100 across the fully-open valve (control path AB → A): between 0.5 and 1 bar.Example:Refrigeration capacity Q RefrigerantCondensation temperature tc Evaporation temperature to Liquid temperature tfl Selected valveActual pressure drop19.1 tons R134a 122°F (50°C) 36°F (2°C) 113 (45°C) M3FB32LX 10 psi (0.7 bar)Figure 8. Heat Recovery Application.M3FB…LX… Series Modulating Control Valve Technical Instructions for Hot Gas Control Document Number CA2N4721E-P25December 4, 2019 Information in this publication is based on current specifications. The company reserves the right to make changes in specifications and models as design improvements are introduced. Product or company names mentioned herein may be trademarks of their respective owners. © 2019 Siemens Industry, Inc.Siemens Industry, Inc. Smart Infrastructure1000 Deerfield Parkway Buffalo Grove, IL 60089-4513 USA1-847-276-1000Your feedback is important to us. If you havecomments about this document, please send themto ***************************************Document No. CA2N4721E-P25Printed in the USAPage9DimensionsValve Product NumberLine Size ø D L[in]H1[in]H2[in]H3[in]A[in]B[in]C[in]W [mm] [in] [in] [lb]M3FB15LX06/A 15 1/2 5/8 5.91 2.56 0.98 7.24 3.15 3.31 2.64 9.5 M3FB15LX15/A 15 1/2 5/8 5.91 2.56 0.98 7.24 3.15 3.31 2.64 9.5 M3FB15LX/A 15 1/2 5/8 5.91 2.56 0.98 7.24 3.15 3.31 2.64 9.5 M3FB20LX/A 20 3/4 7/8 6.69 2.72 1.18 9.37 3.94 3.70 3.31 19.6 M3FB25LX/A 25 1 1-1/8 7.87 2.83 1.42 9.76 3.94 3.70 3.70 20.9 M3FB32LX 32 1-1/4 1-3/8 9.84 3.58 1.69 9.65 3.94 3.70 3.86 25.1D Pipe connectionsW Weight (including packaging)Figure 9. Dimensions.。

柿饼M3模块硬件手册1.概要信息1.1产品简介柿饼M3是上海睿赛德电子科技有限公司基于柿饼UI开发的一款显示屏板卡，用于提供IoT、智能家居、消费电子等领域的屏幕开发解决方案。

作为柿饼派的升级版本，柿饼M3尺寸小巧，功能强悍，支持丰富的外设通讯接口，可外接传感器或其他主控单元，支持丰富的网络协议和音视频播放，此外，柿饼M3支持FOTA功能，便于远程维护升级。

1.2基本参数●主控：RT1806高性能32位处理器●内置SDRAM：32MB●板载Flash：16MB●支持RGB666接口，支持常见的480*272，800*480，1024*600分辨率●支持UART、SPI、SDIO、IIC通信接口●支持USB-HOST功能可接移动4G模块或U盘●支持音视频播放●支持硬件JPEG解码●支持丰富的网络协议（MQTT、HTTP、HTTPS、WebSocket、TCP）●搭配柿饼UI，界面开发便捷，控件丰富（支持多种常用控件、可支持自定义控件）支持小程序多APP应用●支持FOTA安全升级机制2.模块典型应用框图图示为模块典型应用框图，详细参考电路见参考原理图资料。

3.规格参数模块相关规格参数如下：主要参数最小值典型值最大值单位工作温度-202570℃储存温度-302580℃工作湿度10%60%90%RH供电电压 4.5 5.0 5.5V供电电流90100120mAI/O支持电压 3.0 3.3 3.6VCodec支持电压 2.5 3.8 3.1VUSB支持电压 3.0 3.3 3.6V通信电平 3.3V 静电防护(默认)2（接触）24（空气）KV推荐回流温度：4.尺寸与引脚定义4.1尺寸大小项目参数外形尺寸27mm(长)*27mm（宽）*3.5mm（高）焊盘中心间距 1.27mm焊盘距板边距离 2.7mm注：详细参数见封装资料。

4.2引脚定义图4.3默认引脚定义PIN引脚Symbol符号说明Remark备注1,2,49-64LCD_D22,LCD_D23,LCD_D2-LCD_D21RGB数据接口默认RGB666，详情见示意图3LCD_CLK LCD屏时钟线4LCD_DE LCD屏片选脚5LCD_HSYNC RGB帧同步信号6LCD_VSYNC RGB场同步信号7,8VCC_5V电源供电4.5V-5.5V9,10GND电源地11SDA IIC数据线12SCL IIC时钟线13SD_DETC SD卡使能接口14SPK_SHDN音频使能接口（低有效）15，16U2_RX,U2_TX UART2串口信号输出、输入该串口为控制台,默认参数为1152008N117PWM1LCD背光调节接口18PE5WiFi初始化引脚不使用WiFi功能时，可做通用IO使用19PE4WiFi复位引脚同上20TP_INT/PE3触摸IC初始化引脚不使用触摸功能时，可做通用IO使用21TP_RST/PE2触摸IC复位引脚同上22,23LCD_D0/U0_RX,LCD_D1/U0_TX LCD的D0,D1引脚该串口为预留串口，默认参数为1152008N124，25SDIO_D2,SDIO_D3SD卡的SDIO数据D2,D3引脚26SDIO_CMD SDIO的命令引脚27SDIO_CLK SDIO的时钟引脚28,29SDIO_D0,SDIO_D1SD卡的SDIO数据D0,D1引脚30SPI_MISO/PA3默认为WiFi的SPI引脚不使用WiFi功能时，可做通用IO或SPI使用31SPI_CLK/PA2同上32SPI_MOSI/PA1同上33SPI_CS0/PA0同上34,35USB_DM,USB_DP USB数据线36RESET CPU复位引脚37TV_OUT38,39TV_IN1,TV_IN040LRADC ADC-Key带ADC功能的按键，6位分辨率41FMINL42FMINR43LINEIN44MICIN45,46HPR,HPL音频右/左声道输出47,48HPCOM_FB,HPCOM免责声明上海睿赛德电子科技有限公司随附提供的文档资料旨在提供给您（本公司的客户）使用，仅限于且只能在本公司销售或提供服务的产品上使用。

PRELIMINARYNotice: This is not a final specification.Some parametric limits are subject to change.DESCRIPTIONThe 3803 group (Spec.H QzROM version) is the 8-bit microcomputer based on the 740 family core technology.The 3803 group (Spec.H QzROM version) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the serial interface functions, 8/16-bit timer, A/D converter and D/A converter.FEATURES•Basic machine-language instructions (71)•Minimum instruction execution time .......................... 0.24 µs(at 16.8 MHz oscillation frequency)•Memory sizeQzROM .................................................... 16 K to 48 K bytes RAM ..................................................................... 2048 bytes •Programmable input/output ports (56)•Software pull-up resistors............................................Built-in •Interrupts .............................................. 21 sources, 16 vectors(external 8, internal 12, software 1)•Timers ...................................................................... 16-bit × 18-bit × 4(with 8-bit prescaler)•Serial interface.........8-bit × 2 (UART or Clock-synchronized)8-bit × 1 (Clock-synchronized)•PWM ....................................... 8-bit × 1 (with 8-bit prescaler)•A/D converter ........................................ 10-bit × 16 channels(8-bit reading enabled)•D/A converter ............................................ 8-bit × 2 channels •Watchdog timer ....................................................... 16-bit × 1•LED direct drive port.. (8)•Clock generating circuit ............................. Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator)•Power source voltage[In high-speed mode]At 16.8 MHz oscillation frequency....................4.5 to 5.5 V At 12.5 MHz oscillation frequency....................4.0 to 5.5 V At 8.4 MHz oscillation frequency......................2.7 to 5.5 V At 4.2 MHz oscillation frequency......................2.2 to 5.5 V At 2.1 MHz oscillation frequency......................2.0 to 5.5 V [In middle-speed mode]At 16.8 MHz oscillation frequency....................4.5 to 5.5 V At 12.5 MHz oscillation frequency....................2.7 to 5.5 V At 8.4 MHz oscillation frequency......................2.2 to 5.5 V At 6.3 MHz oscillation frequency......................1.8 to 5.5 V [In low-speed mode]At 32 kHz oscillation frequency.........................1.8 to 5.5 V •Power dissipationIn high-speed mode........................................... 40 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................ 45 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage)•Operating temperature range .............................−20 to 85 °C •Packages SP.............................PRDP0064BA-A (64-pin 750 mil SDIP) HP....................PLQP0064KB-A (64-pin 10 × 10 mm LQFP) KP....................PLQP0064GA-A (64-pin 14 × 14 mm LQFP) APPLICATIONHousehold products, Consumer electronics, etc.3803 Group (Spec.H QzROM version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0166-0110Rev.1.10Nov 14, 2005Currently support products are listed below.NOTES:1.This means a shipment of which User ROM has been programmed.2.The user ROM area of a blank product is blank.Table 1Support productsProduct name QzROM size (bytes)ROM size for User in ( )RAM size (bytes)Package RemarksM38039G4H-XXXHP 16384(16254)2048PLQP0064KB-A QzROM version(Programmed shipment) (1)M38039G4H-XXXKP PLQP0064GA-A M38039G6H-XXXHP 24576(24446)PLQP0064KB-A M38039G6H-XXXKP PLQP0064GA-A M38039G8H-XXXHP 32768(32638)PLQP0064KB-A M38039G8H-XXXKP PLQP0064GA-A M38039GCH-XXXHP 49152(49022)PLQP0064KB-A M38039GCH-XXXKP PLQP0064GA-A M38039G4HSP 16384(16254)PRDP0064BA-A QzROM version (blank) (2)M38039G4HHP PLQP0064KB-A M38039G4HKP PLQP0064GA-A M38039G6HSP 24576(24446)PRDP0064BA-A M38039G6HHP PLQP0064KB-A M38039G6HKP PLQP0064GA-A M38039G8HSP 32768(32638)PRDP0064BA-A M38039G8HHP PLQP0064KB-A M38039G8HKP PLQP0064GA-A M38039GCHSP 49152(49022)PRDP0064BA-A M38039GCHHP PLQP0064KB-A M38039GCHKP PLQP0064GA-ANOTES:1.This means a shipment of which User ROM has been programmed.2.The user ROM area of a blank product is blank.Table 2List of package (Spec.H QzROM version) (PLQP0064KB-A/PLQP0064GA-A)PackageProduct name QzROM size (bytes)ROM size for User in ( )RAM size (bytes)RemarksPLQP0064KB-AM38039G4H-XXXHP 16384 (16254)2048QzROM version (Programmed shipment)(1)M38039G4HHP QzROM version (blank)(2)M38039G6H-XXXHP 24576 (24446)QzROM version (Programmed shipment)(1)M38039G6HHP QzROM version (blank)(2)M38039G8H-XXXHP 32768 (32638)QzROM version (Programmed shipment)(1)M38039G8HHP QzROM version (blank)(2)M38039GCH-XXXHP 49152 (49022)QzROM version (Programmed shipment)(1)M38039GCHHP QzROM version (blank)(2)PLQP0064GA-AM38039G4H-XXXKP 16384 (16254)2048QzROM version (Programmed shipment)(1)M38039G4HKP QzROM version (blank)(2)M38039G6H-XXXKP 24576 (24446)QzROM version (Programmed shipment)(1)M38039G6HKP QzROM version (blank)(2)M38039G8H-XXXKP 32768 (32638)QzROM version (Programmed shipment)(1)M38039G8HKP QzROM version (blank)(2)M38039GCH-XXXKP 49152 (49022)QzROM version (Programmed shipment)(1)M38039GCHKPQzROM version (blank)(2)Table 3List of package (Spec.H QzROM version) (PRDP0064BA-A)Package Product nameQzROM size (bytes)ROM size for User in ( )RAM size(bytes)RemarksPRDP0064BA-A M38039G4HSP16384 (16254)2048QzROM version (blank)(1) M38039G6HSP24576 (24446)M38039G8HSP32768 (32638)M38039GCHSP49152 (49022)NOTES:1.The user ROM area of a blank product is blank.PIN DESCRIPTIONTable 4Pin descriptionPin Name FunctionsFunction except a port function V CC, V SS Power source•Apply voltage of 1.8 V − 5.5 V to V CC, and 0 V to V SS.CNV SS CNV SS input•This pin controls the operation mode of the chip and is shared with the V PP pin which is thepower source input pin for programming the built-in QzROM.•Normally connected to V SS.V REF Referencevoltage•Reference voltage input pin for A/D and D/A converters.AV SS Analog powersource •Analog power source input pin for A/D and D/A converters.•Connect to V SS.RESET Reset input•Reset input pin for active “L”.X IN Clock input•Input and output pins for the clock generating circuit.•Connect a ceramic resonator or quartz-crystal oscillator between the X IN and X OUT pins to setthe oscillation frequency.•When an external clock is used, connect the clock source to the X IN pin and leave the X OUT pinopen.X OUT Clock outputP00/AN8−P07/AN15I/O port P0•8-bit CMOS I/O port.•I/O direction register allows each pin to be individuallyprogrammed as either input or output.•CMOS compatible input level.•CMOS 3-state output structure.•Pull-up control is enabled in a bit unit.•P20− P27 (8 bits) are enabled to output large current forLED drive.•A/D converter input pinP10/INT41P11/INT01I/O port P1•Interrupt input pin P12−P17P20-P27I/O port P2P30/DA1 P31/DA2I/O port P3•8-bit CMOS I/O port.•I/O direction register allows each pin to be individuallyprogrammed as either input or output.•CMOS compatible input level.•P30, P31, P34− P37 are CMOS 3-state output structure.•P32, P33 are N-channel open-drain output structure.•Pull-up control of P30, P31, P34− P37 is enabled in a bit unit.•D/A converter input pinP32, P33P34/R X D3P35/T X D3P36/S CLK3P37/S RDY3•Serial I/O3 function pinP40/INT40/X COUT P41/INT00/X CIN I/O port P4•8-bit CMOS I/O port.•I/O direction register allows each pin to be individuallyprogrammed as either input or output.•CMOS compatible input level.•CMOS 3-state output structure.•Pull-up control is enabled in a bit unit.•Interrupt input pin•Sub-clock generating I/O pin(resonator connected)P42/INT1P43/INT2•Interrupt input pinP44/R X D1P45/T X D1P46/S CLK1•Serial I/O1 function pinP47/S RDY1/CNTR2•Serial I/O1, timer Z function pin P50/S IN2P51/S OUT2P52/S CLK2P53/S RDY2I/O port P5•Serial I/O2 function pinP54/CNTR0•Timer X function pinP55/CNTR1•Timer Y function pinP56/PWM•PWM output pinP57/INT3•Interrupt input pinP60/AN0−P67/AN7I/O port P6•A/D converter input pinPART NUMBERINGGROUP EXPANSIONRenesas Technology expands the 3803 group (Spec.H QzROM version) as follows.Memory TypeSupport for QzROM version.Memory Size•QzROM size................................................16 K to 48 K bytes •RAM size..................................................................2048 bytes Packages•PRDP0064BA-A..................64-pin shrink plastic-molded DIP •PLQP0064KB-A...............0.5 mm-pitch plastic molded LQFP •PLQP0064GA-A...............0.8 mm-pitch plastic molded LQFPGROUP DESCRIPTIONThe QzROM version of 3803 group (Spec.H) is under development. The mask ROM version and the flash memory version are mass production. Currently support products are listed below.Table 5Support products (mask ROM version and flash memory version of Spec.H)Product name ROM/flash memory size(bytes)ROM size for User in ( )RAM size(bytes)PackageRemarksM38034M4H-XXXSP 16384(16254)640PRDP0064BA-A (64P4B)Mask ROM versionM38034M4H-XXXFP PRQP0064GA-A (64P6N-A)M38034M4H-XXXHP PLQP0064KB-A (64P6Q-A)M38034M4H-XXXKP PLQP0064GA-A (64P6U-A)M38037M6H-XXXSP 24576(24446)1024PRDP0064BA-A (64P4B)M38037M6H-XXXFP PRQP0064GA-A (64P6N-A)M38037M6H-XXXHP PLQP0064KB-A (64P6Q-A)M38037M6H-XXXKP PLQP0064GA-A (64P6U-A)M38037M8H-XXXSP 32768(32638)1024PRDP0064BA-A (64P4B)M38037M8H-XXXFP PRQP0064GA-A (64P6N-A)M38037M8H-XXXHP PLQP0064KB-A (64P6Q-A)M38037M8H-XXXKP PLQP0064GA-A (64P6U-A)M38039MCH-XXXSP 49152(49022)2048PRDP0064BA-A (64P4B)M38039MCH-XXXFP PRQP0064GA-A (64P6N-A)M38039MCH-XXXHP PLQP0064KB-A (64P6Q-A)M38039MCH-XXXKP PLQP0064GA-A (64P6U-A)M38039MFH-XXXSP 61440(61310)2048PRDP0064BA-A (64P4B)M38039MFH-XXXFP PRQP0064GA-A (64P6N-A)M38039MFH-XXXHP PLQP0064KB-A (64P6Q-A)M38039MFH-XXXKP PLQP0064GA-A (64P6U-A)M38039MFH-XXXWG PTLG0064JA-A (64F0G)M38039FFHSP 614402048PRDP0064BA-A (64P4B)Flash memory version (V CC =2.7−5.5V)M38039FFHFP PRQP0064GA-A (64P6N-A)M38039FFHHP PLQP0064KB-A (64P6Q-A)M38039FFHKP PLQP0064GA-A (64P6U-A)M38039FFHWG PTLG0064JA-A (64F0G)M38039FFSP PRDP0064BA-A (64P4B)Flash memory version (V CC =4.0−5.5V)M38039FFFP PRQP0064GA-A (64P6N-A)M38039FFHPPLQP0064KB-A (64P6Q-A)FUNCTIONAL DESCRIPTIONCENTRAL PROCESSING UNIT (CPU)The 3803 group (Spec.H QzROM version) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set.Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used.The STP, WIT, MUL, and DIV instructions can be used.[Accumulator (A)]The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator.[Index Register X (X)]The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.[Index Register Y (Y)]The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.[Stack Pointer (S)]The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts.The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0”, the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”.The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure.7.Store registers other than those described in Figure.6 with program when the user needs them during interrupts or subroutine calls (see Table 6).[Program Counter (PC)]The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PC L. It is used to indicate the address of the next instruction to be executed.Table 6Push and pop instructions of accumulator or processor status registerPush instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP[Processor status register (PS)]The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.Bit 0: Carry flag (C)The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.Bit 1: Zero flag (Z)The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.Bit 2: Interrupt disable flag (I)The I flag disables all interrupts except for the interrupt generated by the BRK instruction.Interrupts are disabled when the I flag is “1”.Bit 3: Decimal mode flag (D)The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”.Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic.Bit 4: Break flag (B)The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.Bit 5: Index X mode flag (T)When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.Bit 6: Overflow flag (V)The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to −128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.Bit 7: Negative flag (N)The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.Table 7Set and clear instructions of each bit of processor status registerC flag Z flag I flagD flag B flag T flag V flag N flag Set instruction SEC−SEI SED−SET−−Clear instruction CLC−CLI CLD−CLT CLV−[CPU Mode Register (CPUM)] 003B16The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc.The CPU mode register is allocated at address 003B16.MISRG(1)Bit 0 of address 001016: Oscillation stabilizing timeset after STP instruction released bitWhen the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting “1” to bit 0 of MISRG (address 001016).However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction.Figure.9 shows the structure of MISRG.(2)Bits 1, 2, 3 of address 001016: Middle-speed ModeAutomatic Switch FunctionIn order to switch the clock mode of an MCU which has a sub-clock, the following procedure is necessary:set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode).However, the 3803 group (Spec.H QzROM version) has the built-in function which automatically switches from low to middle-speed mode by program.•Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to “1” in the condition that the middle-speed mode automatic switch set bit is “1” while operating in low-speed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016).MEMORY•Special Function Register (SFR) AreaThe Special Function Register area in the zero page contains control registers such as I/O ports and timers.•RAMThe RAM is used for data storage and for stack area of subroutine calls and interrupts.•ROMThe first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. In the QzROM version, 1 byte of address FFDB16 is also a reserved area.•Interrupt Vector AreaThe interrupt vector area contains reset and interrupt vectors.•Zero PageAccess to this area with only 2 bytes is possible in the zero page addressing mode.•Special PageAccess to this area with only 2 bytes is possible in the special page addressing mode.•ROM Code Protect Address (address FFDB16) Address FFDB16, which is the reserved ROM area of QzROM, is the ROM code protect address. “0016” or “FE16” is written into this address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When “0016” or “FE16” is set to the ROM code protect address, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer.As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer.The protect can be performed, dividing twice. The protect area 1 is from the beginning address of ROM to address “EFFF16”. As for the QzROM product shipped after writing, “0016” (protect enabled to all area), “FE16” (protect enabled to the protect area 1) or “FF16” (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing.The writing of “0016”, “FE16” or “FF16” can be selected as ROM option setup (“MASK option” written in the mask file converter) when ordering.<Notes>Since the contents of RAM are undefined at reset, be sure to set an initial value before use.I/O PORTSThe I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port.When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.By setting the port P0 pull-up control register (address 0FF016)to the port P6 pull-up control register (address 0FF616) ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports.NOTES:1.Refer to the applicable sections how to use double-function ports as function I/O ports.2.Make sure that the input level at each pin is either 0 V or V CC during execution of the STP instruction.When an input level is at an intermediate potential, a current will flow from V CC to V SS through the input-stage gate.Table 8 I/O port functionPinNameInput/OutputI/O Structure Non-Port Function Related SFRsRef.No.P00/AN 8−P07/AN 15Port P0Input/output, individual bits CMOS compatible input level CMOS 3-stateoutputA/D converter inputAD/DA control register (1)P10/INT 41P11/INT 01Port P1External interrupt inputInterrupt edge selection register (2)P12−P17(3)P20/LED 0−P27/LED 7Port P2P30/DA 1P31/DA 2Port P3D/A converter outputAD/DA control register(4)P32, P33CMOS compatible input level N-channelopen-drain output(5)P34/R X D 3P35/T X D 3P36/S CLK3P37/S RDY3CMOS compatible input levelCMOS 3-state outputSerial I/O3 function I/O Serial I/O3 control register UART3 control register(6)(7)(8)(9)P40/INT 40/X COUT P41/INT 00/X CIN Port P4External interrupt input Sub-clock generating circuit Interrupt edge selection register CPU mode register (10)(11)P42/INT 1P43/INT 2External interrupt inputInterrupt edge selection register (2)P44/R X D 1P45/T X D 1P46/S CLK1Serial I/O1 function I/OSerial I/O1 control register UART1 control register (6)(7)(8)P47/S RDY1/CNTR 2Serial I/O1 function I/O Timer Z function I/O Serial I/O1 control register Timer Z mode register (12)P50/S IN2P51/S OUT2P52/S CLK2P53/S RDY2Port P5Serial I/O2 function I/OSerial I/O2 control register(13)(14)(15)(16)P54/CNTR 0 P55/CNTR 1Timer X, Y function I/O Timer XY mode register(17)P56/PWM PWM outputPWM control register (18)P57/INT 3External interrupt input Interrupt edge selection register (2)P60/AN 0−P67/AN 7Port P6A/D converter inputAD/DA control register (1)Fig 12.Port block diagram (1)Fig 14.Port block diagram (3)Fig 16.Structure of port pull-up control register (2)INTERRUPTSThe 3803 group (Spec.H QzROM version)’s interrupts are a type of vector and occur by 16 sources among 21 sources: eight external, twelve internal, and one software.•Interrupt ControlEach interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software.The reset and the BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt.When several interrupt requests occur at the same time, the interrupts are received according to priority.•Interrupt OperationBy acceptance of an interrupt, the following operations are automatically performed:1.The contents of the program counter and the processor sta-tus register are automatically pushed onto the stack.2.The interrupt disable flag is set and the corresponding inter-rupt request bit is cleared.3.The interrupt jump destination address is read from the vec-tor table into the program counter.•Interrupt Source SelectionWhich of each combination of the following interrupt sources can be selected by the interrupt source selection register (address 003916).1. INT0 or Timer ZTR1 or Serial I/O3 reception3.Serial I/O2 or Timer Z4.INT4 or CNTR25.A/D converter or serial I/O3 transmission•External Interrupt Pin SelectionThe occurrence sources of the external interrupt INT0 and INT4 can be selected from either input from INT00 and INT40 pin, or input from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit of interrupt edge selection register (bit 6 of address 003A16).<Notes>When setting the followings, the interrupt request bit may be set to “1”.•When setting external interrupt active edgeRelated register: Interrupt edge selection register(address 003A16)Timer XY mode register (address 002316)Timer Z mode register (address 002A16)•When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocatedRelated register: Interrupt source selection register(address 003916)When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence.(1)Set the corresponding interrupt enable bit to “0” (disabled).(2)Set the interrupt edge select bit (the active edge switch bit)or the interrupt source select bit.(3)Set the corresponding interrupt request bit to “0” after 1 ormore instructions have been executed.(4)Set the corresponding interrupt enable bit to “1” (enabled).NOTES:1.Vector addresses contain interrupt jump destination addresses.2.Reset function in the same way as an interrupt with the highest priority.Table 9Interrupt vector addresses and priorityInterrupt Source Priority VectorAddresses (1)Interrupt Request GeneratingConditionsRemarksHigh LowReset (2)1FFFD 16FFFC 16At reset Non-maskableINT 02FFFB 16FFFA 16At detection of either rising or falling edge of INT 0 input External interrupt(active edge selectable)Timer Z At timer Z underflowINT 13FFF916FFF816At detection of either rising or falling edge of INT 1 inputExternal interrupt(active edge selectable)Serial I/O1 reception 4FFF716FFF616At completion of serial I/O1 data receptionValid when serial I/O1 is selected Serial I/O1 transmission 5FFF516FFF416At completion of serial I/O1 transmission shift or when transmission buffer is empty Valid when serial I/O1 is selectedTimer X 6FFF316FFF216At timer X underflow Timer Y 7FFF116FFF016At timer Y underflow Timer 18FFEF 16FFEE 16At timer 1 underflow STP release timer underflow Timer 29FFED 16FFEC 16At timer 2 underflowCNTR 010FFEB 16FFEA 16At detection of either rising or falling edge of CNTR 0 inputExternal interrupt(active edge selectable)CNTR 111FFE916FFE816At detection of either rising or falling edge of CNTR 1 inputExternal interrupt(active edge selectable)Serial I/O3 reception At completion of serial I/O3 data receptionValid when serial I/O3 is selected Serial I/O212FFE716FFE616At completion of serial I/O2 data transmission or reception Valid when serial I/O2 is selectedTimer Z At timer Z underflowINT 213FFE516FFE416At detection of either rising or falling edge of INT 2 inputExternal interrupt(active edge selectable)INT 314FFE316FFE216At detection of either rising or falling edge of INT 3 inputExternal interrupt(active edge selectable)INT 415FFE116FFE016At detection of either rising or falling edge of INT 4 inputExternal interrupt(active edge selectable)CNTR 2At detection of either rising or falling edge of CNTR 2 inputExternal interrupt(active edge selectable)A/D converter 16FFDF 16FFDE 16At completion of A/D conversion Serial I/O3 transmissionAt completion of serial I/O3 transmission shift or when transmission buffer is empty Valid when serial I/O3 is selectedBRK instruction 17FFDD 16FFDC 16At BRK instruction executionNon-maskable software interrupt。