SUNG_VCS_ProductivityTools

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Based on 10+ representative customer designs (90nm-32nm, 1M-150M gates) © Synopsys 2011 5
VCS Compilation
Overview
© Synopsys 2011
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Agenda
• Designs are getting larger and more complex • More functionality needs to be verified in the same amount of time, if not less • Trying to make the most of current compute resources • Knowing when “the design is ready” or “I’m done”
Gate Level
2.0X
Memory Consumption
100%
80% 60% 40%
2.0X
1.5X
1.8X
26%
0.5X 0.0X
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20% 0%
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Native Testbench - Advanced Constraint Solver
Bit-wise Inference
heuristics
SystemVerilog Support
Constraint DB
Solver
Range Inference
Solver State Info
Conditional Inference
(System)Verilog, VHDL, SystemC
Analyze
synopsys_sim.setup
./work (design libraries)
PLI table
Elaboration
./simv.daidir
Байду номын сангаас
C/C++, PLI, DPI, -Object
./csrc (Object Code)
Early Access Technology
6.0X
Partitions are sub-hierarchies of design or test-bench • Compiles partitions independently and in parallel • Simple use-model • Handles XMRs and wire semantics across partitions
© Synopsys 2011 10
% vcs –hsopt=gates …
0.0X Designs
Discovery Visualization Environment
Unified Debug
Design Debug
Assertion Debug
Analog Waveform
Coverage Viewing
Simply Go Back in Time and “Re-debug”
Checkpoint Checkpoint Sim Time
Checkpoint the simulation state
• Lighting fast, no saving to disk • Can be used at any time
© Synopsys 2011 11
C++/SystemC Debug
Low Power Debug
Transaction Level Debug
Full Automation with UVM and VMM
Transaction viewing/debugging
Cross-stepping between SystemC, RTL, and testbench
Details Available Online!
© Synopsys 2011 4
VCS
Improving Performance, Capacity with Every Release
RTL Run Time
2.5X
2.0X 1.5X 1.0X 1.0X 0.5X 0.0X
2008.12 2009.06 2009.12 2010.06 2011.03
© Synopsys 2011
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CONFIDENTIAL INFORMATION The following material is being disclosed to you pursuant to a nondisclosure agreement between you or your employer and Synopsys. Information disclosed in this presentation may be used only as permitted under such an agreement. LEGAL NOTICE
VCS productivity tools and technologies that help reduce the ever-growing verification cycle
Werner Kerscher Staff Application Consultant Verification Specialist Synopsys Munich
© Synopsys 2011
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Partition Compile
Compile Turn-around Time Improvement
top Compile Turn-around Time Improvements core1 core2 test1 xmr1 bfm xmr2
10.0X 8.0X
Information contained in this presentation reflects Synopsys plans as of the date of this presentation. Such plans are subject to completion and are subject to change. Products may be offered and purchased only pursuant to an authorized quote and purchase order. Synopsys is not obligated to develop the software with the features and functionality discussed in the materials.
Run Time Improvement
Gate-Level Sim
always@
Run Time Speed Up
3.0X
always@ always@ always@
always@
2.5X 2.0X
always@
1.5X 1.0X
always@
always@
always@
always@
0.5X
Clock hierarchy handled more intelligently to reduce indirect function calls at runtime
Rewind to any checkpoint
• Rewind back to simulation state • Keeps all other previous checkpoints
Add Checkpoint
Delete Checkpoint
Interactive simulation in DVE
SystemC source with annotated values
Debug relationship between transactions or message
Controlled through systemtasks or TCL
© Synopsys 2011 12
DVE Checkpoint-Rewind
© Synopsys 2011
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Challenges in Today’s Verification
• Designs are getting larger and more complex • More functionality needs to be verified in the same amount of time, if not less • Trying to make the most of current compute resources • Knowing when “the design is ready” or “I’m done”
4.0X 2.0X 0.0X Designs % vcs –partcomp …
Partition Compile Technology is under Limited Customer Availability in VCS 2011.03
© Synopsys 2011 9
HSOPT Gates Optimization
Compile Time
2.0X
1.5X
1.7X
1.5X 1.0X 1.0X 0.5X 0.5X
1.3X
100% 80% 60% 40% 20%
25%