Si3226-27

Preliminary Rev. 0.33 6/07Copyright © 2007 by Silicon Laboratories Si3226/7 Si3208/9This information applies to a product under development. Its characteristics and specifications are subject to change without notice.Si3226/7Si3208/9D U A L P R O SLIC ® W I T H DC-DC C O N T R O L LE RFeaturesApplicationsDescriptionThe Dual ProSLIC is a family of low-voltage CMOS devices that integrate both SLIC and CODEC functionality into a single IC. In combination with a linefeed IC (LFIC), they provide a complete two-channel analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI specifications. The Dual ProSLIC devices (Si3226/7) operate from a single 3.3V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all high-voltage functions and operate from a 3.3V supply as well as high-voltage battery supplies. The Si3208 is rated for –110V, and the Si3209 is rated for –135V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package (TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package (QFN).Functional Block DiagramPerforms all BORSCHT functions Ideal for short- or long-loop applications Internal balanced or unbalanced ringing Low power consumptionSoftware-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance Transhybrid balanceDC current loop feed (10–45mA) Loop closure and ring trip thresholds Ground key detect threshold Integrated dc-dc controller Wideband CODEC (Si3227) Low-power sleep mode On-hook transmissionLoop or ground start operation Smooth polarity reversal DTMF generator/decoder A-Law/µ-Law companding,linear PCMPCM and SPI bus digital interfaces with programmable interrupts GCI/IOM-2 mode support 3.3V operationGR-909 loop diagnosticsAudio diagnostics with loopbackPb-free/RoHS-compliant packagingCustomer Premises Equipment (CPE)Optical Network Terminals (ONT) Private Branch Exchange (PBX) Cable EMTAs, ATAs, VoIPGatewaysPatents pendingSi3226/7Si3208/92Preliminary Rev. 0.33Si3226/7Si3208/9Preliminary Rev. 0.333T A B L E O F C O N T E N TSSectionPage1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264.6. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264.7. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264.8. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.9. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.10. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.11. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.12. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.13. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.14. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274.17. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284.18. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284.19. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284.20. Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285. Pin Descriptions: Si3226/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296. Pin Descriptions: Si3208/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Si3226/7 Si3208/94Preliminary Rev. 0.331. Electrical SpecificationsTable 1. Absolute Maximum Ratings and Thermal Information1Parameter Symbol Test Condition Value Unit Operating Temperature Range T A–40 to 85°C Storage Temperature Range T STG–55 to 150°C Thermal Resistance, Typical2TQFP-64θJA25°C/WContinuous Power Dissipation3TQFP-64P D T A=85°C 1.6WThermal Resistance, Typical2QFN-40θJA32°C/W Continuous Power Dissipation4QFN-40P D T A=85°C 1.7WSi3226/7Supply Voltage V DD1–V DD4–0.5 to 4.0V Digital Input Voltage V IND–0.3 to 3.6VSi3208Supply Voltage V DD–0.5 to 4.0VBattery Supply Voltage5V BAT Continuous+0.4 to –110VPulse < 10µs+0.4 to –118VTIP, RING Current I TIP, I RING±100mASi3209Supply Voltage V DD–0.5 to 4.0VHigh Battery Supply Voltage5V BATContinuous+0.4 to –135V Pulse < 10µs+0.4 to –143VTIP, RING Current I TIP, I RING±100mA Notes:1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should berestricted to the conditions as specified in the operational sections of this data sheet.2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layoutguidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal/bottom copper plane.3. Operation of the Si3226 or Si3227 above 125°C junction temperature may degrade device reliability.4. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junctiontemperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to 145 °C; when in the ringing state the thermal shutdown may be set to 200 °C. For optimal reliability long term operation of the Si3208/Si3209 above 150°C junction temperature should be avoided.5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10V/µs.Si3226/7Si3208/9Preliminary Rev. 0.335Table 2. Recommended Operating ConditionsParameterSymbol Test Condition Min *Typ Max *UnitAmbient Temperature T A F-grade 02570oCAmbient Temperature T A G-grade–402585o CSupply Voltage, Si3226/7V DD1–V DD43.13 3.3 3.47V Supply Voltage, Si3208/Si3209V DD3.13 3.33.47V Battery Voltage, Si3208V BAT –9—–110V Battery Voltage, Si3209V BAT–9—–135V*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.Table 3. 3.3V Power Supply Characteristics 1(V DD =3.3V, T A =0 to 70 ºC for F-Grade, –40 to 85 ºC for G-Grade)ParameterSymbol Test Condition Min Typ Max Unit High Impedance, ResetI DD V T and V R =Hi-ZRST =0— 2.4—mA I VBAT —0—mA High Impedance, Open CurrentI DD V T and V R =Hi-Z —9.7—mA I VBAT —0.6—mA Forward/Reverse Sleep, On-hook Current I DD V TR =–48V —15—mA I VBAT — 1.2—mA Forward/Reverse Active, On-hook Current I DD V TR =–48V —24—mA I VBAT — 1.2—mA Forward/Reverse Active, Off-hook Current I DD I LOOP =30mA R LOAD =50Ω—43—mA I VBAT — 3.1 + I LOOP—mA Forward/Reverse OHT, On-hook Current I DD V TR =–48V —43—mA I VBAT — 1.6—mA Tip/Ring Open, On-hook Current I DD V T or V R =–48V V R or V T =Hi-Z—23—mA I VBAT —0.6—mA Ringing CurrentI DD V TR =55V RMS + 0V DC balanced, sinusoidal, f =20Hz R LOAD =5 REN =1400Ω—26—mA I VBAT—2.3 + I AVE—mANotes:1.All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with allchannels in the same operating state.2. I LOOP is the dc current in the subscriber loop during the off-hook state.3. I AVE is the average of the full-wave rectified current in the subscriber loop during ringing (I AVE = I PEAK x 2/π).Si3226/7 Si3208/96Preliminary Rev. 0.33Table 4. AC Characteristics(V DD=3.13 to 3.47V, T A=0 to 70°C for F-Grade, –40 to 85°C for G-Grade)Parameter Test Condition Min Typ Max UnitTX/RX PerformanceOverload Level 2.5——V PK Overload Compression2-Wire – PCM Figure6——Single Frequency Distortion12-Wire – PCM or PCM – 2-Wire:200Hz to 3.4kHz——–65dBPCM – 2-Wire – PCM:200Hz – 3.4kHz,16-bit Linear mode——–65dBSignal-to-(Noise + Distortion) Ratio2200Hz to 3.4kHzD/A or A/D 8-bitActive off-hook, and OHT, any Z TFigure5——Audio Tone Generator Signal-to-Distortion Ratio20dBm0, Active off-hook, andOHT, any Z T46——dBIntermodulation Distortion——–41dB Gain Accuracy22-Wire to PCM or PCM to 2-Wire1014Hz, Any gain settingV DD1–V DD4=3.3V±5%–0.2—0.2dB Attenuation Distortion vs. Freq.0dBm0See AN317Group Delay vs. FrequencyGain Tracking31014Hz sine wave,reference level –10dBmSignal level:————3dB to –37dB——0.25dB–37dB to –50dB——0.5dB–50dB to –60dB—— 1.0dB Round-Trip Group Delay 1014Hz, Within same time-slot—450500µsCrosstalk between channels TX or RX to TXTX or RX to RX0dBm0,300Hz to 3.4kHz300Hz to 3.4kHz————–75–75dBdB2-Wire Return Loss4200Hz to 3.4kHz2630—dB Transhybrid Balance4300Hz to 3.4kHz2630—dBNoise PerformanceIdle Channel Noise5C-Message weighted—812dBrnCPsophometric weighted —–80–78dBmP PSRR from V DD1–V DD4RX and TX, dc to 3.4kHz40——dB Notes:1.The input signal level should be 0dBm0 for frequencies greater than 100Hz. For 100Hz and below, the level shouldbe –10dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.2. Analog signal measured as V TIP – V RING. Assumes ideal line impedance matching.3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain trackingperformance in the signal range of 3 to –37dB for signal frequencies that are integer divisors of the 8kHz PCMsampling rate.4. V DD1–V DD4=3.3V, V BAT=–52V, no fuse resistors; R L=600Ω, Z S=600Ω synthesized using RS registercoefficients.5. The level of any unwanted tones within the bandwidth of 0 to 4kHz does not exceed –55dBm.Si3226/7Si3208/9Preliminary Rev. 0.337Longitudinal Performance Longitudinal to Metallic/PCM Balance (forward or reverse)200Hz to 1kHz 5860—dB 1kHz to 3.4kHz 5358—dB Metallic/PCM to Longitudinal Bal-ance200Hz to 3.4kHz 40——dB Longitudinal Impedance 200Hz to 3.4kHz at TIP or RING—50—ΩLongitudinal Current per Pin Active off-hook 200Hz to 3.4kHz——30mA DC CurrentDifferential ——45mA Common Mode ——30mA Differential + Common Mode——45mATable 4. AC Characteristics (Continued)(V DD =3.13 to 3.47V, T A =0 to 70°C for F-Grade, –40 to 85°C for G-Grade)ParameterTest ConditionMin Typ Max Unit Notes:1.The input signal level should be 0dBm0 for frequencies greater than 100Hz. For 100Hz and below, the level shouldbe –10dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.2. Analog signal measured as V TIP – V RING . Assumes ideal line impedance matching.3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain trackingperformance in the signal range of 3 to –37dB for signal frequencies that are integer divisors of the 8kHz PCM sampling rate.4. V DD1–V DD4=3.3V, V BAT =–52V, no fuse resistors; R L =600Ω, Z S =600Ω synthesized using RS registercoefficients.5. The level of any unwanted tones within the bandwidth of 0 to 4kHz does not exceed –55dBm.Si3226/7 Si3208/98Preliminary Rev. 0.33Table 5. Linefeed Characteristics(V DD= 3.13 to 3.47V, T A = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade)Parameter Symbol Test Condition Min Typ Max Unit Maximum Loop Resistance R LOOP R DC,MAX=430ΩI LOOP=18mA,V BAT=–52V——2000ΩDC Loop Current Accuracy I LIM=18mA——10%DC Open Circuit Voltage Accuracy Active Mode; V OC=48V,V TIP – V RING——4VDC Differential OutputResistanceR DO I LOOP < I LIM160—640ΩDC On-Hook Voltage Accuracy—Ground Start V OHTO I RING<I LIM; V RING wrt ground,V RING=–51V——4VDC OutputResistance—Ground StartR ROTO I RING<I LIM; RING to ground160—640ΩDC Output Resistance—Ground StartR TOTO TIP to ground400——kΩLoop Closure DetectThreshold AccuracyI THR=13mA——10%Ground Key DetectThreshold AccuracyI THR=13mA——10%Ring Trip Threshold AccuracyAC detection,V RING=70Vpk, no offset,I TH=80mA——4mADC detection,20V dc offset, I TH=13mA——1mADC Detection,48V DC offset, R loop=1500Ω——3mARinging Amplitude V RING Open circuit, V BAT=–110V108——V PK5 REN load, R LOOP=0Ω,V BAT=–110V,R DO=160Ω99——V PKOpen Circuit, V BAT=–135V133——V PK5 REN load, R LOOP=0Ω,V BAT=–130V, R DO=160Ω121——V PKSinusoidal Ringing TotalHarmonic DistortionR THD—2—% Ringing Frequency Accuracy f=16Hz to 100Hz——1% Ringing Cadence Accuracy Accuracy of ON/OFF times——50ms Calibration Time↑CAL to ↓CAL bit——TBD msLoop Voltage Sense Accuracy Accuracy of boundaries foreach output Code;V TIP – V RING=48V—24%*Note:Ringing amplitude is set for 93V peak and measured at TIP-RING using no series protection resistance.Si3226/7Si3208/9Preliminary Rev. 0.339Loop Current Sense Accuracy Accuracy of boundaries foreach output code;I LOOP =18mA —710%Power AlarmThreshold AccuracyPower Threshold =300mW——25%Table 6. Monitor ADC Characteristics(V DD =3.13 to 3.47V, T A =0 to 70°C for F-Grade, –40 to 85°C for G-Grade)ParameterSymbol Test Condition Min Typ Max Unit Differential Nonlinearity (8-bit resolution)DNLE ——1LSB Integral Nonlinearity (8-bit resolution)INLE——1LSB Gain Error——5%Table 7. Si3208/Si3209 Characteristics(V DD =3.13 to 3.47V, V BAT =–15 to –130 V, T A =0 to 70°C for F-Grade, –40 to 85°C for G-Grade)ParameterSymbol Test Condition Min Typ Max UnitTIP/RING Pull-down Transistor Saturation VoltageV CMV RING – V BAT (Forward)V TIP – V BAT (Reverse)V AC =2.5V PK I OUT =22mA I OUT =60mA ⎯⎯3⎯⎯3.5V VTIP/RING Pull-up Transistor Saturation VoltageV OVGND – V TIP (Forward)GND – V RING (Reverse)V AC =2.5V PK I OUT =22mA I OUT =60mA⎯⎯3⎯⎯3.5V V OPEN State TIP/RING Leakage CurrentI LKGR L =0Ω⎯⎯150µATable 5. Linefeed Characteristics (Continued)(V DD = 3.13 to 3.47V, T A = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade)ParameterSymbol Test Condition Min Typ Max Unit *Note: Ringing amplitude is set for 93V peak and measured at TIP-RING using no series protection resistance.Si3226/7 Si3208/910Preliminary Rev. 0.33Table 8. DC Characteristics(V DD=3.13 to 3.47V, T A=0 to 70°C for F-Grade, –40 to 85°C for G-Grade)Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage V IH0.7 x V DD— 5.25V Low Level Input Voltage V IL——0.3 x V DD V High Level OutputVoltageV OH I O=4mA V DD –0.6——VLow Level Output Voltage V OL DTX, SDO, INT,SDITHRU:I O=–4mA——0.4VGPIO1 a/b, GPIO2 a/b:I O=–40mA——0.72SDITHRU internal pullupresistance3550—kΩRelay Driver Source Impedance R OUT V DD1–V DD4=3.13VIO < 28mA—63—ΩRelay Driver Sink Impedance R IN V DD1–V DD4=3.13VIO < 85mA—11—ΩInput Leakage Current I L——10µA Table 9. Switching Characteristics—General Inputs1(V DD=3.13 to 5.25V, T A=0 to 70°C for F-Grade, –40 to 85°C for G-Grade, C L=20pF)Parameter Symbol Min Typ Max Unit Rise Time, RESET t r——5ns RESET Pulse Width, GCI Mode2,3t rl33/PCLK——µs RESET Pulse Width, SPI Daisy Chain Mode3t rl33/PCLK——µs Notes:1.All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels areV IH=V DD – 0.4V, V IL=0.4V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than10kΩ per device.3. The minimum RESET pulse width is 33/PCLK frequency (i.e. 33/8.192MHz=4µs).Si3226/7Si3208/9Figure 1.SPI Timing DiagramTable 10. Switching Characteristics—SPI(V DDA =3.13 to 5.25V, T A =0 to 70°C for F-Grade, –40 to 85°C for G-Grade, C L =20pF)ParameterSymbol Test Conditions Min Typ Max Unit Cycle Time SCLK t c 62——ns Rise Time, SCLK t r ——25ns Fall Time, SCLKt f ——25ns Delay Time, SCLK Fall to SDO Active t d1——20ns Delay Time, SCLK Fall to SDO Transitiont d2——20ns Delay Time, CS Rise to SDO Tri-state t d3——20ns Setup Time, CS to SCLK Fall t su125——ns Hold Time, CS to SCLK Rise t h120——ns Setup Time, SDI to SCLK Rise t su225——ns Hold Time, SDI to SCLK Rise t h220——ns Delay Time between Chip Selects t cs 220——ns SDI to SDITHRU Propagation Delayt d4—410nsNote:All timing is referenced to the 50% level of the waveform. Input test levels are V IH =V DDD –0.4V, V IL =0.4VSi3226/7Si3208/9Table 11. Switching Characteristics—PCM Highway Interface(V DD=3.13 to 5.25V, T A=0 to 70°C for F-Grade, –40 to 85°C for G-Grade, C L=20pF)Parameter Symbol TestConditionsMin1Typ1Max1Units PCLK Period t p122—3906nsValid PCLK Inputs————————5127681.0241.5361.5442.0484.0968.192————————kHzkHzMHzMHzMHzMHzMHzMHzFSYNC Period2t fs—125—µs PCLK Duty Cycle Tolerance t dty405060% FSYNC Jitter Tolerance t jitter——±120ns Rise Time, PCLK t r——25ns Fall Time, PCLK t f——25ns Delay Time, PCLK Rise to DTX Active t d1——20ns Delay Time, PCLK Rise to DTXTransitiont d2——20nsDelay Time, PCLK Rise to DTXTristate3t d3——20ns Setup Time, FSYNC to PCLK Fall t su125——ns Hold Time, FSYNC to PCLK Fall t h120——ns Setup Time, DRX to PCLK Fall t su225——ns Hold Time, DRX to PCLK Fall t h220——ns FSYNC Pulse Width t wfs t p—125µs–t p Notes:1.All timing is referenced to the 50% level of the waveform. Input test levels are V IH – V I/O–0.4V,V IL=0.4V.2. FSYNC source is assumed to be 8kHz under all operating conditions.3. Spec applies to PCLK fall to DTX tristate when that mode is selected.Si3226/7Si3208/9Table 12. Switching Characteristics—GCI Highway Serial Interface(V DD=3.13 to 5.25V, T A=0 to 70°C for F-Grade, –40 to 85°C for G-Grade)Min Typ Max Units Parameter1Symbol TestConditionsPCLK Period (2.048MHz PCLK Mode)t p—488—ns PCLK Period (4.096MHz PCLK Mode)t p—244—ns FSYNC Period2t fs—125—µs PCLK Duty Cycle Tolerance t dty405060% FSYNC Jitter Tolerance t jitter——±120ns Rise Time, PCLK t r——25ns Fall Time, PCLK t f——25ns Delay Time, PCLK Rise to DTX Active t d1——20ns Delay Time, PCLK Rise to DTX Transition t d2——20ns Delay Time, PCLK Rise to DTX Tristate3t d3——20ns Setup Time, FSYNC Rise to PCLK Fall t su125——ns Hold Time, PCLK Fall to FSYNC Fall t h120——ns Setup Time, DRX Transition to PCLK Fall t su225——ns Hold Time, PCLK Falling to DRX Transition t h220——ns FSYNC Pulse Width t wfs t p/2——ns Notes:1.All timing is referenced to the 50% level of the waveform. Input test levels are V IH=V O – 0.4V and V IL=0.4V.Rise and fall times are referenced to the 20% and 80% levels of the waveform.2. FSYNC source is assumed to be 8kHz under all operating conditions.3. Specification applies to PCLK fall to DTX tristate when that mode is selected.Si3226/7Si3208/9Figure3.GCI Highway Interface Timing Diagram (2.048MHz PCLK Mode)Si3226/7Si3208/9Figure 5.Transmit and Receive Path SNDRFigure 6.Overload Compression PerformanceAcceptable12345678912345678902.6Acceptable RegionSi3226/7 Si3208/92. Typical Application CircuitsF i g u r e 7.S i 3226/7 (2 L i n e s )Si3226/7Si3208/9F i g u r e 8.D C -D C C o n v e r t e r (A )Si3226/7 Si3208/9F i g u r e 9.D C -D C C o n v e r t e r (B )Si3226/7Si3208/9F i g u r e 10.L i n e f e e d (2 L i n e s )Si3226/7 Si3208/93. B i l l o f M a t e r i a l sT a b l e 13. B i l l o f M a t e r i a l s f o r S i 3226/7 (2 L i n e s )Q u a n t i t yR e f e r e n c e V a l u eR a t i n gT o l e r a n c e D i e l e c t r i c P C B F o o t p r i n t M a n u f a c t u r e r2C 1, C 610µF6.3V±20%Y 5V C C 1210V e n k e l2C 100, C 2000.1µF6.3V±10%X 7R C C 0603V e n k e l4C 2, C 4, C 5, C 70.1µF6.3V±20%X 7R C C 0603V e n k e l1C 3*10µF6.3V±20%Y 5V C C 1210V e n k e l1C 84.7n F6.3V±10%X 7R C C 0603V e n k e l1L 1*10µH180m A±10% I N D -N L C 3225T D K1R 249.9k Ω1/16W±0.5% R C 0603V e n k e l4R 13, R 15, R 16, R 1910k Ω1/10W±5% R C 0603V e n k e l1R 17137k Ω1/16W±1% R C 0603V e n k e l2R 100, R 200825k Ω1/10W , 100V±1%R C 0805V e n k e l4R 106*, R 107*, R 206*, R 207*1.58M Ω1/10W , 100V ±5% R C 0805V e n k e l1U 1S i 3226T Q F P 64S i L a b s*N o t e : D e n o t e s o p t i o n a l c o m p o n e n t .Si3226/7Si3208/9T a b l e 14. B i l l o f M a t e r i a l s f o r L i n e f e e d a n d D C -D C C o n v e r t e r s w i t h |V O U T | < 90V (2 L i n e s )V I N =+12V n o m i n a l , |V o u t | < 90VQ u a n t i t yR e f e r e n c e V a l u eR a t i n gT o l e r a n c e D i e l e c t r i c P C B F o o t p r i n t M a n u f a c t u r e r1C 12010µF25V±20%X 7R C C 1210V e n k e l 1C 220*10µF 25V±20%X 7R C C 1210V e n k e l2C 121, C 2210.1µF25V±10%X 7R C C 0603V e n k e l2C 126, C 2260.1µF25V±20%X 7R C C 0603V e n k e l2C 124, C 2240.1µF100V±20%X 7R C C 1210V e n k e l2C 125*, C 225*0.1µF100V±20%X 7R C C 1210V e n k e l2C 122, C 2220.22µF100V±20%X 7R C C 1812V e n k e l2C 123, C 2233.3µF100V±20%A l C 2.5X 6.3M M -R A DP a n a s o n i c4C 127, C 128, C 227, C 228470p F25V±10%X 7R C C 0402V e n k e l2D 122, D 222B A S 21H T 1250V ,200m AS O D -323O N S E M I2D 121, D 221S T P S 2150A150V , 2.0AD O -214A CS T M i c r o2L 120, L 22015µHC D R 74S U M I D A2Q 120, Q 220F Q T 7N 10100V , 2WS O T -223F a i r c h i l d2Q 121, Q 221M M D T 3946S O T -363D i o d e s I n c .2R 121, R 2210.1Ω1/4W±1%R C 1210V e n k e l2R 122, R 22215Ω1/4W±5%R C 1206V e n k e l2R 123, R 223220Ω1/16W±5%R C 0402V e n k e l2R 124, R 2241k Ω1/16W±5%R C 0402V e n k e l2R 125, R 225150k Ω1/16W±5%R C 0402V e n k e l2R 126, R 226100k Ω1/16W±5%R C 0402V e n k e l2R 127, R 2272Ω1/8W±5%R C 0402V e n k e l1C 1070.1µF25V±10%X 7R C C 0603V e n k e l*N o t e : D e n o t e s o p t i o n a l c o m p o n e n t .Si3226/7 Si3208/94C 101, C 102, C 201, C 20210n F100V±10%X 7R C C 0805V e n k e l 4C 103, C 104, C 203, C 20410n F100V±10%X 7R C C 0805V e n k e l2C 105, C 2050.1µF100V±20%X 7R C C 1210V e n k e l4R 101, R 102, R 201, R 202681k Ω1/10W , 150V±1% R C 0805V e n k e l4R 103, R 104, R 203, R 204301k Ω1/16W , 75V±1% R C 0603V e n k e l2R 105, R 205590k Ω1/10W , 150V ±1% R C 0805V e n k e l1U 100S i 3208 o r S i 3209Q F N -40S i l i c o n L a b o r a t o r i e sT a b l e 14. B i l l o f M a t e r i a l s f o r L i n e f e e d a n d D C -D C C o n v e r t e r s w i t h |V O U T | < 90V (2 L i n e s ) (C o n t i n u e d )V I N =+12V n o m i n a l , |V o u t | < 90VQ u a n t i t yR e f e r e n c e V a l u eR a t i n gT o l e r a n c e D i e l e c t r i c P C B F o o t p r i n t M a n u f a c t u r e r*N o t e : D e n o t e s o p t i o n a l c o m p o n e n t .Si3226/7Si3208/9T a b l e 15. B i l l o f M a t e r i a l s f o r L i n e f e e d a n d D C -D C C o n v e r t e r s w i t h |V O U T | < 135V (2 L i n e s )V I N =+12V n o m i n a l , |V o u t | < 135VQ u a n t i t yR e f e r e n c e V a l u eR a t i n gT o l e r a n c e D i e l e c t r i c P C B F o o t p r i n t M a n u f a c t u r e r1C 12010µF25V±20%X 7R C C 1210V e n k e l1C 220*10µF 25V±20%X 7R C C 1210V e n k e l2C 121,C 2210.1µF25V±10%X 7R C C 0603V e n k e l2C 126,C 2260.1µF25V±20%X 7R C C 0603V e n k e l2C 124,C 2240.1µF200V±20%X 7R C C 1210V e n k e l2C 125*,C 225*0.1µF200V±20%X 7R C C 1210V e n k e l2C 122,C 2220.22µF200V±20%X 7R C C 1812V e n k e l2C 123,C 2233.3µF160V±20%A l C 2.5X 6.3M M -R A DP a n a s o n i c4C 127, C 128, C 227, C 228470p F25V±10%X 7R C C 0402V e n k e l2D 122, D 222B A S 21H T 1250V ,200m AS O D -323O N S E M I2D 121, D 221S T P S 2150A150V , 2.0AD O -214A CS T M i c r o2L 120, L 22015µHC D R H 125S U M I D A2Q 120, Q 220F Q D 7N 20L200V , 2.5WD -P A KF a i r c h i l d2Q 121, Q 221M M D T 3946S O T -363D i o d e s I n c .2R 121, R 2210.1Ω1/4W±1%R C 1210V e n k e l2R 122, R 22215Ω1/4W±5%R C 1206V e n k e l2R 123, R 223220Ω1/16W±5%R C 0402V e n k e l2R 124, R 2241k Ω1/16W±5%R C 0402V e n k e l2R 125, R 225150k Ω1/16W±5%R C 0402V e n k e l2R 126, R 226100k Ω1/16W±5%R C 0402V e n k e l2R 127, R 2272Ω1/8W±5%R C 0402V e n k e l1C 1070.1µF25V±10%X 7R C C 0603V e n k e l*N o t e : D e n o t e s o p t i o n a l c o m p o n e n t .。