MAX2631中文资料

General DescriptionThe MAX3280E/MAX3281E/MAX3283E/MAX3284E are single receivers designed for RS-485 and RS-422 com-munication. These devices guarantee data rates up to 52Mbps, even with a 3V power supply. Excellent propa-gation delay (15ns max) and package-to-package skew time (8ns max) make these devices ideal for mul-tidrop clock distribution applications.The MAX3280E/MAX3281E/MAX3283E/MAX3284E have true fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are opened or shorted. The receiver output will be a logic high if all transmitters on a terminated bus are disabled (high impedance). These devices feature 1/4-unit-load receiver input impedance, allowing up to 128 receivers on the same bus.The MAX3280E is a single receiver available in a 5-pin SOT23 package. The MAX3281E/MAX3283E single receivers have a receiver enable (EN or EN ) function and are offered in a 6-pin SOT23 package. The MAX3284E features a voltage logic pin that allows com-patibility with low-voltage logic levels, as in digital FPGAs/ASICs. On the MAX3284E, the voltage threshold for a logic high is user-defined by setting V L in the range from 1.65V to V CC . The MAX3284E is also offered in a 6-pin SOT23 package.ApplicationsClock Distribution Telecom Racks Base Stations Industrial Control Local Area NetworksFeatureso ESD Protection:±15kV–Human Body Model±6kV–IEC 1000-4-2, Contact Discharge ±12kV–IEC 1000-4-2, Air-Gap Discharge o Guaranteed 52Mbps Data Rateo Guaranteed 15ns Receiver Propagation Delay o Guaranteed 2ns Receiver Skewo Guaranteed 8ns Package-to-Package Skew Time o V L Pin for Connection to FPGAs/ASICs o Allow Up to 128 Transceivers on the Bus (1/4-unit-load)o Tiny SOT23 Package o True Fail-Safe Receivero -7V to +12V Common-Mode Range o 3V to 5.5V Power-Supply Rangeo Enable (High and Low) Pins for Redundant Operation o Three-State Output Stage (MAX3281E/MAX3283E)o Thermal Protection Against Output Short CircuitMAX3280E/MAX3281E/MAX3283E/MAX3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers________________________________________________________________Maxim Integrated Products1Ordering Information19-2320; Rev 0; 1/02For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Pin Configurations appear at end of data sheet.M A X 3280E /M A X 3281E /M A X 3283E /M A X 3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe ReceiversABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = 3V to 5.5V, V L = V CC , T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = 5V and T A = +25°C.) (Notes 2, 3)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.(All Voltages Referenced to GND)Supply Voltage (V CC )...............................................-0.3V to +6V Control Input Voltage (EN, EN ).................................-0.3V to +6V V L Input Voltage.......................................................-0.3V to +6V Receiver Input Voltage (A, B)..............................-7.5V to +12.5V Receiver Output Voltage (RO)....................-0.3V to (V CC + 0.3V)Receiver Output Voltage(RO) (MAX3284E).....................................-0.3V to (V L + 0.3V)Receiver Output Short-Circuit Current.......................ContinuousContinuous Power Dissipation (T A = +70°C)5-Pin SOT23 (derate 7.1mW/°C above +70°C)............571mW 6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW Operating Temperature RangeMAX328_EA__..............................................-40°C to +125°C Storage Temperature Range.............................-65°C to +150°C Junction Temperature......................................................+150°C Lead Temperature (soldering, 10s).................................+300°CMAX3280E/MAX3281E/MAX3283E/MAX3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers_______________________________________________________________________________________3SWITCHING CHARACTERISTICSTypical Operating Characteristics(V CC = 3.3V, T A = +25°C, unless otherwise noted.)0132450201030405060RECEIVER OUTPUT LOW VOLTAGEvs. OUTPUT CURRENTOUTPUT CURRENT (mA)O U T P U T V O L T A G E (V )013245-50-30-40-20-10RECEIVER OUTPUT HIGH VOLTAGEvs. OUTPUT CURRENTOUTPUT CURRENT (mA)O U T P U T V O L T A G E (V )2.53.04.03.54.55.0-50-25255075100125RECEIVER OUTPUT HIGH VOLTAGEvs. TEMPERATURETEMPERATURE (°C)R E C E I V E R O U T P U T H I G H V O L T A G E (V )ground, unless otherwise noted.Note 4:V CM is the common-mode input voltage. V ID is the differential input voltage.Note 5:Not production tested. Guaranteed by design.Note 6:See Table 2 for MAX3284E data rates with V L < V CC .M A X 3280E /M A X 3281E /M A X 3283E /M A X 3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers 4_______________________________________________________________________________________050100150200-50-25255075100125RECEIVER OUTPUT LOW VOLTAGEvs. TEMPERATURETEMPERATURE (°C)R E C E I V E R O U T P U T L O W V O L T A G E (m V)457689-50-25255075100125RECEIVER PROPAGATION DELAY (t PLH )vs. TEMPERATURETEMPERATURE (°C)t P L H (n s)678910-50-25255075100125RECEIVER PROPAGATION DELAY (t PHL )vs. TEMPERATURETEMPERATURE (°C)t P H L (n s )56789SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )-502550-257510012560504030201.53.52.54.55.5MAX3284E MAXIMUM DATA RATEvs. VOLTAGE LOGIC LEVELM A X 3280/1/3/4E t o c 08VOLTAGE LOGIC LEVEL (V)D A T A R A TE (M b p s )0264810SUPPLY CURRENT vs. DATA RATEDATA RATE (kbps)S U P P L Y C U R R E N T (m A )10100010010,000100,0000.0010.010.1110V L SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)V L S U P P L Y C U R R E N T (m A )-502550-2575100125Typical Operating Characteristics (continued)(V CC = 3.3V, T A = +25°C, unless otherwise noted.)Detailed Description The MAX3280E/MAX3281E/MAX3283E/MAX3284E are single, true fail-safe receivers designed to operate at data rates up to 52Mbps. The fail-safe architecture guar-antees a high output signal if both input terminals are open or shorted together. See the True Fail-Safe section. This feature assures a stable and predictable output logic state with any transmitter driving the line. These receivers function with a 3.3V or 5V supply voltage and feature excellent propagation delay times (15ns).The MAX3280E is a single receiver available in a 5-pin SOT23 package. The MAX3281E (EN, active high) and MAX3283E (EN, active low) are single receivers that also contain an enable pin. Both the MAX3281E and MAX3283E are available in a 6-pin SOT23 package. The MAX3284E is a single receiver that contains a V L pin, which allows communication with low-level logic included in digital FPGAs. The MAX3284E is available in a 6-pin SOT23 package.The MAX3284E’s low-level logic application allows users to set the logic levels. A logic high level of 1.65V will limit the maximum data rate to 20Mbps.±15kV ESD Protection ESD-protection structures are incorporated on the receiver input pins to protect against ESD encountered during handling and assembly. The MAX3280E/ MAX3281E/MAX3283E/MAX3284E receiver inputs (A, B) have extra protection against static electricity found in normal operation. Maxim’s engineers developed state-of-the-art structures to protect these pins against family of parts continues working without latchup.ESD protection can be tested in several ways. The receiver inputs are characterized for protection to the following:•±15kV using the Human Body Model•±6kV using the Contact Discharge method specified in IEC 1000-4-2 (formerly IEC 801-2)•±12kV using the Air-Gap Discharge method speci-fied in IEC 1000-4-2 (formerly IEC 801-2)ESD Test ConditionsESD performance depends on a number of conditions. Contact Maxim for a reliability report that documentstest setup, methodology, and results.Human Body Model Figure 3a shows the H uman Body Model, and Figure3b shows the current waveform it generates when dis-charged into a low impedance. This model consists ofa 100pF capacitor charged to the ESD voltage of inter-est, which is then discharged into the device through a1.5kΩresistor.IEC 1000-4-2Since January 1996, all equipment manufacturedand/or sold in the European community has been required to meet the stringent IEC 1000-4-2 specifica-tion. The IEC 1000-4-2 standard covers ESD testingand performance of finished equipment; it does not specifically refer to integrated circuits. TheMAX3280E/MAX3281E/MAX3283E/MAX3284E help MAX3280E/MAX3281E/MAX3283E/MAX3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers_______________________________________________________________________________________5M A X 3280E /M A X 3281E /M A X 3283E /M A X 3284Eusers design equipment that meets Level 3 of IEC 1000-4-2, without additional ESD-protection components.The main difference between tests done using the H uman Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2. Because series resistance is lower in the IEC 1000-4-2 ESD test model (Figure 4a),the ESD-withstand voltage measured to this standard is generally lower than that measured using the H uman Body Model. Figure 4b shows the current waveform for the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized.Machine ModelThe Machine Model for ESD testing uses a 200pF stor-age capacitor and zero-discharge resistance. It mimics the stress caused by handling during manufacturing and assembly. All pins (not just the RS-485 inputs)require this protection during manufacturing. Therefore,the Machine Model is less relevant to the I/O ports than are the Human Body Model and IEC 1000-4-2.True Fail-SafeThe MAX3280E/MAX3281E/MAX3283E/MAX3284E guarantee a logic-high receiver output when the receiv-er inputs are shorted or open, or when they are connect-ed to a terminated transmission line with all drivers disabled. This guaranteed logic high is achieved by set-ting the receiver threshold between -50mV and -200mV.If the differential receiver input voltage (A-B) is greater than or equal to -50mV, RO is logic high. If (A-B) is less than or equal to -200mV, RO is logic low.In the case of a terminated bus with all transmitters dis-abled, the receiver ’s differential input voltage is pulled to ground by the termination. This results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold com-plies with the ±200mV EIA/TIA-485 standard.Receiver Enable(MAX3281E and MAX3283E only)The MAX3281E and MAX3283E feature a receiver out-put enable (EN, MAX3281E or EN , MAX3283E) input that controls the receiver. The MAX3281E receiver enable (EN) pin is active high, meaning the receiver outputs are active when EN is high. The MAX3283E receiver enable (EN ) pin is active low. Receiver outputs are high impedance when the MAX3281E ’s EN pin is low and when the MAX3283E ’s EN pin is high.(MAX3284E only)An increasing number of applications now operate at low-voltage logic levels. To enable compatibility with these low-voltage logic level applications, such as digi-tal FPGAs, the MAX3284E V L pin is a user-defined sup-ply voltage that designates the voltage threshold for a logic high.At lower V L voltages, the data rate will also be lower. A logic-high level of 1.65V will receive data at 20Mbps.Table 2 gives data rates at various voltages at V L .Applications InformationPropagation Delay MatchingThe MAX3280E/MAX3281E/MAX3283E/MAX3284E (V CC = V L ) exhibit propagation delays that are closely matched from one device to another, even between devices from different production lots. This feature allows multiple data lines to receive data and clock sig-nals with minimal skew with respect to each other.Figure 5 shows the typical propagation delays. Small receiver skew times, the difference between the low-to-high and high-to-low propagation delay, help maintain a symmetrical ratio (50% duty cycle). The receiver skewtime | t PLH - t PHL | is under 2ns for either a 3.3V supply or a 5V supply.Multidrop Clock DistributionLow package-to-package skew (8ns max) makes the M A X 3280E /M A X 3281E /M A X 3283E /M A X 3284E (V CC = V L )ideal for multidrop clock distribution. When distributing a clock signal to multiple circuits over long transmission lines, receivers in separate locations, and possibly at two different temperatures, would ideally±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers 6_______________________________________________________________________________________Table 1. MAX3281E/MAX3283E Enable TableTable 2. MAX3284E Data Rate Tableprovide the same clock to their respective circuits.Thus, minimal package-to-package skew is critical. The skew must be kept well below the period of the clock signal to ensure that all of the circuits on the network are synchronized.128 Receivers on the BusThe standard RS-485 input impedance is 12k Ω(one-unit load). The standard RS-485 transmitter can drive 32 unit loads. The MAX3280E/MAX3281E/MAX3283E/MAX3284E present a 1/4-unit-load input impedance(48k Ω), which allows up to 128 receivers on the bus.Any combination of these RS-485 receivers with a total of 32 unit loads can be connected to the same bus.Thermal ProtectionThe MAX3280E/MAX3281E/MAX3283E/MAX3284E fea-ture thermal protection. Thermal protection sets the out-put stage in high-impedance mode when a short circuit occurs at the output, limiting both the power dissipation and temperature. The thermal temperature threshold is +165°C, with a hysteresis of 20°C.MAX3280E/MAX3281E/MAX3283E/MAX3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers_______________________________________________________________________________________7Test Circuits/Timing DiagramsFigure 2. MAX3281E/MAX3283E Receiver Enable/Disable TimingM A X 3280E /M A X 3281E /M A X 3283E /M A X 3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers 8_______________________________________________________________________________________Test Circuits/Timing Diagrams (continued)Figure 3a. Human Body ESD Test ModelFigure 3b. Human Body Model Current WaveformFigure 4a. IEC 1000-4-2 ESD Test ModelFigure 4b. IEC 1000-4-2 ESD Generator Current Waveform10nsB = GNDFigure 5. Receiver Propagation Delay Driven by External RS-485 DeviceMAX3280E/MAX3281E/MAX3283E/MAX3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers_______________________________________________________________________________________9Typical Operating CircuitPin ConfigurationsChip InformationTRANSISTOR COUNT: 233PROCESS: BiCMOSM A X 3280E /M A X 3281E /M A X 3283E /M A X 3284E±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe Receivers 10______________________________________________________________________________________Package InformationMAX3280E/MAX3281E/MAX3283E/MAX3284E ±15kV ESD-Protected 52Mbps, 3V to 5.5V , SOT23RS-485/RS-422 True Fail-Safe ReceiversMa xim ca nnot a ssume responsibility for use of a ny circuitry other tha n circuitry entirely embodied in a Ma xim product. No circuit pa tent licenses a re implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________11©2002 Maxim Integrated Products Printed USAis a registered trademark of Maxim Integrated Products.Package Information (continued)元器件交易网。

1-146HHigh CMR, High Speed TTL Compatible Optocouplers Technical Data6N137HCNW137HCNW2601HCNW2611HCPL-0600HCPL-0601HCPL-0611HCPL-0630CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.Features• 5 kV/µs Minimum Common Mode Rejection (CMR) at V CM = 50 V for HCPL-X601/X631, HCNW2601 and10kV/µs Minimum CMR at V CM = 1000 V for HCPL-X611/X661, HCNW2611• High Speed: 10 MBd Typical • LSTTL/TTL Compatible • Low Input Current Capability: 5 mA• Guaranteed ac and dcPerformance over Temper-ature: -40°C to +85°C • Available in 8-Pin DIP,SOIC-8, Widebody Packages • Strobable Output (Single Channel Products Only)• Safety ApprovalUL Recognized - 2500 V rms for 1 minute and 5000V rms*for 1 minute per UL1577CSA ApprovedVDE 0884 Approved with V IORM = 630 V peak forHCPL-2611 Option 060 and V IORM =1414 V peak for HCNW137/26X1BSI Certified(HCNW137/26X1 Only)• MIL-STD-1772 Version Available (HCPL-56XX/66XX)Functional Diagram*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.HCPL-0631HCPL-0661HCPL-2601HCPL-2611HCPL-2630HCPL-2631HCPL-4661Applications• Isolated Line Receiver • Computer-Peripheral Interfaces• Microprocessor System Interfaces• Digital Isolation for A/D,D/A Conversion• Switching Power Supply • Instrument Input/Output Isolation• Ground Loop Elimination • Pulse Transformer Replacement• Power Transistor Isolation in Motor Drives• Isolation of High Speed Logic SystemsDescriptionThe 6N137, HCPL-26XX/06XX/4661, HCNW137/26X1 are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed.The output of the detector IC isA 0.1 µF bypass capacitor must be connected between pins 5 and 8.CATHODEANODE GNDV V CC O ANODE 2CATHODE 2CATHODE 1ANODE 1GNDV V CC O2V E V O16N137, HCPL-2601/2611 HCPL-0600/0601/0611 HCPL-2630/2631/4661 NC NCLED ON OFF ON OFF ON OFFENABLEH H L L NC NCOUTPUTL H H H L HTRUTH TABLE (POSITIVE LOGIC)LED ON OFFOUTPUTL HTRUTH TABLE (POSITIVE LOGIC)5965-3594Ean open collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/µs for the HCPL-X601/X631 and HCNW2601, and 10,000 V/µs for the HCPL-X611/X661 and HCNW2611.This unique design providesmaximum ac and dc circuitisolation while achieving TTLcompatibility. The optocoupler acand dc operational parametersare guaranteed from -40°C to+85°C allowing troublefreesystem performance.The 6N137, HCPL-26XX, HCPL-06XX, HCPL-4661, HCNW137,and HCNW26X1 are suitable forhigh speed logic interfacing,input/output buffering, as linereceivers in environments thatconventional line receiverscannot tolerate and are recom-mended for use in extremely highground or induced noiseenvironments.Selection GuideNotes:1. Technical data are on separate HP publications.2. 15 kV/µs with V CM = 1 kV can be achieved using HP application circuit.3. Enable is available for single channel products only, except for HCPL-193X devices.1-1471-148Ordering InformationSpecify Part Number followed by Option Number (if desired).Example:HCPL-2611#XXX020 = 5000 V rms/1 minute UL Rating Option*060 = VDE 0884 V IORM = 630 Vpeak Option**300 = Gull Wing Surface Mount Option†500 = Tape and Reel Packaging OptionOption data sheets available. Contact Hewlett-Packard sales representative or authorized distributor for information.*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only.**For HCPL-2611 only. Combination of Option 020 and Option 060 is not available.†Gull wing surface mount option applies to through hole parts only.SchematicV FUSE OF A 0.1 µF BYPASS CAPACITOR CONNECTEDBETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).V CC V OGNDE6N137, HCPL-2601/2611 HCPL-0600/0601/0611V V CC V O1V V O2GNDHCPL-2630/2631/4661 HCPL-0630/0631/0661+ 0.076- 0.051(0.010+ 0.003)- 0.002)DIMENSIONS IN MILLIMETERS AND (INCHES).*MARKING CODE LETTER FOR OPTION NUMBERS"L" = OPTION 020"V" = OPTION 060OPTION NUMBERS 300 AND 500 NOT MARKED. Package Outline Drawings8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)8-pin DIP Package with Gull Wing Surface Mount Option 300(6N137, HCPL-2601/11/30/31, HCPL-4661)**JEDEC Registered Data (for 6N137 only).(0.025 ± 0.005)1.080 ± 0.320MAX.(0.100)BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).+ 0.076- 0.051+ 0.003)- 0.002)1-1491-150Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)(0.012)MIN.DIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).1.78 ± 0.15 + 0.076 - 0.0051+ 0.003) - 0.002)1-1518-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300(HCNW137, HCNW2601/11)Note: Use of nonchlorine activated fluxes is highly recommended.Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount Option 300 Parts)240TIME – MINUTEST E M P E R A T U R E – °C2202001801601401201008060402002601.78 ± 0.15 MAX.BSCDIMENSIONS IN MILLIMETERS (INCHES).LEAD COPLANARITY = 0.10 mm (0.004 INCHES).Regulatory Information The 6N137, HCPL-26XX/06XX/ 46XX, and HCNW137/26XX have been approved by the following organizations:ULRecognized under UL 1577, Component Recognition Program, File E55361.CSAApproved under CSA ComponentAcceptance Notice #5, File CA88324.VDEApproved according to VDE0884/06.92. (HCPL-2611 Option060 and HCNW137/26X1 only)BSICertification according toBS415:1994(BS EN60065:1994),BS7002:1992(BS EN60950:1992) andEN41003:1993 for Class IIapplications. (HCNW137/26X1only)Insulation and Safety Related Specifications8-pin DIP Widebody(300 Mil)SO-8(400 Mil)Parameter Symbol Value Value Value Units Conditions Minimum External L(101)7.1 4.99.6mm Measured from input terminals Air Gap (External to output terminals, shortest Clearance)distance through air. Minimum External L(102)7.4 4.810.0mm Measured from input terminals Tracking (External to output terminals, shortest Creepage)distance path along body. Minimum Internal0.080.08 1.0mm Through insulation distance, Plastic Gap conductor to conductor, usually (Internal Clearance)the direct distance between thephotoemitter and photodetectorinside the optocoupler cavity. Minimum Internal NA NA 4.0mm Measured from input terminals Tracking (Internal to output terminals, along Creepage)internal cavity.Tracking Resistance CTI200200200Volts DIN IEC 112/VDE 0303 Part 1 (ComparativeTracking Index)Isolation Group IIIa IIIa IIIa Material Group(DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802.1-1521-153VDE 0884 Insulation Related Characteristics (HCPL-2611 Option 060 Only)*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only)*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.Absolute Maximum Ratings* (No Derating Required up to 85°C)*JEDEC Registered Data (for 6N137 only).**Ratings apply to all devices except otherwise noted in the Package column.†0°C to 70°C on JEDEC Registration.Recommended Operating ConditionsParameter Symbol Min.Max.Units Input Current, Low Level I FL*0250µAInput Current, High Level[1]I FH**515mA Power Supply Voltage V CC 4.5 5.5VLow Level Enable Voltage†V EL00.8VHigh Level Enable Voltage†V EH 2.0V CC V Operating Temperature T A-4085°CFan Out (at R L = 1 kΩ)[1]N5TTL Loads Output Pull-up Resistor R L330 4 kΩ*The off condition can also be guaranteed by ensuring that V FL≤0.8 volts.**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband.†For single channel products only.1-154Electrical SpecificationsOver recommended temperature (T A = -40°C to +85°C) unless otherwise specified. All Typicals at V CC = 5 V, T A = 25°C. All enable test conditions apply to single channel products only. See note 5.*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.1-155Switching Specifications (AC)Over Recommended Temperature (T A = -40°C to +85°C), V CC = 5 V, I F= 7.5 mA unless otherwise specified. All Typicals at T A = 25°C, V CC = 5 V.*JEDEC registered data for the 6N137.**Ratings apply to all devices except otherwise noted in the Package column.1-156Package Characteristics= 25°C.All Typicals at T**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”†For 6N137, HCPL-2601/2611/2630/2631/4661 only.Notes:1. Each channel.2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current doesnot exceed 20 mA.3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current doesnot exceed 15 mA.4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated inFigure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.6. The JEDEC registration for the 6N137 specifies a maximum I OH of 250 µA. HP guarantees a maximum I OH of 100 µA.7. The JEDEC registration for the 6N137 specifies a maximum I CCH of 15 mA. HP guarantees a maximum I CCH of 10 mA.8. The JEDEC registration for the 6N137 specifies a maximum I CCL of 18 mA. HP guarantees a maximum I CCL of 13 mA.9. The JEDEC registration for the 6N137 specifies a maximum I EL of –2.0 mA. HP guarantees a maximum I EL of -1.6 mA.10. The t PLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on therising edge of the output pulse.11. The t PHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on thefalling edge of the output pulse.12. t PSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specifiedtest conditions.13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.14. The t ELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 Vpoint on the rising edge of the output pulse.15. The t EHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V pointon the falling edge of the output pulse.16. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state(i.e., V O > 2.0 V).17. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state(i.e., V O < 0.8 V).18. For sinusoidal voltages, (|dV CM | / dt)max = πf CM V CM(p-p).1-1571-158I O H – H I G H L E V E L O U T P U T C U R R E N T – µAT A – TEMPERATURE – °C1015519. No external pull up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC will result inimproved CMR performance. For single channel products only.20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second(leakage detection current limit, I I-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second(leakage detection current limit, I I-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel productsonly.24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.Figure 2. Typical Output Voltage vs. Forward Input Current.Figure 3. Typical Input Threshold Current vs. Temperature.Figure 1. Typical High Level Output Current vs. Temperature.1623I F – FORWARD INPUT CURRENT – mA 0V O – O U T P U T V O L T A G E – V8-PIN DIP, SO-81623I F – FORWARD INPUT CURRENT – mAV O – O U T P U T V O L T A G E – VWIDEBODY6360T A – TEMPERATURE – °C 20I T H – I N P U T T H R E S H O L D C U R R E N T – m A1458-PIN DIP, SO-86360T A – TEMPERATURE – °C20I T H – I N P U T T H R E S H O L D C U R R E N T – m A145WIDEBODY1-159706060T A – TEMPERATURE – °C5020I O L – L O W L E V E L O U T P U T C U R R E N T – m A400.80.460T A – TEMPERATURE – °C 0.20V O L – L O W L E V E L O U T P U T V O L T A G E – V0.10.50.7WIDEBODY0.30.6Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.Figure 4. Typical Low Level Output Voltage vs. Temperature.Figure 5. Typical Low Level Output Current vs. Temperature.Figure 6. Typical Input Diode Forward Characteristic.0.80.4T A – TEMPERATURE – °C 0.20V O L – L O W L E V E L O U T P U T V O L T A G E – V0.10.50.78-PIN DIP, SO-80.30.6I F – F O R W A R D C U R R E N T – m A0.001V F – FORWARD VOLTAGE – V 1.010000.010.110100I F – F O R W A R D C U R R E N T – m A0.001V F – FORWARD VOLTAGE – V1.01100.010.110100d V F /d T – F O R W A R D V O L T A G E T E M P E R A T U R E C O E F F I C I E N T – m V /°C0.1110100I F – PULSE INPUT CURRENT – mA -1.4-2.2-2.0-1.8-1.6-1.2-2.48-PIN DIP, SO-8d V F /d T – F O R W A R D V O L T A G E T E M P E R A T U R E C O E F F I C I E N T – m V /°C0.1110100I F – PULSE INPUT CURRENT – mA-1.9-2.2-2.1-2.0-1.8-2.3WIDEBODY1-1604030T A – TEMPERATURE – °C 20P W D – P U L S E W I D T H D I S T O R T I O N – n s10-10Figure 8. Test Circuit for t PHL and t PLH .Figure 9. Typical Propagation Delay vs. Temperature.Figure 10. Typical Propagation Delay vs. Pulse Input Current.Figure 11. Typical Pulse Width Distortion vs. Temperature.Figure 12. Typical Rise and Fall Time vs. Temperature.10590I F – PULSE INPUT CURRENT – mA7530t P – P R O P A G A T I O N D E L A Y – n s6045OUTPUT V MONITORING NODEOOUTPUT V MONITORING NODEOI V FF*C L IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.10080T A – TEMPERATURE – °C600t P – P R O P A G A T I O N D E L A Y – n s4020t r , t f – R I S E , F A L L T I M E – n sT A – TEMPERATURE – °C1-161OUTPUT V MONITORING NODEOV V*C IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.LFigure 13. Test Circuit for t EHL and t ELH .Figure 14. Typical Enable Propagation Delay vs. Temperature.Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.V O0.5 VOV (MIN.)5 V0 V FSWITCH AT B: I = 7.5 mA FCM V HCM CM L OV (MAX.)CMV (PEAK)V Ot E– E N A B L E P R O P A G A T I O N D E L A Y – n sT A – TEMPERATURE – °C901203060+5 VOUTPUT V MONITORING NODE O PULSE GENERATOR Z = 50 ΩO+5 VOUTPUT V MONITORING NODEO PULSE GENERATOR Z = 50 ΩO1-162Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.Figure 17. Recommended Printed Circuit Board Layout.O U T P U T P O W E R – P S , I N P U T C U R R E N T – I S0T S – CASE TEMPERATURE – °C400600800200100300500700ENABLE(SEE NOTE 5)OUTPUTDEVICE ILLUSTRATED.O U T P U T P O WE R – P S , I N P U T C U R R E N T – I S0T S – CASE TEMPERATURE – °C 4006008002001003005007001-163VDUAL CHANNEL DEVICE CC2*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.VCC2Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga-tion delay from low to high (t PLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure8).Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232,RS422, T-l, etc.).Propagation delay skew, t PSK, is an important parameter to consider in parallel data applica-tions where synchronization ofsignals on parallel data lines is aconcern. If the parallel data isbeing sent through a group ofoptocouplers, differences inpropagation delays will cause thedata to arrive at the outputs of theoptocouplers at different times. Ifthis difference in propagationdelays is large enough, it willdetermine the maximum rate atwhich parallel data can be sentthrough the optocouplers.Propagation delay skew is definedas the difference between theminimum and maximumpropagation delays, either t PLH ort PHL, for any given group ofoptocouplers which are operatingunder the same conditions (i.e.,the same drive current, supplyvoltage, output load, andoperating temperature). Asillustrated in Figure 19, if theinputs of a group of optocouplersare switched either ON or OFF atthe same time, t PSK is thedifference between the shortestpropagation delay, either t PLH ort PHL, and the longest propagationdelay, either t PLH or t PHL.As mentioned earlier, t PSK candetermine the maximum paralleldata transmission rate. Figure 20is the timing diagram of a typicalparallel data application with boththe clock and the data lines beingsent through optocouplers. Thefigure shows data and clocksignals at the inputs and outputsof the optocouplers. To obtain themaximum data transmission rate,both edges of the clock signal arebeing used to clock the data; ifonly one edge were used, theclock signal would need to betwice as fast.Propagation delay skew repre-sents the uncertainty of where anedge might be after being sentthrough an optocoupler. Figure20 shows that there will beuncertainty in both the data andthe clock lines. It is importantthat these two areas of uncertaintynot overlap, otherwise the clocksignal might arrive before all ofthe data outputs have settled, orsome of the data outputs maystart to change before the clocksignal has arrived. From theseconsiderations, the absoluteminimum pulse width that can besent through optocouplers in aparallel application is twice t PSK. Acautious design should use aslightly longer pulse width toensure that any additionaluncertainty in the rest of thecircuit does not cause a problem.The t PSK specified optocouplersoffer the advantages ofguaranteed specifications forpropagation delays, pulsewidthdistortion and propagation delayskew over the recommendedtemperature, input current, andpower supply ranges.1-1641-165Figure 19. Illustration of Propagation Delay Skew - t PSK .Figure 20. Parallel Data Transmission Example.I FV OI FVODATAINPUTSCLOCKDATAOUTPUTSCLOCK。

第32卷第3期2000年5月四川大学学报(工程科学版)J OURNA L OF SICHUAN UNIVERSITY(ENGINEERING SCIENCE EDITIO N)Vol.32No.3May2000文章编号:1009-3087(2000)03-0058-03MAX26系列数字编码式滤波器的使用方法羿飒,田远富(四川大学电气信息学院,成都610065)摘要:主要介绍MAX26系列4阶开关电容滤波器的使用方法。

给出了其引脚图及各引脚功能,指明了其使用的电压频率范围,说明了如何进行模式选择以及在不同模式下频率编码输入端和Q值编码输入端的设定。

总结了其性能优点,特别指出了实际应用中应注意的问题。

并在理论计算的基础上,设计出用MAX267实现中心频率220 Hz,带宽6.875Hz的带通滤波电路,进一步通过实验测试,验证了MAX26系列数字滤波器的滤波效果。

关键词:数字滤波器;中心频率;带宽中图分类号:TN713.92文献标识码:AUsage of MAX26Series Digital FilterY I Sa,TIAN Y uan-f u(College of Electrical Informati on,Sichuan Uni v.,Chengdu610065,Chi na)Abstract:This paper mainly introduces the operation methods of the MAX26series four-order on-off capacitance filter. We provide the pin description,show clearly the applicable range of volt and frequency,demonstrate how to select mode and set up the frequency-encode input and Q value-encode input under each mode,summarize the virtues of properties, especially point out the problems which should be a ware of in actual applications.Then on the basis of theoretic calcula-tion,we have designed the band-pass filter circuit,which can realize center frequenc y220Hz,bandwidth6.875Hz by using MAX267.Through experimental test,take further steps to verify the filter effect of MAX26series digital filter. Key words:digital filter;center frequenc y;bandwidthMAX263/264/267/268是MAXIM公司新推出的4种应用非常广泛的4阶开关电容滤波器。

PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)MAX3221CDB ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CDBE4ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CDBG4ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CDBR ACTIVE SSOP DB162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CDBRG4ACTIVE SSOP DB162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPW ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPWE4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPWG4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPWR ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPWRE4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221CPWRG4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDB ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDBE4ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDBG4ACTIVE SSOP DB1680Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDBR ACTIVE SSOP DB162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDBRE4ACTIVE SSOP DB162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IDBRG4ACTIVE SSOP DB162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPW ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPWE4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPWG4ACTIVE TSSOP PW1690Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPWR ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPWRE4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMMAX3221IPWRG4ACTIVE TSSOP PW162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to 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