W981208BH中文资料

Features Array•8-bit Microcontroller Compatible with MCS®51 Products•Enhanced 8051 Architecture–Single Clock Cycle per Byte Fetch–Up to 20 MIPS Throughput at 20 MHz Clock Frequency–Fully Static Operation: 0 Hz to 20 MHz–On-chip 2-cycle Hardware Multiplier–128 x 8 Internal RAM–4-level Interrupt Priority•Nonvolatile Program Memory–2K Bytes of In-System Programmable (ISP) Flash Memory–Endurance: Minimum 10,000 Write/Erase Cycles–Serial Interface for Program Downloading–32-byte Fast Page Programming Mode–64-byte User Signature Array–2-level Program Memory Lock for Software Security•Peripheral Features–Two 16-bit Enhanced Timer/Counters–Two 8-bit PWM Outputs–Enhanced UART with Automatic Address Recognition and FramingError Detection–Enhanced Master/Slave SPI with Double-buffered Send/Receive–Programmable Watchdog Timer with Software Reset–Analog Comparator with Selectable Interrupt and Debouncing–8 General-purpose Interrupt Pins•Special Microcontroller Features–Two-wire On-chip Debug Interface–Brown-out Detection and Power-on Reset with Power-off Flag–Internal 8 MHz RC Oscillator–Low Power Idle and Power-down Modes–Interrupt Recovery from Power-down Mode•I/O and Packages–Up to 14 Programmable I/O Lines–Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, andOpen-drain Modes–5V Tolerant I/O–16-lead TSSOP, SOIC or PDIP•Operating Conditions–2.4V to 5.5V V CC Voltage Range–-40⋅C to 85°C Temperature Range1.DescriptionThe AT89LP216 is a low-power, high-performance CMOS 8-bit microcontroller with 2K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel®'s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The AT89LP216 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-tions to execute in 12, 24 or 48 clock cycles. In the AT89LP216 CPU, instructions23621C–MICRO–6/08AT89LP216need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051.Seventy percent of instructions need only as many clock cycles as they have bytes to execute,and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. The AT89LP216 provides the following standard features: 2K bytes of In-System Programmable Flash memory, 128 bytes of RAM, up to 14 I/O lines, two 16-bit timer/counters, two PWM out-puts, a programmable watchdog timer, a full duplex serial port, a serial peripheral interface, an internal 8MHz RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system.The two timer/counters in the AT89LP216 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may independently drive a pulse width modulation output.The I/O ports of the AT89LP216 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode pro-vides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt using the general-purpose interrupt interface. The I/O pins of the AT89LP216 tolerate voltages higher than the device’s own power supply, up to 5.5V. When the device is supplied at 2.4V and all I/O ports receive 5.5V, the total back flowing current in all I/Os is less than 100 µA.2.Pin Configuration2.116-lead PDIP/SOIC/TSSOP33621C–MICRO–6/08AT89LP2163.Pin DescriptionTable 3-1.Pin DescriptionPinSymbolType Description1P1.5I/O I/O I P1.5: User-configurable I/O Port 1 bit 5.MOSI : SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input.GPI5: General-purpose Interrupt input 5.2P1.7I/O I/O I P1.7: User-configurable I/O Port 1 bit 7.SCK : SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input.GPI7: General-purpose Interrupt input 7.3P1.3I/O I I I P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled).RST : External Active-Low Reset input (if Reset Fuse is enabled, see Section 10.3 “External Reset” on page 15)GPI3: General-purpose Interrupt input 3.DCL : Serial Clock input for On-Chip Debug Interface when OCD is enabled.4GND I Ground5P1.2I/O I P1.2: User-configurable I/O Port 1 bit 2.GPI2: General-purpose Interrupt input 2.6P3.0I/O I P3.0: User-configurable I/O Port 3 bit 0.RXD : Serial Port Receiver Input.7P3.4I/O I/O P3.4: User-configurable I/O Port 3 bit 4.T0: Timer/Counter 0 External Input or PWM Output.8P3.2I/O II/O P3.2: User-configurable I/O Port 3 bit 2.XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source.DDA : Serial Data input/output for On-Chip Debug Interface when OCD is enabled and the internal RC oscillator is selected as the clock source.9P3.3I/O OO I/O P3.3: User-configurable I/O Port 3 bit 3.XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal RC oscillator is selected as the clock source.CLKOUT : When the internal RC oscillator is selected as the clock source, may be used to output the internal clock divided by 2.DDA : Serial Data input/output for On-Chip Debug Interface when OCD is enabled and the external clock is selected as the clock source.10P3.5I/O I/O P3.5: User-configurable I/O Port 3 bit 5.T1: Timer/Counter 1 External input or PWM output.11P3.1I/O O P3.1: User-configurable I/O Port 3 bit 1.TXD : Serial Port T ransmitter Output.12VDD I Supply Voltage13P1.0I/O I I P1.0: User-configurable I/O Port 1 bit 0.AIN0: Analog Comparator Positive input.GPI0: General-purpose Interrupt input 0.14P1.1I/O I I P1.1: User-configurable I/O Port 1 bit 1.AIN1: Analog Comparator Negative input.GPI1: General-purpose Interrupt input 115P1.4I/O I I P1.4: User-configurable I/O Port 1 bit 4.SS : SPI slave select input.GPI4: General-purpose Interrupt input 4.16P1.6I/O I/O IP1.6: User-configurable I/O Port 1 bit 6.MISO : SPI master-in/slave-out. When configured as master, this pin is an input. When configured as slave, this pin is an output.GPI6: General-purpose Interrupt input 6.43621C–MICRO–6/08AT89LP2164.Block DiagramFigure 4-1.AT89LP216 Block Diagramparison to Standard 8051The AT89LP216 is part of a family of devices with enhanced features that are fully binary com-patible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel’s existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs.5.1System ClockThe CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer divided by 2 to provide the internal clock and x2 mode is not supported.5.2Instruction Execution with Single-cycle FetchThe CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See “Instruction Set Summary” on page 59 for more details.53621C–MICRO–6/08AT89LP2165.3Interrupt HandlingThe interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle.every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response,this leads to a higher maximum rate of incidence for the external interrupts.5.4Timer/CountersBy default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the prescaler (Table 9-2 on page 13). Setting TPS = 1011B will cause the timers to count once every 12 clocks.The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function.5.5Serial PortThe baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock fre-quency in the standard 8051; and output data is only stable around the rising edge of the serial clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP216 while running at the same frequency as a standard 8051,the time-out period must be 12times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates.5.6Watchdog TimerThe Watchdog Timer in AT89LP216 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the counting rate.5.7I/O PortsThe I/O ports of the AT89LP216 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also con-figure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse.When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be weakly pulled high.5.8Resetdard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.63621C–MICRO–6/08AT89LP2166.Memory OrganizationThe AT89LP216 uses a Harvard Architecture with separate address spaces for program and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 128 bytes of internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP216 does not support external data memory or external program memory.6.1Program MemoryThe AT89LP216 contains 2K bytes of on-chip In-System Programmable Flash memory for pro-gram storage. The Flash memory has an endurance of at least 10,000 write/erase cycles and a minimum data retention time of 10 years. The reset and interrupt vectors are located within the first 59 bytes of program memory (refer to Table 12-1 on page 19). Constant tables can be allo-cated within the entire 2K program memory address space for access by the MOVC instruction.The AT89LP216 does not support external program memory.Figure 6-1.Program Memory MapA map of the AT89LP216 program memory is shown in Figure 6-1. In addition to the 2K code space from 0000h to 07FFh, the AT89LP216 also supports a 64-byte User Signature Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fashion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While SIGEN is one,MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped to addresses 0040h to 007Fh and the Atmel Signature Array is mapped to addresses 0000h to 001Fh. SIGEN must be cleared before using MOVC to access the code memory.The Atmel Signature Array is initialized with the Device ID in the factory. The User Signature Array is available for user identification codes or constant parameter data. Data stored in the sig-nature array is not secure. Security bits will disable writes to the array; however, reads are always allowed.Table 6-1.AUXR1 – Auxiliary Register 1AUXR1 = A2H Reset Value = XXXX 0XXXBNot Bit Addressable––––SIGEN –––Bit765432173621C–MICRO–6/08AT89LP2166.2Data MemoryThe AT89LP216 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O mem-ory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128 bytes of I/O memory reside in the upper 128 byte address space (Figure 6-2). The I/O memory can only be accessed through direct addressing and contains the Special Function Registers (SFRs).Indirect accesses to the upper 128 byte addresses will return invalid data. The lowest 32bytes of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3and PSW.4) select which register bank is in use. Instructions using register addressing will only access the currently specified bank. The AT89LP216 does not support external data memory.Figure 6-2.Data Memory Map83621C–MICRO–6/08AT89LP2167.Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 7-1.Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features.Notes:1.All SFRs in the left-most column are bit-addressable.2.Reset value is xx111111B when Tristate-Port Fuse is enabled and xx000000B when disabled.Table 7-1.AT89LP216 SFR Map and Reset Values89ABCDEF0F8H 0FFH 0F0H B000000000F7H 0E8H SPSR 000x x000SPCR 00000000SPDR xxxx xxxx0EFH 0E0H ACC 000000000E7H 0D8H 0DFH 0D0H PSW 000000000D7H 0C8H0CFH0C0H P1M0(2)P1M1xx000000P3M0(2)P3M1xx0000000C7H 0B8H IP x0000000SADEN 000000000BFH 0B0H P3xx111111IPH x00000000B7H 0A8H IE 00000000SADDR 000000000AFH 0A0HAUXR1xxxx 0xxxWDTRST (write-only)WDTCON 0000x0000A7H 98H SCON 00000000SBUF xxxx xxxx GPMOD 00000000GPLS 00000000GPIEN 00000000GPIF 000000009FH 90H P111111111TCONB 00100100RL000000000RL100000000RH000000000RH100000000ACSR xx00000097H 88H TCON 00000000TMOD 00000000TL000000000TL100000000TH000000000TH100000000CLKREG 0000x0008FH 80HSP 00000111DPL 00000000DPH 00000000PCON 0000000087H123456793621C–MICRO–6/08AT89LP2168.Enhanced CPUThe AT89LP216 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in parallel. This basic pipelining concept allows the CPU to obtain up to 1MIPS per MHz. A simple example is shown in Figure 8-1.The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a sin-gle-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has bytes to execute. The majority of instructions in the AT89LP216 follow this rule: the instruc-tion execution time in clock cycles equals the number of bytes per instruction with a few exceptions. Branches and Calls require an additional cycle to compute the target address and some other complex instructions require multiple cycles. See “Instruction Set Summary” on page 59 for more detailed information on individual instructions. Figures 8-2 and 8-3 show examples of 1- and 2-byte instructions.Figure 8-1.Parallel Instruction Fetches and ExecutionsFigure 8-2.Single-cycle ALU Operation (Example: INC R0)103621C–MICRO–6/08AT89LP216#Data 8.1Restrictions on Certain InstructionsThe AT89LP216 is an economical and cost-effective member of Atmel’s growing family of micro-controllers. It contains 2K bytes of Flash program memory. It is fully compatible with the MCS-51architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89LP216. This should be the responsibility of the software programmer. For example,LJMP 7E0H would be a valid instruction, whereas LJMP 900H would not.8.1.1Branching InstructionsThe LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instruc-tions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (loca-tions 000H to 7FFH for the AT89LP216). Violating the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ condi-tional branching instructions, the same previous rule applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal inter-rupt service routine address locations of the 8051 family architecture have been preserved.8.1.2MOVX-related Instructions, Data MemoryThe AT89LP216 contains 128 bytes of internal data memory. The RAM accesses to addresses above 7FH will return invalid data. Furthermore, the stack depth is limited to 128 bytes, the amount of available RAM. The Stack Pointer should not be allowed to point to locations above 7FH. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program.A typical 8051 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the user to know the physical features and limitations of the device being used and to adjust the instructions used accordingly.AT89LP2169.System ClockThe system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The clock source is selected by the Clock Source User Fuses as shown in Table 9-1. No internal clock division is used to generate the CPU clock from the system clock. See “User Configuration Fuses” on page 71.9.1Crystal OscillatorWhen enabled, the internal inverting oscillator amplifier is connected between XTAL1 and XTAL2 for connection to an external quartz crystal or ceramic resonator as shown in Figure 9-1.Note that in some cases, external capacitors C1 and C2 may NOT be required due to the on-chip capacitance of the XTAL1 and XTAL2 inputs (approximately 10 pF each). When using the crystal oscillator, P3.2 and P3.3 will have their inputs and outputs disabled. When using the crystal oscillator, XTAL2 should not be used to drive a board-level clock without a buffer.Figure 9-1.Note:1. C1, C2=5 pF ± 5pF for Crystals=5 pF ± 5pF for Ceramic ResonatorsTable 9-1.Clock Source SettingsClock SourceFuse 1Clock SourceFuse 0Selected Clock Source 00Crystal Oscillator 01Reserved10External Clock on XT AL111Internal 8 MHz RC Oscillator9.2External Clock SourceThe external clock option disables the oscillator amplifier and allows XTAL1 to be driven directlyby the clock source as shown in Figure 9-2. XTAL2 may be left unconnected, used as P3.3 I/O,or configured to output a divided version of the system clock.Figure 9-2.9.3Internal RC OscillatorThe AT89LP216 has an internal RC oscillator tuned to 8.0 MHz ±1.0% at 5.0V and 25⋅C. Whenenabled as the clock source, XTAL1 and XTAL2 may be used as P3.2 and P3.3, respectively.The XTAL2 may also be configured to output a divided version of the system clock. The fre-quency of the oscillator may be adjusted by changing the RC Adjust Fuses. (See “UserConfiguration Fuses” on page 71.) A copy of the initial factory setting is stored at location 0007hof the Atmel Signature.9.4System Clock OutWhen the AT89LP216 is configured to use either an external clock or the internal RC oscillator,a divided version of the system clock may be output on XTAL2 (P3.3). The Clock Out feature isenabled by setting the COE bit in CLKREG. The two CDV bits determine the clock divide ratio.For example, setting COE = “1” and CDIV = “00” when using the internal oscillator will result in a4.0 MHz clock output on P3.3. P3.3 must be configured as an output in order to use the clock outfeature.AT89LP21610.ResetDuring reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP216 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset.10.1Power-on ResetA Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever V CC is below the detection level. The POR cir-cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A power-on sequence is shown in Figure 10-1. When V CC reaches the Power-on Reset threshold voltage V POR , an initialization sequence lasting t POR is started. When the initialization sequence completes, the start-up timer determines how long the device is kept in POR after V CC rise. The POR signal is activated again, without any delay, when V CC falls below the POR threshold level.A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be extended beyond the power-on period by holding the RST pin low longer than the time-out.Table 9-2.CLKREG – Clock Control RegisterCLKREG = 8FH Reset Value = 0000 0000BNot Bit AddressableTPS3TPS2TPS1TPS0–CDV1CDV0COE Bit7654321Symbol FunctionTPS3TPS2TPS1TPS0Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycles (TPS = 0000B). To configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to 1011B.CDV1CDV0Clock Out Division. Determines the frequency of the clock output relative to the system clock.CDIV1CDIV0Clock Out Frequency 00f/201f/410f/811f/16COEClock Out Enable. Set COE to output a divided version of the system clock on XTAL2 (P3.3). The internal RC oscillator or external clock source must be selected in order to use this feature.Figure 10-1.Power-on Reset Sequence (BOD Disabled)If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after V CC reaches the BOD threshold voltage V BOD as shown in Figure 10-2. However, if this event occurs prior to the end of the initialization sequence, the timer must first wait for that sequence to complete before counting.Figure 10-2.Power-on Reset Sequence (BOD Enabled)Note:t POR is approximately 92 µs ± 5%.The start-up timer delay is user configurable with the Start-up Time User Fuses and depends on the clock source (Table 10-1). The start-up delay should be selected to provide enough settling time for V CC and the selected clock source. The Start-Up Time fuses also control the length of the start-up time after a Brown-out Reset or when waking up from Power-down during internally timed mode.AT89LP21610.2Brown-out ResetThe AT89LP216 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V CC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nomi-nally 2.2V. The purpose of the BOD is to ensure that if V CC fails or dips while executing at speed,the system will gracefully enter reset without the possibility of errors induced by incorrect execu-tion. A BOD sequence is shown in Figure 10-3. When V CC decreases to a value below the trigger level V BOD , the internal reset is immediately activated. When V CC increases above the trigger level, the start-up timer releases the internal reset after the specified time-out period has expired (Table 10-1). The Brown-out Detector must be enabled by setting the BOD Enable Fuse.(See “User Configuration Fuses” on page 71.)10.3External Resetpose I/O,P1.3. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input function on P1.3. (See “User Configuration Fuses” on page 71.) When cleared, P1.3 may be used as an input or output pin. When configured as a reset input, the pin must be held low for at least two clock cycles to trigger the internal reset.Note:During a power-up sequence, the fuse selection is always overridden and therefore the pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset until the pin tran-sitions high . After the power-up delay, this input will function either as an external reset input or as a digital input as defined by the fuse bit. Only a power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources of reset will not override the reset fuse bit. external reset pin is held low. When the reset pin is disabled by the fuse, ISP may only be entered by pulling P1.3 low during power-up.Table 10-1.Start-up Timer SettingsSUT Fuse 1SUT Fuse 0Clock Sourcet SUT (± 5%) 0Internal RC/External Clock 16 µs Crystal Oscillator1024 µs 01Internal RC/External Clock 512 µs Crystal Oscillator2048 µs 10Internal RC/External Clock 1024 µs Crystal Oscillator4096 µs 11Internal RC/External Clock 4096 µs Crystal Oscillator16384 µs。

玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理。

1M × 4 BANKS × 32BITS SDRAM Table of Contents-1.GENERAL DESCRIPTION (3)2.FEATURES (3)3.AVAILABLE PART NUMBER (3)4.BALL CONFIGURATION (4)5.PIN DESCRIPTION (5)6.BLOCK DIAGRAM (6)7.FUNCTIONAL DESCRIPTION (7)7.1.Power Up and Initialization (7)7.2.Programming Mode Register (7)7.3.Bank Activate Command (7)7.4.Read and Write Access Modes (7)7.5.Burst Read Command (8)7.6.Burst Write Command (8)7.7.Read Interrupted by a Read (8)7.8.Read Interrupted by a Write (8)7.9.Write Interrupted by a Write (8)7.10.Write Interrupted by a Read (8)7.11.Burst Stop Command (9)7.12.Addressing Sequence of Sequential Mode (9)7.13.Addressing Sequence of Interleave Mode (9)7.14.Auto-precharge Command (10)7.15.Precharge Command (10)7.16.Self Refresh Command (10)7.17.Power Down Mode (11)7.18.No Operation Command (11)7.19.Deselect Command (11)7.20.Clock Suspend Mode (11)8.OPERATION MODE (12)9.ELECTRICAL CHARACTERISTICS (13)9.1.Absolute Maximum Ratings (13)9.2.Recommended DC Operating Conditions (13)9.3.Capacitance (13)9.4.DC Characteristics (14)9.5.AC Characteristics and Operating Condition (15)10.TIMING WAVEFORMS (17)mand Input Timing (17)10.2.Read Timing (18)10.3.Control Timing of Input/Output Data (19)10.4.Mode Register Set Cycle (20)11.OPERATING TIMING EXAMPLE (21)11.1.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (21)11.2.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) (22)11.3.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (23)11.4.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) (24)11.5.Interleaved Bank Write (Burst Length = 8) (25)11.6.Interleaved Bank Write (Burst Length = 8, Auto-precharge) (26)11.7.Page Mode Read (Burst Length = 4, CAS Latency = 3) (27)11.8.Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) (28)11.9.Auto-precharge Read (Burst Length = 4, CAS Latency = 3) (29)11.10.Auto-precharge Write (Burst Length = 4) (30)11.11.Auto Refresh Cycle (31)11.12.Self Refresh Cycle (32)11.13.Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (33)11.14.Power Down Mode (34)11.15.Auto-precharge Timing (Read Cycle) (35)11.16.Auto-precharge Timing (Write Cycle) (36)11.17.Timing Chart of Read to Write Cycle (37)11.18.Timing Chart of Write to Read Cycle (37)11.19.Timing Chart of Burst Stop Cycle (Burst Stop Command) (38)11.20.Timing Chart of Burst Stop Cycle (Precharge Command) (38)11.21.CKE/DQM Input Timing (Write Cycle) (39)11.22.CKE/DQM Input Timing (Read Cycle) (40)12.PACKAGE SPECIFICATION (41)12.1.TFBGA 90 Balls pitch=0.8mm (41)13.REVISION HISTORY (42)1. GENERAL DESCRIPTIONW9812G2GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9812G2GB delivers a data bandwidth of up to 166MHz words per second (-6). For different application, W9812G2GB is sorted into two speed grades: -6/-6I and -75. The –6 is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G2GB is ideal for main memory in high performance applications.2. FEATURES• 3.3V ± 0.3V Power Supply•Up to 166 MHz Clock Frequency• 1,048,576 Words × 4 banks × 32 bits organization• Self Refresh Mode•CAS Latency: 2 and 3•Burst Length: 1, 2, 4, 8 and full page•Burst Read, Single Writes Mode•Byte Data Controlled by DQM•Auto-precharge and Controlled Precharge•4K Refresh cycles / 64 mS• Interface: LVTTL•Packaged in TFBGA 90 Ball•W9812G2GB is using lead free materials with RoHS compliant3. AVAILABLE PART NUMBERPART NUMBER SPEEDMAXIMUM SELFREFRESH CURRENTOPERATINGTEMPERATUREW9812G2GB-6 166MHz/CL3 2mA 0°C ~ 70°C W9812G2GB-6I 166MHz/CL3 2mA -40°C ~ 85°C W9812G2GB-75 133MHZ/CL3 2mA 0°C ~ 70°C4. BALL CONFIGURATION5. PIN DESCRIPTION6. BLOCK DIAGRAM7. FUNCTIONAL DESCRIPTION7.1. Power Up and InitializationThe default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.During power up, all V DD and V DDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed V DD +0.3V on any of the input pins or V DD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.7.2. Programming Mode RegisterAfter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RA,S CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.7.3. Bank Activate CommandThe Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD). The maximum time that each bank can be held active is specified as t RAS (max).7.4. Read and Write Access ModesAfter a bank has been activated, a read or write cycle can be followed. This is accomplished by setting S RCD delay. WE pin voltage level RAS high and CA low at the clock rising edge after minimum of tdefines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation amongmany different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.7.5. Burst Read CommandThe Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.7.6. Burst Write CommandThe Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.7.7. Read Interrupted by a ReadA Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied.7.8. Read Interrupted by a WriteTo interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.7.9. Write Interrupted by a WriteA burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.7.10. Write Interrupted by a ReadA Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.7.11. Burst Stop CommandA Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop.7.12. Addressing Sequence of Sequential ModeA column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.Table 2 Address Sequence of Sequential Mode7.13. Addressing Sequence of Interleave ModeA column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.Table 3 Address Sequence of Interleave Mode7.14. Auto-precharge CommandIf A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency.A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as Write t WR. The bank undergoing auto-precharge can not be reactivated until t WR and t RP are satisfied. This is referred to as t DAL, Data-in to Active delay (t DAL = t WR + t RP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS (min).7.15. Precharge CommandThe Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t RP).7.16. Self Refresh CommandThe Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t AC cycle time plus the Self Refresh exit time.If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The period between the Auto Refresh command and the next command is specified by t RC.7.17. Power Down ModeThe Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF) of the device.The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK. The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + t CK (min).7.18. No Operation CommandThe No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.7.19. Deselect CommandThe Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.7.20. Clock Suspend ModeDuring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.8. OPERATION MODEFully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.Table 1 Truth Table (Note (1), (2))Notes:(1) v =valid x =Don’t care L =Low Level H =High Level(2) CKEn signal is input level when commands are provided.CKEn-1 signal is the input level one clock cycle before the command is issued.(3) These are state of bank designated by BS0, BS1 signals.(4) Device state is full page burst operation.(5) Power Down Mode can not be entered in the burst cycle.When this command asserts in the burst cycle, device state is clock suspend mode.9. ELECTRICAL CHARACTERISTICS9.1. Absolute Maximum RatingsRATINGUNIT PARAMETER SYMBOLInput/Output Voltage V IN, V OUT -0.3 ~ V DD +0.3 VPower Supply Voltage V DD, V DDQ-0.3 ~ 4.6 VOperating Temperature (-6/-75) T OPR0 ~ 70 °C°C85Operating Temperature (-6I) T OPR -40~°C150Storage Temperature T STG -55~Soldering Temperature (10s) T SOLDER 260 °CW Power Dissipation P D 1mA Short Circuit Output Current I OUT 50Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.9.2. Recommended DC Operating Conditions(Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I)UNIT PARAMETER SYMBOL MIN.MAX.TYP.Power Supply Voltage V DD 3.0 3.3 3.6 VPower Supply VoltageV DDQ 3.0 3.3 3.6 V(for I/O Buffer)V DD +0.3 VInput High Voltage V IH 2.0 -Input Low Voltage V IL -0.3 - 0.8 VNote: V IH(max) = V DD/ V DDQ+1.2V for pulse width < 5 nSV IL(min) = V SS/ V SSQ-1.2V for pulse width < 5 nS9.3. Capacitance(V DD= 3.3V, f = 1 MHz, Ta 25°C)Note: These parameters are periodically sampled and not 100% tested.9.4. DC Characteristics(VDD =3.3V± 0.3V, Ta = 0 to 70°C for-6/-75, Ta= -40 to 85°C for -6I)NOTESUNIT PARAMETER SYMBOL MIN.MAX.Input Leakage CurrentI I(L) -5 5 µA (0V ≤V IN≤ V DD, all other pins not under test = 0V)Output Leakage CurrentI O(L) -5 5 µA (Output disable , 0V ≤ V OUT≤ V DDQ)LVTTL Output ″H″ Level VoltageV OH 2.4 - V(I OUT = -2 mA )LVTTL Output ″L″ Level VoltageV OL - 0.4 V(I OUT = 2 mA )9.5. AC Characteristics and Operating Condition(VDD =3.3V ± 0.3V, Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I, Notes: 5, 6, 7, 8, 9, 10)-6/-6I -75PARAMETER SYM.MIN. MAX. MIN. MAX.UNIT NOTESRef/Active to Ref/Active Command Period t RC 60 65 Active to precharge Command Period t RAS 42 10000045 100000 nSActive to Read/Write Command Delay Timet RCD 18 20 Read/Write(a) to Read/Write(b) Command Periodt CCD 1 1 t CKPrecharge to Active Command Period t RP 18 20 Active(a) to Active(b) Command Period t RRD 12 15 nS CL* = 2 22 t CKWrite Recovery Time CL* = 3 t WR 22CL* = 2 101000101000CLK Cycle TimeCL* = 3t CK6 1000 7.5 1000CLK High Level widtht CH 2 2.5 9 CLK Low Level widtht CL 2 2.59CL* = 2 6 6 Access Time from CLKCL* = 3t AC 5 5.4 10 Output Data Hold Timet OH 3 3 10 Output Data High Impedance Time t HZ 3 6 3 7.5 8 Output Data Low Impedance Time t LZ 0 0 10 Power Down Mode Entry Time t SB 0 6 0 7.5Transition Time of CLK (Rise and Fall) t T 0.1 1 0.1 1 7 Data-in Set-up Time t DS 1.5 1.5 9 Data-in Hold Time t DH 1.0 1.0 9 Address Set-up Time t AS 1.5 1.5 9 Address Hold Time t AH 1.0 1.0 9 CKE Set-up Time t CKS 1.5 1.5 9 CKE Hold Time t CKH 1.0 1.0 9 Command Set-up Time t CMS 1.5 1.5 9 Command Hold Time t CMH 1.0 1.0nS9Refresh Timet REF 64 64 mS Mode register Set Cycle Time t RSC 12 15 nS Exit self refresh to ACTIVE commandt XSR72 75 nS*CL = CAS LatencyNotes:1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.2. All voltages are referenced to V SS3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t CK and t RC .4. These parameters depend on the output loading conditions. Specified values are obtained with output open.5. Power up sequence is further described in the “Functional Description” section.6. AC Testing ConditionsPARAMETER CONDITIONSOutput Reference Level1.4VOutput LoadSee diagram belowInput Signal Levels (V IH /V IL ) 2.4V/0.4VTransition Time (t T : tr/tf) of Input Signal 1/1 nS Input Reference Level 1.4V7. Transition times are measured between V IH and V IL .8. t HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.9. Assumed input transition Time (t T ) = 1nS.If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter(The t T maximum can’t be more than 10nS for low frequency application.)10. If clock rising time (t T ) is longer than 1nS, (t T /2-0.5)nS should be added to the parameter.10. TIMING WAVEFORMS 10.1. Command Input Timing10.2. Read Timing10.3. Control Timing of Input/Output Data10.4. Mode Register Set Cycle11. OPERATING TIMING EXAMPLE11.1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)11.2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)11.3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)11.4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)11.5. Interleaved Bank Write (Burst Length = 8)11.6. Interleaved Bank Write (Burst Length = 8, Auto-precharge)11.7. Page Mode Read (Burst Length = 4, CAS Latency = 3)11.8. Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)11.9. Auto-precharge Read (Burst Length = 4, CAS Latency = 3)11.10. Auto-precharge Write (Burst Length = 4)11.11. Auto Refresh Cycle11.12. Self Refresh Cycle11.13. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)11.14. Power Down Mode11.15. Auto-precharge Timing (Read Cycle)11.17. Timing Chart of Read to Write Cycle11.18. Timing Chart of Write to Read Cycle11.19. Timing Chart of Burst Stop Cycle (Burst Stop Command)11.20. Timing Chart of Burst Stop Cycle (Precharge Command)11.21. CKE/DQM Input Timing (Write Cycle)11.22. CKE/DQM Input Timing (Read Cycle)12. PACKAGE SPECIFICATION12.1. TFBGA 90 Balls pitch=0.8mmPublication Release Date:Aug. 13,2007- 41 - Revision A07Publication Release Date: Aug. 13,2007- 42 - Revision A0713. REVISION HISTORYVERSION DATEPAGEDESCRIPTIONA01 Mar. 24, 2006 All Create new datasheet A02 Jul. 05, 2006 8 Burst Stop commandA03 Sep. 08, 2006 10 Exit Auto refresh to next command is specified by t RC A04 Sep. 27, 200615,16Modify Characteristics Notes 9 and add Notes 10 (t T ) A05 Apr. 12, 2007 15,32,34,41Add t XSR timing specification and package dimension ball openingA06 Jun. 21, 2007 3,13,14,15Add -6I gradeA07 Aug. 13, 200716Revise transient time t T AC test condition and calculate formula for compensation consideration in Notes 6, 9 of AC Characteristics and Operating ConditionImportant NoticeWinbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.。

8M × 4 BANKS × 8 BIT DDR SDRAMPublication Release Date: March 21, 2002Table of Contents-1. GENERAL DESCRIPTION..................................................................................................................3 2. FEATURES..........................................................................................................................................3 3. KEY PARAMETERS............................................................................................................................3 4. PIN CONFIGURATION........................................................................................................................4 5. PIN DESCRIPTION .............................................................................................................................5 6. BLOCK DIAGRAM...............................................................................................................................6 7. ABSOLUTE MAXIMUM RATINGS......................................................................................................7 8. RECOMMENDED DC OPERATING CONDITIONS............................................................................7 9. CAPACITANCE ...................................................................................................................................8 10. LEAKAGE AND OUTPUT BUFFER CHARACTERISTICS...............................................................8 11. DC CHARACTERISTICS...................................................................................................................9 12. AC CHARACTERISTICS AND OPERATING CONDITION.............................................................10 13. AC TEST CONDITIONS..................................................................................................................11 14. OPERATION MODE (13)Simplified Truth Tabl..............................................................................................................................13 Function Truth Table .............................................................................................................................14 Function Truth Table for CKE. (17)15. SIMPLIFIED STATE DIAGRAM ......................................................................................................18 16. FUNCTIONAL DESCRIPTION.. (19)Power Up Sequence..............................................................................................................................19 Command Function...............................................................................................................................19 Read Operation.....................................................................................................................................22 Write Operation .....................................................................................................................................22 Precharge..............................................................................................................................................22 Burst Termination..................................................................................................................................23 Refresh Operation.................................................................................................................................23 Power Down Mode................................................................................................................................23 Mode Register Operation . (23)17. TIMING WAVEFORMS (27)Command Input Timing.........................................................................................................................27 Timing of the CLK Signals.....................................................................................................................27 Read Timing (Burst Length = 4) (28)Write Timing (Burst Length = 4) (29)DM, DATA MASK (W942508BH/W942504BH) (30)DM, DATA MASK (W942516BH) (30)Mode Register Set (MRS) Timing (31)Extend Mode Register Set (EMRS) Timing (32)Auto Precharge Timing (Read cycle, CL = 2) (33)Auto Precharge Timing (Write Cycle) (35)Read Interrupted by Read (CL = 2, BL = 2, 4, 8) (36)Burst Read Stop (BL = 8) (36)Read Interrupted by Write & BST (BL = 8) (37)Read Interrupted by Precharge (BL = 8) (37)Write Interrupted by Write (BL = 2, 4, 8) (38)Write Interrupted by Read (CL = 2, BL = 8) (38)Write Interrupted by Read (CL = 2.5, BL = 4) (39)Write Interrupted by Precharge (BL = 8) (39)2 Bank Interleave Read Operation (CL = 2, BL = 2) (40)2 Bank Interleave Read Operation (CL = 2, BL = 4) (40)4 Bank Interleave Read Operation (CL = 2, BL = 2) (41)4 Bank Interleave Read Operation (CL = 2, BL = 4) (41)Auto Refresh Cycle (42)Active Power Down Mode Entry and Exit Timing (42)Precharged Power Down Mode Entry and Exit Timing (42)Self Refresh Entry and Exit Timing (43)18. PACKAGE DIMENSION (44)TSOP 66l – 400 mil (44)19. VERSION HISTORY (45)Publication Release Date: March 21, 20021. GENERAL DESCRIPTIONW942508BH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 8,388,608 words × 4 banks × 8 bits. Using pipelined architecture and 0.175 µm process technology, W942508BH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942508BH is sorted into three speed grades: -6, -7, -75 The -6 is compliant to the 166 MHz/CL2.5 specification.All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe).By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942508BH is ideal for main memory in high performance applications.2. FEATURES• 2.5V ±0.1V Power Supply• Up to 166 MHz Clock Frequency• Double Data Rate architecture; two data transfers per clock cycle • Differential clock inputs (CLK and CLK )• DQS is edge-aligned with data for Read; center-aligned with data for Write • CAS Latency: 2 and 2.5 • Burst Length: 2, 4 and 8• Auto Refresh and Self Refresh• Precharged Power Down and Active Power Down • Write Data Mask• Write Latency = 1• 8K Refresh cycles / 64 mS• Interface: SSTL-2• Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65mm pin pitch3. KEY PARAMETERSSYMBOLDESCRIPTIONMIN./MAX.-6t CK Clock Cycle Time CL = 2 7.5 nS Min. CL = 2.5 6 nS Min. t RAS Active to Precharge Command Period Min. 42 nS t RC Active to Ref/Active Command Period Min. 60 nS I DD1 Operation Current (Single bank) Max. 110 mA I DD4 Burst Operation Current Max. 165 mA I DD6 Self-refresh Current Max. 3 mA4. PIN CONFIGURATIONPublication Release Date: March 21, 20025. PIN DESCRIPTION6. BLOCK DIAGRAMCKEA10Publication Release Date: March 21, 20027. ABSOLUTE MAXIMUM RATINGSPARAMETERSYMBOL RATING UNIT Input/Output Voltage V IN , V OUT -0.3 − V DDQ +0.3VPower Supply Voltage V DD , V DDQ-0.3 − 3.6 VOperating Temperature T OPR 0 − 70 °C Storage Temperature T STG -55 − 150 °C Soldering Temperature (10s) T SOLDER260 °C Power DissipationP D 1 W Short Circuit Output CurrentI OUT50mANote: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.8. RECOMMENDED DC OPERATING CONDITIONS(T A = 0 to 70 °C)Notes: Undershoot Limit: V IL (min.) = -0.9V with a pulse width < 5 nSOvershoot Limit: V IH (max.) = V DDQ +0.9V with a pulse width < 5 nS V IH (DC) and V IL (DC) are levels to maintain the current logic state. V IH (AC) and V IL (AC) are levels to change to the new logic state.9. CAPACITANCE(V DD = V DDQ = 2.5V ±0.2V, f = 1 MHz, T A = 25°C, V OUT (DC) = V DDQ /2, V OUT (Peak to Peak) = 0.2V)SYMBOL PARAMETERMIN. MAX. DELTA (MAX.) UNIT C IN Input Capacitance (except for CLK pins) 2.0 3.0 0.5 pF C CLK Input Capacitance (CLK pins) 2.0 3.0 0.25 pF C I/O DQ, DQS, DM Capacitance 4.0 5.0 0.5 pF C NC1 NC1 Pin Capacitance - 1.5 - pF C NC2NC2 Pin Capacitance4.05.0-pFNotes: These parameters are periodically sampled and not 100% tested.The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance. The NC2 pins have Power and Ground clamp.10. LEAKAGE AND OUTPUT BUFFER CHARACTERISTICSSYMBOL PARAMETERMIN. MAX. UNITS NOTES I I(L) Input Leakage Current(0V < V IN < V DDQ , All other pins not under test = 0V) -2 2 µA I O(L) Output Leakage Current(Output disabled, 0V < V OUT < V DDQ ) -5 5 µA V OH Output High Voltage(under AC test load condition) V TT +0.76- V V OL Output Low Voltage(under AC test load condition)- V TT -0.76 V I OH (DC)Output Minimum Source DC Current-15.2 - mA 4, 6 I OL (DC) Output Minimum Sink DC Current Full Strength15.2 - mA 4, 6 I OH (DC) Output Minimum Source DC Current -10.4 - mA 5 I OL (DC) Output Minimum Sink DC CurrentHalf Strength10.4-mA5Publication Release Date: March 21, 200211. DC CHARACTERISTICSCKDQSRANDOM READ CURRENT TimingtRCDt RC12. AC CHARACTERISTICS AND OPERATING CONDITION (Notes: 10, 12)Publication Release Date: March 21, 200213. AC TEST CONDITIONSV SWING (MAX)V DD QV SS(8) V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be setequal to V REF and must track variations in the DC level of V REF .(9) These parameters depend on the output loading. Specified values are obtained with the output open.(10) Transition times are measured between V IH min. (AC) and V IL max.(AC). Transition (rise and fall) of input signals have afixed slope.(11) IF the result of nominal calculation with regard to t CK contains more than one decimal place, the result is rounded up tothe nearest decimal place. (i.e., t DQSS = 0.75 × t CK , t CK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)(12) V X is the differential clock cross point voltage where input timing measurement is referenced.(13) V ID is magnitude of the difference between CLK input level and CLK input level.(14) V ISO means {V ICK (CLK)+V ICK (CLK )}/2.(15) Refer to the figure below.CLKV V XXV V XV V (16) t AC and t DQSCK depend on the clock jitter. These timing are measured at stable clock.Publication Release Date: March 21, 200214. OPERATION MODEThe following table shows the operation commands.Simplified Truth TablNotes :1. V = Valid X = Don’t Care L = Low level H = High level2. CKE n signal is input level when commands are issued.CKE n-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. LDM, UDM (W942516BH)5. Power Down Mode can not entry in the burst cycle.Function Truth Table(Note 1)Publication Release Date: March 21, 2002Function Truth Table, continuedFunction Truth Table, continuedNotes :1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.2. Illegal if any bank is not idle.3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on thestate of that bank.4. Illegal if t RCD is not satisfied.5. Illegal if t RAS is not satisfied.6. Must satisfy burst interrupt condition.7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy t WRRemark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid dataPublication Release Date: March 21, 2002Function Truth Table for CKENotes :1. Self refresh can enter only from the all banks idle state.2. Power down can enter only from bank idle or row active state.Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data15. SIMPLIFIED STATE DIAGRAMPublication Release Date: March 21, 200216. FUNCTIONAL DESCRIPTIONPower Up Sequence(1) Apply power and attempt to CKE at a low state (≤0.2V), all other inputs may be undefined1) Apply V DD before or at the same time as V DDQ .2) Apply V DDQ before or at the same time as V TT and V REF . (2) Start Clock and maintain stable condition for 200µS (min). (3) After stable power and clock, apply NOP and take CKE high.(4) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. (5) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.(an additional 200 cycles(min) of clock are required for DLL Lock) (6) Issue precharge command for all banks of the device. (7) Issue two or more Auto Refresh commands. (8) Issue MRS-Initialize device operation.(If device operation mode is set at sequence 5, sequence 8 can be skipped.)Command Function1. Bank Activate Command(RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address)The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as t RAS (max). After this command is issued, Read or Write operation can be executed.2. Bank Precharge Command(RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don ’t care)The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state.3. Precharge All Command(RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don’t care, A10 = "H", A0 to A9, A11, A12 = Don’t care)The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state.4. Write Command(RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address)The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation.5. Write with Auto Precharge Command(RAS="H", CAS= "L", WE= "L", BS0, BS1 = Bank, A10= "H", A0 to A9, A11 = Column Address)The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands.6. Read Command(RAS="H", CAS= "L", WE= "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column Address)The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation.7. Read with Auto Precharge Command(RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column Address)The Read with Auto precharge command automatically performs the Precharge operation after the Read operation.1) READA≥t RAS (min) - (BL/2) x t CKInternal precharge operation begins after BL/2 cycle from Read with Auto Precharge command.2) t RCD(min) ≤ READA < t RAS(min) - (BL/2) x t CKData can be read with shortest latency, but the internal Precharge operation does not begin until after t RAS (min) has completed.This command must not be interrupted by any other command.8. Mode Register Set Command(RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after power-up are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes.Publication Release Date: March 21, 20029. Extended Mode Register Set Command(RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes.10. No-Operation Command(RAS = "H", CAS = "H", WE = "H")The No-Operation command simply performs no operation (same command as Device Deselect).11. Burst Read Stop Command(RAS = "H", CAS = "H", WE = "L")The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation.12. Device Deselect Command(CS ="H")The Device Deselect command disables the command decoder so that the RAS ,CAS ,WE and Address inputs are ignored. This command is similar to the No-Operation command.13. Auto Refresh Command(RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t care)The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 8192 times within 64ms. The next command can be issued after t REF from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state.14. Self Refresh Entry Command(RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = don’t care)The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self Refresh Exit command). During self refresh, DLLl is disable.15. Self Refresh Exit Command(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after t XSNR (t XSRD for Read Command) from the end of this command.16. Data Write Enable /Disable Command(DM = "L/H" or LDM, UDM = "L/H")During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15.Read OperationIssuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after t RCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up.When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated.When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation.Write OperationIssuing the Write command after t RCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up.When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated.When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation.PrechargeThere are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as t RAS (max). Therefore, each bank must be precharged within t RAS(max) from the bank activate command.The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state.Publication Release Date: March 21, 2002Burst TerminationWhen the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high": during t WR to prevent writing the invalided data to the cell array.When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination.Refresh OperationTwo types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times(rows) within 64 mS. The period between the Auto Refresh command and the next command is specified by t RFC .Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8 µS before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.Power Down ModeTwo types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode.When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer).Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode.Mode Register OperationThe mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BS0, BS1 address inputs.The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select atype of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode)The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation.(1) Burst Length field (A2 to A0)This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words.A2 A1 A0 BURST LENGTH0 0 0 Reserved0 0 1 2 words0 1 0 4 words0 1 1 8 words1 x x Reserved(2) Addressing Mode Select (A3)The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words.A3 ADDRESSING MODE0 Sequential0 InterleavePublication Release Date: March 21, 2002• Address Sequence of Sequential ModeA column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following.Addressing Sequence of Sequential Mode• Addressing Sequence of Interleave ModeA Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following.Address Sequence for Interleave Mode(3) CAS Latency field (A6 to A4)This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK.(4) DLL Reset bit (A8)This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.(5) Mode Register /Extended Mode register change bits (BS0, BS1)These bits are used to select MRS/EMRS.BS1 BS0 A12-A00 0 Regular MRS Cycle0 1 Extended MRS Cycle1 x Reserved(6) Extended Mode Register field1) DLL Switch field (A0)This bit is used to select DLL enable or disableA0 DLL0 Enable1 Disable2) Output Driver Size Control field (A1)This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard.A1 OUTPUT DRIVER0 Full Strength1 Half Strength(7) Reserved field• Test mode entry bit (A7)This bit is used to enter Test mode and must be set to "0" for normal operation.• Reserved bits (A9, A10, A11, A12)These bits are reserved for future operations. They must be set to "0" for normal operation.。