ZTX690B中文资料

FPGA可编程逻辑器件芯⽚XC7VX690T-2FFG1927中⽂规格书with exemption 15 where there is lead in the C4 bumps that are used to complete a viable electrical connection between the semiconductor die and the package substrate. The FFV, FBV, and SBV flip-chip packages marked with the Pb-free character are RoHS 6 of 6compliant (without the use of exemption 15). The CPG, CSG, FTG, and FGG non-flip chip packages are RoHS 6 of 6 compliant.All of the 7series devices supported in a particular package are pinout compatible. See Pin Compatibility between Packages, page33. Pins that are available in a device but are not available in a smaller device with a compatible package are listed as No Connects. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards (see the 7Series FPGAs SelectIO Resources User Guide (UG471). Table1-12 provides definitions for all pin types.7series device’s flip-chip assembly materials are manufactured using ultra-low alpha (ULA) materials defined as <0.002cph/cm2 or materials that emit less than 0.002 alpha-particles per square centimeter per hour.Device/Package Combinations and Maximum I/OsTable1-1 shows the maximum number of user I/Os possible in the 7series FPGAs BGApackages.Table 1-1:7Series FPGAs Package SpecificationsPackages(1)DescriptionPackage SpecificationsPackage Type Pitch(mm)Size(mm)Maximum I/Os(2)CPGA196Wire-bondchip-scale BGA0.58x8100FTB196/FTGB196BGA 1.015 x 15100 CP236/CPG236BGA0.510x10106 CPG238BGA0.510x10110CSA225/CSGA225BGA0.813x13100 CS324/CSG324BGA0.815 x 15210 CSGA324BGA0.815 x 15210 CS325/CSG325BGA0.815 x 15150FT256/FTG256Wire-bond fine-pitch BGA 1.017 x 17170FG484/FGG484BGA 1.023 x 23285 FGGA484BGA 1.023 x 23338 FG676/FGG676BGA 1.027 x 27300 FGGA676BGA 1.027 x 27400Kintex-7 device/package combination.Table 1-9:Available I/O Pin/Device/Package Combinations for Kintex-7 FPGAsKintex-7 Devices User I/OPinsKintex-7 FPGA Packages: HR and HP I/O BanksFBG484FBV484FBG676FBV676FBG900FBV900FFG676FFV676FFG900FFV900FFG901FFV901FFG1156FFV1156RF676RF900 HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HRXC7K70T User I/O100185100200––––––––––––––Differential9617696192––––––––––––––XC7K160T User I/O100185150250––150250––––––––––Differential96176144240––144240––––––––––XC7K325T User I/O––150250150350150250150350––––––––Differential––144240144336144240144336––––––––XC7K355T User I/O––––––––––0300––––––Differential––––––––––0288––––––XC7K410T User I/O––150250150350150250150350––––––––Differential––144240144336144240144336––––––––XC7K420T User I/O––––––––––03800400––––Differential––––––––––03660384––––XC7K480T User I/O––––––––––03800400––––Differential––––––––––03660384––––XA7K160T User I/O––––––150250––––––––––Differential––––––144240––––––––––XQ7K325T User I/O––––––––––––––150250150350 Differential––––––––––––––144240144336XQ7K410T User I/O––––––––––––––150250150350 Differential––––––––––––––144240144336I/Os for each Virtex-7 device/package combination. When applicable, it also lists the number of user I/Os in the 3.3V-capable high-range (HR) banks and the number of1.8V-capable high-performance (HP) banks.Table 1-10:Available I/O Pin/Device/Package Combinations for Virtex-7T FPGAsVirtex-7TDevices User I/O PinsVirtex-7T FPGA Packages: HR and HP I/O BanksFFG1157FFG1761FLG1925FHG1761RF1157RF1761 HP HR HP HR HP HR HP HR HP HR HP HRXC7V585T User I/O6000750100––––Differential576072096––––XC7V2000T User I/O––120008500––Differential––115208160––XQ7V585T User I/O––––6000750100 Differential––––576072096The physical XY locations for each IDELAYCTRL start at X0Y0 in the bottom left-most bank. The locations then increment by onestarting with the lowest bank number in each column in the vertical Y direction and by one for each column in the horizontal X direction. IDELAYCTRLs are located in each of the HROWs.This section visually describes the die level bank numbering.Spartan-7 devices on page36 through page39.Artix-7 devices on page40 through page45.Kintex-7 devices on page46 through page52.Virtex-7T devices (XC7V585T and XC7V2000T) on page53 through page55.Virtex-7XT devices (XC7VX330T, XC7VX415T,XC7VX485T, XC7VX550T, XC7VX690T, XC7VX980T, and XC7VX1140T) on page56 through page66.。

7Series FPGAs Data Sheet: OverviewDS180 (v2.6.1) September 8, 2020Product SpecificationKintex-7 FPGA Feature SummaryTable 6:Kintex-7 FPGA Feature Summary by Device Device Logic Cells Configurable Logic Blocks (CLBs)DSP Slices (2)Block RAM Blocks (3)CMTs (4)PCIe (5)GTXs XADC Blocks Total I/O Banks (6)Max User I/O (7)Slices (1)Max Distributed RAM (Kb)18Kb 36Kb Max (Kb)XC7K70T 65,60010,2508382402701354,86061816300XC7K160T 162,24025,3502,18860065032511,70081818400XC7K325T 326,08050,9504,00084089044516,02010116110500XC7K355T 356,16055,6505,0881,4401,43071525,740612416300XC7K410T 406,72063,5505,6631,5401,59079528,62010116110500XC7K420T 416,96065,1505,9381,6801,67083530,060813218400XC7K480T 477,76074,6506,7881,9201,91095534,380813218400Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x 18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTX transceivers.Table 7:Kintex-7 FPGA Device-Package Combinations and Maximum I/OsPackage (1)FBG484 FBG676(2)FFG676(2) FBG900(3)FFG900(3)FFG901FFG1156Size (mm)23 x 2327 x 2727 x 2731 x 3131 x 3131 x 3135 x 35Ball Pitch (mm)1.0 1.0 1.0 1.0 1.0 1.0 1.0DeviceGTX (4)I/O GTX (4)I/O GTX I/O GTX (4)I/O GTX I/O GTX I/O GTX I/O HR (5)HP (6)HR (5)HP (6)HR (5)HP (6)HR (5)HP (6)HR (5)HP (6)HR (5)HP (6)HR (5)HP (6)XC7K70T41851008200100XC7K160T418510082501508250150XC7K325T825015082501501635015016350150XC7K355T243000XC7K410T825015082501501635015016350150XC7K420T283800324000XC7K480T 283800324000Notes:1.All packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FBG676 and FFG676 are footprint compatible.3.Devices in FBG900 and FFG900 are footprint compatible.4.GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. Refer to Kintex-7 FPGAs Data Sheet:DC and AC Switching Characteristics (DS182) for details.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.6.HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.7Series FPGAs Data Sheet: OverviewBlock RAMSome of the key features of the block RAM include:•Dual-port 36Kb block RAM with port widths of up to 72•Programmable FIFO logic•Built-in optional error correction circuitryEvery 7series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data.Synchronous OperationEach memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.Programmable Data WidthEach port can be configured as 32K×1, 16K×2, 8K×4, 4K×9 (or8), 2K×18 (or16), 1K×36 (or32), or 512×72 (or64). The two ports can have different aspect ratios without any constraints.Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any aspect ratio from 16K×1 to 512×36. Everything described previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs.Only in simple dual-port (SDP) mode can data widths of greater than 18bits (18Kb RAM) or 36bits (36Kb RAM) be accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72.Both sides of the dual-port 36Kb RAM can be of variable width.Two adjacent 36Kb block RAMs can be configured as one cascaded 64K×1 dual-port RAM without any additional logic. Error Detection and CorrectionEach 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.FIFO ControllerThe built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width.First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode.DS180 (v2.6.1) September 8, 2020Product Specification。

C HIPTRONICTC690数字式十二脉波三相全控整流触发板（恒压恒流控制）---------------------------------------------------------------------------------------------------------- 深圳市中软创芯电子有限公司版权所有电话Tel：*************传真Fax：*************手机Mob：189****8358技术支持QQ：1092081589邮箱Email：******************网址：版本号：V3.6.1（2016）----------------------------------------------------------------------------------------------------------目录操作前的安全规范及注意事项……………………………………………………………………………………3页一、产品概述………………………………………………………………………………………………………5页二、技术规格………………………………………………………………………………………………………5页三、性能特点………………………………………………………………………………………………………7页四、显示屏面板操作说明即手操器………………………………………………………………………………8页五、控制板端子定义………………………………………………………………………………………………9页六、中文菜单显示及参数操作说明………………………………………………………………………………11页七、输出反馈控制接入说明………………………………………………………………………………………19页八、整流控制过程中的相关原理示意图…………………………………………………………………………21页九、故障显示及故障处理方法……………………………………………………………………………………23页十、常见问题分析及排除…………………………………………………………………………………………24页 十一、主回路及控制回路接线示意图……………………………………………………………………………24页我们产品的元器件：* 电源变压器采用军工级品质变压器，环氧树脂灌封，经过高温老化锤炼的高品质产品；* 主控芯片采用NXP 32位LPC17系列工业级高性能处理器，拥有超强的运算处理能力及可靠的抗干扰能力；* 被动元器件基本为国巨Yageo品牌，耐高温，低漂移，器件工作寿命达10年以上；* 关键被动器件采用村田Murata及英飞凌Infineon品牌，保证控制板高压关键部位不易损坏；* 控制继电器为欧姆龙Omron品牌，动作次数是国产品牌10倍以上；* 接线端子采用町洋DINKLE品牌，内部铜合金制成，不像市场上的控制板是采用铁质端子；* 控制板本安型设计，电源处采用自恢复保险丝来限制电流输出，防止外接线端子意外短路损坏控制板；* 配合我们多年引领行业的核心控制算法及SMD贴片工艺，保证控制板具有可靠稳定的性能。