Efficient Circuit Analysis of ESD Protection Networks
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Efficient Circuit Analysis of ESD Protection Networks
Faculty Investigator Sachin S. Sapatnekar, University of Minnesota
IBM Technical Contact Charles J. Alpert, IBM Austin Research Laboratory Description
The problem of electrostatic discharge (ESD) is increasingly serious as technology progresses, as circuits become more susceptible to ESD failures. Circuit analysis to measure susceptibility to ESD has grown in importance for high performance designs, and will become vital in the future. Inadequate ESD verification can lead to numerous design iterations, which may result in a large cost overhead.
The design of on-chip ESD protection networks requires two criteria to be met: (1) providing a low impedance path between any two pads, and (2) clamping pad voltages to a sufficiently low level to avoid the possibility of gate oxide breakdown. The analysis of an ESD network requires a check to determine whether these criteria are met. However, this can be very difficult since the networks to be analyzed tend to be extremely large, and existing techniques are either computationally expensive, or trade off speed for unacceptably low levels of accuracy.
This work will apply our random walk based approach [1] for solving large systems of linear equations, and adapt it to the problem of analyzing ESD networks. This approach has many attractive features that localize the computation, and seems to point towards a promising approach to this problem. However, considerable research remains to be carried out in working with realistic ESD network models, and considering how our method can be tailored specifically to this problem, and in efficiency enhancements that are specific to the structure of the problem. We also intend to explore methods that can be used to optimize the network to decrease ESD failures.
Objectives and Goals
In the coming year, we intend to explore the following issues:
a) Explore accurate, yet computationally tractable, models for ESD networks, and study the requirements and constraints.
b) Apply our random walk approach to test the reliability of ESD networks.
c) Develop efficiency enhancing methods to reduce the computational cost.
d) Apply the method on benchmark and industrial circuits to demonstrate its efficacy in cooperation with our mentors at the IBM Austin Research Laboratory.
Long term impact to the information/computing industry and IBM
Reliability issues have long been extremely important, and are now rapidly moving towards becoming the next frontier in high-performance chip design. The development of analysis and optimization methods for enhancing ESD protection networks is widely accepted as an industry-wide problem for the next generation of high-performance circuits. Therefore, it is imperative to develop high-quality solutions to this problem. In terms of long term impact, this research stands to greatly benefit IBM, which is a leader in the design of bleeding-edge circuits, and in time, as these problems filter down to the less aggressive designs, the greater semiconductor industry will stand to benefit.
References
[1] H. Qian, S. R. Nassif and S. S. Sapatnekar, "Random Walks in a Supply Network," Proceedings of the ACM/IEEE Design Automation Conference, pp. 93 - 98, 2003 (Best paper award).。
