UDA1309H中文资料

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Iref 17
CURRENT IDAC REFERENCE
47 kΩ
DIGITAL FILTER
Low-power stereo bitstream ADC/DAC
4
DAC
ADC
Vm 5 4 1 2 41 6
UDA1309H
27 28 VDDD VSSD
1.6 kΩ 23 DACR 1 nF 24 VOR
VERSION
UDA1309H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2
1998 Jan 06
2
Philips Semiconductors
Product specification
1998 Jan 06
3
ook, full pagewidth
analog input VIL
1998 Jan 06
analog output VOL 1 nF VDDA(DA) CLKEDGE VSSD(F) VSSA(DA) DADEM TEST0 MODE2 VDDO MODE1 TEST1 VDDD(F) SYSCLK MODE0 VSSO 38 3 1.6 kΩ 30 26 37 44 43 42 33 20 34 25 19 DACL 22 VOL 21 MODE SELECT DAC DIGITAL INTERFACE DIGITAL FILTER DIGITAL INTERFACE Vm 18 DAref 0.22 µF 10 µF
Analog-to-digital converter input voltage (RMS value) note 1 at 0 dB at −60 dB; A-weighted VI = 0 V; A-weighted 0.9 − − tbf − 1.0 −85 −35 95 90 1.1 tbf −30 − − V dB dB dB dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N αcs VO(rms) idle channel signal-to-noise ratio channel separation
UDA1309H
The UDA1309H is a single chip stereo analog-to-digital and digital-to-analog converter employing bitstream conversion techniques. The device is eminently suitable for use in low-power portable digital audio equipment which incorporates recording and playback functions.
Digital-to-analog converter output voltage (RMS value) note 2 at 0 dB at −60 dB; A-weighted at −60 dB; A-weighted; note 3 S/N αcs Notes 1. VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to −1.0 dB in the digital domain]. 2. At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA). 3. 18-bit input data. idle channel signal-to-noise ratio channel separation code 0000H; A-weighted 0.9 − − − − 90 1.0 −90 −38 −44 104 100 1.1 −82 −34 − − − V dB dB dB dB dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio
MBH527
47 µF
analog input VIR
Supply decoupling on pins 19, 25, 28 and 34; 0.22 µF (ceramic), 47 µF (electrolytic). Capacitance at pin 11 should be close to pins 11 and 9.
47 DIAGRAM
330 pF
0.22 µF
Philips Semiconductors
4.7 kΩ
0.22 µF
Vref
10
BAIL 13
BAOL Vref(pos) Vref(neg) 12 11 40 9
VSSA(AD) 7
VDDA(AD) 8
ADC
Low-power stereo bitstream ADC/DAC
UDA1309H
QUICK REFERENCE DATA VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless otherwise specified. SYMBOL Supply VDDA(AD) VDDA(DA) VDDO VDDD VDDD(F) IDDA(AD) IDDA(DA) IDDO IDDD IDDD(F) Tamb VI(rms) ADC analog supply voltage (pin 8) DAC analog supply voltage (pin 25) operational amplifiers supply voltage (pin 19) ADC and DAC digital supply voltage (pin 28) digital filters supply voltage (pin 34) ADC analog supply current (pin 8) DAC analog supply current (pin 25) operational amplifiers supply current (pin 19) ADC and DAC digital supply current (pin 28) digital filters supply current (pin 34) operating ambient temperature 4.5 4.5 4.5 4.5 4.5 − − − − − −20 5.0 5.0 5.0 5.0 5.0 9 4.5 14 0.2 24 − 5.5 5.5 5.5 5.5 5.5 13.5 6.8 21 0.5 36 +75 V V V V V mA mA mA mA mA °C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
FEATURES • Low power • Integrated high-pass filter to cancel DC offset (ADC) • Analog loop-through function • Multiple digital input/output formats possible • 256fs system clock frequency • Several power-down modes • Digital de-emphasis (DAC) • Overload detector to enable automatic recording level adjustment (ADC) • High dynamic range • DAC requires only one capacitor for post-filtering • Small 44-pin quad flat pack with 0.8 mm pitch • 256fs system clock frequency in Analog-to-Digital (AD) and Digital-to-Analog (DA) mode • Choice of three system clock frequencies (192fs, 256fs or 384fs) in DA mode. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION APPLICATION • Portable digital audio equipment.
Product specification
UDA1309H
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
PINNING SYMBOL ADBCK ADWS MODE0 ADENB OVLOAD ADPON VSSA(AD) VDDA(AD) Vref(neg) Vref Vref(pos) BAOL BAIL BAIR BAOR ADref Iref DAref VDDO VSSO VOL DACL DACR VOR VDDA(DA) VSSA(DA) VSSD VDDD DAPON DADEM DABCK DAWS VSSD(F) VDDD(F) DASDA ANLPTR TEST0 TEST1 VSS(I/O) SYSCLK 1998 Jan 06 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ADC input bit clock; 32fs or 64fs ADC word select input at fs ADC/DAC mode select input ADC serial data enable input (active HIGH) ADC output overload flag (active LOW) ADC power-on-mode input (active HIGH) ADC analog ground supply voltage ADC analog supply voltage ADC negative reference voltage input (ground) ADC decoupling capacitor ADC positive reference voltage decoupling capacitor ADC input amplifier output left ADC input amplifier virtual ground left ADC input amplifier virtual ground right ADC input amplifier output right ADC decoupling capacitor ADC/DAC reference current resistor input DAC decoupling capacitor ADC/DAC operational amplifier supply voltage ADC/DAC operational amplifier ground supply voltage DAC output voltage left DAC output current left DAC output current right DAC output voltage right DAC analog supply voltage DAC analog ground supply voltage ADC/DAC digital ground supply voltage ADC/DAC digital supply voltage DAC power-on-mode input (active HIGH) DAC digital de-emphasis input (active HIGH) DAC input bit clock; 32fs, 48fs or 64fs DAC word select input at fs ADC/DAC digital filters ground supply voltage ADC/DAC digital filters supply voltage DAC serial data input ADC/DAC analog loop-through input (active HIGH) ADC/DAC enable test mode 0 input (LOW is normal mode) ADC/DAC enable test mode 1 input (LOW is normal mode) ADC/DAC digital input/output ground supply voltage DESCRIPTION