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基于FPGA的模糊PID控制器设计的开题报告一、选题背景目前，PID（Proportional-Integral-Derivative）控制器被广泛应用于各个领域中的控制问题中，其简单明晰的结构以及易于调整参数的优秀表现为其在实际应用中受到广泛关注，但在某些复杂的系统中，如水、电、气控制系统中，传统PID控制器可能无法满足控制需求。
因此，模糊PID控制器应运而生。
采用模糊控制理论的PID控制器对于复杂系统的控制较传统PID控制器更加适用，能够提供更加优越的性能和更加灵活的适应性。
而FPGA（Field Programmable Gate Array）可以通过编程重新实现逻辑门电路，具有高速、低功耗以及可编程的优势，因此，基于FPGA的模糊PID控制器设计具有重要意义。
二、选题意义本设计旨在探究基于FPGA的模糊PID控制器的实现方法，具体如下：1. 探究模糊控制理论，了解模糊控制器在控制系统中的应用与优点。
2. 研究PID控制器的工作原理以及传统PID控制器的优缺点。
3. 实现模糊PID控制器的控制算法。
4. 设计基于FPGA的模糊PID控制器系统，并在实验中验证其性能和适用性。
通过此项研究，可以向实现更加高效、快速和灵活的控制系统迈进，同时在控制系统的设计与应用中提供理论支持和实践指导。
三、研究内容和步骤本项目的主要研究内容和步骤如下：1. 搜集相关的模糊控制理论与PID控制器的相关文献，掌握模糊控制原理和PID控制理论的基础知识。
2. 分析常见控制场景，比如电机控制系统场景，根据需要对PID控制器进行改进。
3. 设计基于FPGA的模糊PID控制器，并编写控制算法，完成整个控制器的逻辑设计。
4. 模拟和验证该模糊PID控制器算法的可行性和准确性。
5. 将设计的基于FPGA的模糊PID控制器应用到实际的控制系统场景中，进行性能测试。
四、预期成果本研究的预期成果包括：1. 实现了基于FPGA的模糊PID控制器，并完成控制算法的逻辑设计。
FPGA的模糊控制交通灯控制方案设计彭汪昆;吴修权;白天蕊【期刊名称】《单片机与嵌入式系统应用》【年(卷),期】2011(11)11【摘要】The current split of intersection traffic control signal lights is fixed, so a fuzzy control scheme is proposed. The split is controlled in real-time according to the traffic flow of current phase and the traffic flow difference between current phase and next phase, so as to reduce waiting vehicles at the intersection. The split is implemented based on FPGA. The scheme is emulated using E-Elements ISE Development Kit and software design tool ISE10.1.%针对目前交叉路口交通控制信号灯的绿信比固定不变的问题，提出一种模糊控制的方案。
根据当前相位的车流量和当前相位与下一相位车流量之差，实时控制相位绿信比，缩减车辆在交叉路口的排队长度。
绿信比可在FPGA上模拟实现，采用E—Elements ISE Development Kit开发套件，使用ISE10．1软件设计工具，对上述控制方案进行仿真。
【总页数】3页(P49-51)【作者】彭汪昆;吴修权;白天蕊【作者单位】西南交通大学信息科学与技术学院,成都610031;西南交通大学信息科学与技术学院,成都610031;西南交通大学信息科学与技术学院,成都610031【正文语种】中文【中图分类】TP319【相关文献】1.在FPGA中实现交通灯控制系统的设计 [J], 赵博玉;沈小林2.基于FPGA的交通灯控制器的设计与实现 [J], 金春花3.基于模糊控制的十字路口交通灯控制系统 [J], 田海;薛艳春;赵宇明;郭昌;杨海涛4.基于FPGA的步行街自助式交通灯控制器的设计 [J], 林倩;胡耀武;胡丽冰;陈梁5.基于FPGA的智能交通灯控制系统设计 [J], 赵磊因版权原因，仅展示原文概要，查看原文内容请购买。
I.J.Modern Education and Computer Science, 2012, 7, 24-30Published Online July 2012 in MECS (/)DOI: 10.5815/ijmecs.2012.07.04FPGA Based Pipelined Parallel Architecture forFuzzy Logic ControllerVinod KapseResearch Scholar, Dept. of Electronics & Communication Engg. Jabalpur Engineering College, Jabalpur, IndiaEmail: kapse.vinod@Bhavana JhariaAssociate Professor, Dept. of Electronics & Communication Engg. Jabalpur Engineering College, Jabalpur, IndiaEmail: dr.bhavana.jharia@S. S. ThakurProfessor, Dept. of Mathematics, Jabalpur Engineering College, Jabalpur, IndiaEmail: samajh_singh@Abstract— This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The controller is capable of processing fuzzified input.The proposed controller is designed for 2-input 1-output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.Index Terms—VLSI, FPGA, Pipelined, Inference Processor, Matching Degree.I.I NTRODUCTIONFuzzy inference techniques [1] are becoming an attractive approach to solve control and decision-making problems. This is mainly due to its inherent ability to manage the intuitive and ambiguous behavioral rules given by a human operator to describe a complex system. The application of fuzzy technologies to real-time control problems implies that hardware realizations be adapted to the fuzzy paradigm. Many microelectronics implementations of fuzzy controllers have been proposed recently [2-7]. However, if fuzzy controllers are to be massively adopted in consumer products, they must fulfill some additional characteristics. First, they must be flexible, that is, suitable for adapting their functionality to different applications. This implies the capability to program the knowledge base and select different inference mechanisms. On the other hand, considering fuzzy controllers as integrated circuits, they must be efficient in terms of operational speed.Fuzzy Logic (FL) control system implemented and tested successfully on simple, small, embedded micro-controllers to large, networked, multi-channel PC or workstation-based data acquisition and control systems, but they are not precise to achieve more accurate control such type of controller should be implemented on FPGA which is faster and cost effective.The various fuzzy inference systems are realized by different researcher for different applications. The original digital realization of fuzzy inference processor was performed by Toga and Watanabe [2]. H. Peyravi et al. [6] have proposed reconfigurable inference engine for the analog fuzzy logic controller, based on Mamdani inference technique. J.M. Jou et al. [7], R. d 'Amore [8] and N. E. Evmorfopoulong et al. [9] have proposed different architecture for the fuzzy inference processor. Many variations [1-14] have been proposed to improve the inferencing performance. The speed bottleneck of these fuzzy inference processors lies in the calculation of the matching degree. In order to obtain the matching degree between two membership functions, these fuzzy inference processors need to traverse all the elements in the universal disclosure set. As a result, calculating the matching degree requires very high latency, which limits the overall circuit performance.Some digital hardware fuzzy inference processors [7-8] restrict their inputs to crisp values; in other words, they do not tackle fuzzified inputs. Since calculation of the matching degree requires a crisp value and a membership function, these fuzzy inference processors need not traverse all the elements in the universal disclosure set to obtain the same. The main drawback of these fuzzy inference processors [7-8] is that they do not cover the ignorance of the input measure.Figure 1. Block diagram of the Max-Min CalculatorAsica, Catania and Russo [12] assumed that each membership function is composed of nine segments. Based on this assumption, they used a binary search mechanism to obtain the matching degree between two membership functions. The main drawback of their fuzzy inference processor [13] is that they applied a detection process to extract active rules from the knowledge base. As a result, the inference speed of their fuzzy inference processor depends on the number of active rules. Therefore, their fuzzy inference processor is only suitable for applications that have few active rules.In this paper, it is assumed that each membership function is in trapezoid-shape. The matching degree between two trapezoid-shaped membership functions can be obtained by providing fuzzy input to the controller. Based on this analysis, a pipelined parallel FPGA based hardware is proposed to take advantage of basic idea. The rest of the paper is organized as follows. Section II present the motivation for fast calculation of the matching degree. The architecture of our proposed fuzzy inference processor is described in section III. Comparisons with other hardware architectures are presented in section IV. Finally, some concluding remarks are presented in section V.II.M IN-MAX UNITThe block diagram of the max min calculation is shown in fig.1. This block is used to calculate the degree of membership function. For this design, assuming that the membership grades are discretized into 16 levels which is represented by l=4 bits and it has 64 elements at universal disclosure i.e. e=6 bits. Thus the degree of membership ranges from 0 to 1 is represented as 0000 to 1111, respectively.The max-min block is used to calculate the matching degree of the fuzzy input and antecedent membership functions as shown in fig. 1. Assume that the trapezoidal antecedent membership function is (a1, a2, a3, and a4) and the trapezoidal fuzzified input is (x1, x2, x3, and x4). The following four mutually exclusive conditions are used to calculate the degree of matching between the antecedents and fuzzified input membership functions. The conditions are as follows: 1. If a3 < x2 and x1 < a4: MD is the grade value of the cross-over point ( Fig. 2).2. If x3 < a2 and a1 < x4: MD is the grade value of the cross-over point (Fig. 3).3. If a1=x1, a2=x2, a3=x3, a4=x4: MD = …1‟ (Fig. 4).4. If a4 ≤x1 or x4 ≤a1: MD = …0‟ (Fig. 5).Figure 2. Cross Over PointFigure 3. Cross Over PointFigure 4. Complete MatchingFigure 5. No MatchingThe max-min calculator circuit is consisting of comparator, multiplexers, subtractors, adders, divider and shifter circuit. The comparator circuit is used to differentiate four condition to find matching degree. The inputs to the comparator circuit are a1, a2, a3, a4, x1, x2, x3 and x4, whereas circuit produces two bit output to find out matching degree for four different condition that may occur. According to the result obtained by the comparator circuit, the output of the dedicated max-min calculation hardware is selected. The 00 and 11 output value of comparator circuit indicates that the two membership functions are completely matched or mismatched respectively. The value “01” output of the comparator circuit realizes the equation (1) and “10” realize s equation (2).If (a3 < x2 and x1 < a4) Then()( ) If (x3 < a2 and a1 < x4) Then()( )The proposed fuzzy controller has pipelined parallel architecture with 16 and 8 rules, two inputs and one output variable. The membership degree is divided into 16 levels which is represented by l=4 bits.III.PROPOSED ARCHITECTUREThe fuzzy inference execution can be split into the following three primary steps: fuzzy decoding, inference decision, and defuzzification. The proposed fuzzy decoding is a pipelined architecture is shown in fig. 6. The center of gravity (COG) technique is used for defuzzification process. This can be done using accumulation and division process.Figure 6. The Pipelined ArchitectureA.Fuzzy DecodingThe function of fuzzy decoding unit is to find the weights of rules, including weight0, weight1… weight16, as shown in fig.7. The function of the max-min calculator is split into two phases. Thus, the fuzzy decoding step is also divided into two pipeline stages.Two max-min calculation units operate in parallel to obtain the matching degrees of the two input variables at the same time, as shown in Eqs. (3) and (4).( ( ()())) ( )( ( ()())) ( ) Then, a minimum unit is employed to obtain the weight, as shown in equation (5).() ( ) Note that, at each pipeline stage, a rule will take only two clock cycles. Thus, in order to utilize the fuzzy decoder fully, four rules are processed sequentially during a pipeline stage. In the first pipeline stage, two 4-to-1 multiplexers are used to sequentially pass the rules to max-min calculators; in the second pipeline stage, a 1-to-4 demultiplexer is used to sequentially store the obtained weights. This fuzzy decoder is expandable. To process 16 rules, four fuzzy decoders, operating in parallel are employed. During a pipeline stage, rules R4i (i = 0, 1, 2, 3) are processed in the first and the second cycles, rules R4i+1 (i = 0, 1, 2, 3) are processed in the third and the fourth cycles, rules R4i+2 (i = 0, 1, 2, 3) are processed in the fifth and the sixth cycles, and so on.B.Inference DecisionThe inference decision unit finds degree of membership of the output variable, including O(0), O(1), …, and O(15). Each grade O(m), where m = 0, 1, 2, …, and 15, is determined by means of a maximum of 16 control decisions, which are O0(m), O1(m), …, and O16(m).Simultaneously operating, 16 control decision units are employed. As equation (6) shows, the control decision of a rule O i(m) is obtained by means of the minimum between weight i and C i(m), where m = 0, 1, 2, …, and 16, and i = 0, 1, 2, …, and 16.()(( )) ( )Fig. 8 depicts the control decision unit of a fuzzy rule. The weighti , which is the weight of rule Ri , is calculated in the fuzzy decoding step. Ci is the consequent membership function associated with rule Ri . For computation of Oi (m ), where m = 0, 1, 2, …, and 16, we need to have all 64 elements of . To find all the control decisions within a pipeline stage, four 4-to-1 multiplexers are used. Then, Ci (15), Ci (11), Ci (7), and Ci (3) are sampled on the first cycle, Ci (14), Ci (10), Ci (6), and Ci (2) are sampled on the second cycle, and so on. Consequently, Oi (15), Oi (11), Oi (7), and Oi (3) are obtained on the first cycle, Oi (14), Oi (10), Oi (6), and Oi (2) are obtained on the second cycle, and so on.Four maximum units, i.e., MAX1, MAX2, MAX3, and MAX4, are used to calculate output. The output is calculated using equation (7) is as follows:( ) ( ( ) ( )) ( )Each maximum unit has 64 inputs. In the first cycle, the inputs to MAX1 are ( ) ( ) ( ); the inputs to MAX2 are ( ) ( ) ( ), the inputs to MAX3 are O 0(11), O 1(11), …, and O 15(11); and the inputs to MAX4 are ( ) ( ) ( ). In the second cycle, the inputs to MAX1 are ( ) ( ) ( ) ( ); the inputs to MAX2 are ( ) ( ) ( ) ( );the inputs to MAX3 are ( ) ( ) ( ) ( ); the inputs to MAX4 are ( ) ( ) ( ) ( ); and so on.Figure7. Fuzzy decoder unitFigure 8. Fuzzy control decision unitC.DefuzzificationThe Center of gravity defuzzification method is used to find the final output. It includes two pipeline stages: accumulation and division. For processing the output, four parallel maximum units are used. The numerator N and denominator D is calculated using equation (8) and (9), respectively.∑()∑()∑()∑() ( )∑()∑()∑()∑() ( ) After calculating the value of N and D, the output will be calculated using N/D.PARISONSome high-speed fuzzy inference processors are proposed in [3, 5, 8, 10, 13] and [14] using different approaches such as ASIC, FPGA, DSP and MIPS processor approach.Note that the [10] is a software implementation running on a high-speed DSP, those in [5, 8] and [14] are FPGA implementations, and [13] is an extension of the MIPS processor. Table I shows the comparative study of proposed design with different architectures in terms of resolution , number of inputs and outputs, number of rules and speed in terms mega logic inferences (MFLIPS). Table I compares proposed fuzzy inference processor with above mentioned fuzzy inference processor concludes that it achieves very high performance. It is worth mentioning that [3] and [13] executed their instructions sequentially. Therefore, the works in [3] and [13] are only suitable for applications that have few rules or whose required inference speeds are not high.V.CONCLUSIONIn this paper, a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions has been presented. From the analysis it is clear that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea.The proposed fuzzy inference processor has been implemented on FPGA CycloneII- EP2C70F896C8. The proposed controller is designed and found maximum clock rate as 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules respectively.TABLE I COMPARATIVE STUDY OF DIFFERENT FUZZY CONTROLLERREFERENCES[1]K. Nakamura, N. Sakashita, Y. Nitta, K.Shimomura, and T. Tokuda, “Fuzzy inference andfuzzy inference processor,” IEEE Micro, Vol. 13,1993, pp. 37-48.[2]M. Togai and H. Watanabe, “Expert system on achip: an engine for real-time approximatereasoning ,”IEEE Expert Magazine, Vol. 1, 1986,pp. 55-62.[3]S.H.Huang et al, “High Speed Fuzzy Inferencep rocessor Using Active Rules Identification” JCIS06-Joint conference on Information Sciences, Oct 8-11, 2006, Taiwan.R. J. Dirkman and J.Leonard,68HC11 Microcontroller LaboratoryWorkbook, Prentice Hall, 1996.[4]J.Y. Lai et al, “A High Speed VLSI Fuzzy LogicController with Pipeline Architecture”, Proceedingsof IEEE International Conference on Fuzzy Systems, vol. 3, pp.1054-1057, 2001[5] F. Homburg and R. Palomera-Garcia, “A high-speed scalable and reconfigurable fuzzy controller,”in proceedings of IEEE International Symposium onCircuits and Systems, Vol. 5, 2003, pp. 797-800 [6]H. Peyravi, A. Khoei, and K. Hadidi, “Design of anan alog CMOS fuzzy logic controller chip”, FuzzySets and Systems 132, PP. 254-260, 2002.[7]J. M. Jou and P. Y. Chen, “An adaptive fuzzy logiccontroller: its VLSI architecture and applications,”IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 8, 2000, pp. 52-60.[8]R. D‟Amore, O. Saotome, and K. H. Kienitz, “Atwo-input, one-output bit-scalable architecture forfuzzy processors,” IEEE Design and Test ofComputers, 2001, pp.56-64.[9]N. E. Evmorfopoulos, and J. N. Avaritsiots, “Anadaptive digital fuzzy architecture for application-specific integrated circuits”, Active and PassiveElec. Comp., Vol. 25, pp. 289-306, 2002.[10] E. Frias-Martinez, “Real-time fuzzy processor on aDSP,” in Proceedings of IEEE InternationalConference on Emerging Technologies andFactory Automation, Vol.1, 2001, pp. 403-408. [11]Sajad A. Loan and Asim M. Murshid,“A NovelFuzzy Inference Processor using Trapezoidal-Shaped Membership Function”Proceedings of theIEEE International Conference on Open Systems(ICOS2011), September 25 - 28, 2011, Langkawi,Malaysia.[12]G. Asica, V. Catania, M. Russo, and L. Vita, “Ruledriven VLSI fuzzy processor,” IEEE Micro, Vol.1996, pp. 62-74.[13]V. Salapura, “A fuzzy RISC processor”, IEEETransactions on Fuzzy Systems, Vol.8, 2000, pp.781-790.[14]Shabiul Islam, Mukter Zaman, Bakri Madon, andMasuri Othman (2008). Designing Fuzzy BasedMobile Robot Controller using VHDL. InternationalJournal of Mathematical Models and Methods inApplied Science, Issue 1, Volume 2, ,p-p 138-142.Vinod Kapse born at Nagpur in India. He received the B.E. degree in Industrial Electronics from Amaravati University, Amaravati , India, in 1998, M. Tech. degree in Electronics Engg. from Nagpur University, Nagpur , India in 2007.In 1999, he joined the Srijan Control Drives in R & D department. In 2000, he joined the Sibar Software Services (India) Ltd. as a Design Engineer. In 2002, he joined as a Lecturer in Department of Electronics & Communication in Guru Ramdas Khalsa Institute of Science & Technology, Jabalpur(M.P.) India. He has been member of IEEE. He is currently a Asst. Professor in Gyan Ganga Institute of Technology & Science,Jabalpur(M.P.) India. His research interest includes VLSI Design, Fuzzy logic, Robotics.Bhavana Jharia is presently working as a Associate professor in Department of Electronics & Communication Engineering, Jabalpur Engineering College, Jabalpur, (M. P.), INDIA. Dr. B. Jharia received B.E. degree from Government Engineering College, Jabalpur in 1987 , M.E. from UOR, Roorkee in 1998 and Ph. D. Degrees from I.I.T. Roorkee in 2008. She has published more than 40 research papers in national, International Journals and supervised 30 B.E. 20 M.E. thesis in the area of VLSI design, Communication etc. She is a member of IEEE, IE (I), CSI, VLSI Society of India, senior member of IACSIT and Life Member of ISTE. She has been the coordinator, National Mission on Education through ICT conducted by I.I.T. Bombay. She is a member of editorial board and reviewer of many International Journals and Conferences. The main interest of her current work includes VLSI Design, Communication, Wireless communication and Fuzzy Logic. S. S. Thakur is presently working as a professor in Department of Applied Mathematics and Coordinator Advanced Computing Centre of Fuzzy Technology, Jabalpur Engineering College, Jabalpur, (M. P.), INDIA. Dr. Thakur received M. Sc. and Ph. D. Degrees in mathematics from Dr. Hari Singh Gour University, Sagar in 1977 and 1982 respectively. He has published more than 160 research papers and supervised sixteen Ph. D. students most in the area of Topology and Fuzzy Topology and Fuzzy Data bases. He has been the organizing secretary of an International conference on “Soft Computing and Intelligent Systems” held in Dec. 2007. He is a member of editorial board and serves as referee of many international Journals. The main foci of his current work includes Intuitionist Fuzzy Topology and applications of Intuitionist Fuzzy Sets in Databases.。
基于FPGA的模糊PID控制器实现
锦晓曦;张天兴
【期刊名称】《河南科学》
【年(卷),期】2010(028)008
【摘要】在研究了数字PID的硬件串行与并行实现方法的基础上,对PID控制器的并行实现方法上进行优化,实现在保证快速性的前提下,减少硬件资源.在模糊控制器的FPGA的实现方面,研究了联合MATLAB的间接设计方法,通过MATLAB的模糊工具箱的GUI界面中的修改隶属度函数与模糊控制规则表得到整定参数.最后将模糊控制器与经过改进后设计的PID控制器进行综合设计,实现了模糊自整定PID控制器.
【总页数】6页(P1005-1010)
【作者】锦晓曦;张天兴
【作者单位】上海交通大学,电子信息与电气工程学院自动化系,上海,200240;新乡白鹭化纤集团有限公司,河南,新乡,453011
【正文语种】中文
【中图分类】TP182
【相关文献】
1.基于FPGA的模糊PID控制器的设计 [J], 齐建玲;庄士霞
2.基于FPGA的模糊PID控制器设计 [J], 许忠仁;姜丽;杨冶杰;朱文伟
3.基于FPGA的模糊PID控制器设计 [J], 沈峰;郝国法;贺秋实
4.基于FPGA的倒立摆模糊PID控制器设计实现 [J], 郑浩;汪正祥;张凤登
5.基于FPGA的BLDCM模糊PID控制器设计 [J], 卿金晖;胡黄水;王宏志
因版权原因，仅展示原文概要，查看原文内容请购买。
基于FPGA的网络通讯流量模糊控制器的实现
谭会生
【期刊名称】《测试技术学报》
【年(卷),期】2011(025)005
【摘要】提出了一种基于FPGA的网络通讯流量模糊控制器的实现方法.根据一个基于缓冲管理模式和模糊逻辑的网络通讯流量模糊控制器模型,提出了系统总体实现结构和模糊化、模糊推理和去模糊化模块的实现方法,给出了Verilog HDL程序实现结果,包括功能仿真结果、逻辑资源消耗和系统最高时钟频率.为了提高系统的处理速度,系统结构设计中采用了流水线技术和并行技术,并采用了专门设计的乘法器和除法器.实验结果验证了本控制器结构设计的有效性和程序设计的正确性,系统的最高时钟频率达273.22 MHz.本系统可以应用于ATM和IP网络的流量控制,修改后也可应用于智能交通控制.
【总页数】6页(P421-426)
【作者】谭会生
【作者单位】湖南工业大学电气与信息工程学院,湖南株洲412008
【正文语种】中文
【中图分类】TP311
【相关文献】
1.基于FPGA的高速模糊控制器设计与实现 [J], 张超;支晓东;司兵见;唐旭光
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5.参数自调整模糊控制器研究及基于FPGA实现设计 [J], 路永坤
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基于FPGA的高速模糊控制器设计与实现张超;支晓东;司兵见;唐旭光【摘要】In order to improve the response speed of the fuzzy controller,this paper presents the design of a high-speed fuzzy controller based on FPGA.The program uses five pipeline structure.The first stage calculate the difference between the expected value and the actual value.The second stage get accurate value of e and ec,then the third stage get it's fuzzy values E and EC.The fourth stage look up the value of the third stage from a look-up table and get the fuzzy output U.Finally,the fifth stage get the accurate output u.This program runs on Vertex-II FPGA frequencies up to 100 M,suitable for sensitive response speed control domin.This paper describes the design and simulation of the fuzzy controller with matlab.Then show circuit simulation to verify the correctness of its functions and finally achieve the desired results,having a high market value.%为了提高模糊控制器的响应速度,提出了一种基于FPGA的高速模糊控制器设计方案.该方案采用了5级流水线结构:第一级计算期望值与实际值的差值,第二级得到精确的差值e与ec,第三级对其模糊化得到模糊值E与EC,第四级对前一级输出查表得到模糊输出U,第五级解模糊得到精确输出u.该方案在Vertex-II FPGA上运行时钟频率达到100 M,适用于对响应速度敏感的控制领域.通过对该模糊控制器的matlab以及电路的仿真,验证了其功能的正确性,达到预期的设计效果,具有较高的应用价值.【期刊名称】《电子设计工程》【年(卷),期】2017(025)011【总页数】4页(P122-125)【关键词】模糊控制;simulink仿真;FPGA;流水线结构【作者】张超;支晓东;司兵见;唐旭光【作者单位】哈尔滨理工大学应用科学学院,黑龙江哈尔滨150080;哈尔滨理工大学应用科学学院,黑龙江哈尔滨150080;哈尔滨理工大学应用科学学院,黑龙江哈尔滨150080;哈尔滨理工大学应用科学学院,黑龙江哈尔滨150080【正文语种】中文【中图分类】TN79+1对于复杂度很高的控制系统来说，很难对其建立精确的数学模型，这给控制系统的设计带来巨大的挑战，模糊控制理论的提出为解决这类问题提供了新的思路[1]。
现场可编程门阵列FPGA是近年来发展迅速的大规模可编程逻辑器件，它具有设计周期短，片内资源丰富，可无限次加载和现场可编程等特点。
在FPGA上实现模糊控制器是一种介于专用集成电路(ASIC )和通用处理器之间的方案，具有电子产品的高速度、高可靠性、小型化、集成化、低功耗、保密性能好、具有自主知识产权、产品上市快等优势。
模糊控制器不需要控制对象的精确数学模型，是一种基于规则的控制，依据操作人员的控制经验和专家的知识，通过查表得到控制量。
因此，模糊控制器具有响应快，超调量小，鲁棒性强等特点。
它能够克服系统中模型参数变化和非线性等不确定因素，在大滞后、非线性系统中得到广泛应用。
随着EDA技术的发展，FPGA在数字逻辑系统中发挥越来越重要的作用，采用硬件描述语言的硬件电路设计方法得到了广泛应用。
本文利用VHDL硬件描述语言在FPGA芯片上设计一种简化的模糊控制器。
一模糊控制器的结构及其FPGA实现流程图1 模糊控制器的组成框图图2 模糊控制器机构图由于一维模糊控制器的动态性能不能令人满意，三维及三维以上的模糊控制器结构复杂，建立模糊控制规则比较困难，因此一般采用双输入单输出的二维模糊控制器。
典型的两输人单输出模糊控制器的结构如图2所示，它由知识库、模糊化、模糊推理和逆模糊化4部分构成。
知识库向模糊化模块提供模糊量的隶属函数形态，使模糊化模块在接收到外部的精确量输人之后，能够将其转换成相对应时模糊量及隶属度。
同时，知识库向模糊推理模块提供控制规则，由模糊推理模块执行推理过程，由输人的模糊量推出输出的模糊量。
知识库也向反模糊化模块提供模糊量的隶属函数形态，反模糊化接口则将输出的模糊量及隶属度转换成与之对应的精确量。
论域和模糊状态应根据问题的实际情况而定，现在假设e，ec和u的模糊子集均为{NB，NM，NS，ZO，PS，PM，PB}，模糊论域均为[-4，-3，-2，-1，0，1，2，3，4]，设e的基本论域为[-2，2]，ec的基本论域为[-1，1]，u的基本论域为[-5，5]。
一种模糊控制器在FPGA上的分析设计
张科;靖固
【期刊名称】《工业控制计算机》
【年(卷),期】2008(21)8
【摘要】提出了一种在新型的硬件平台FPGA上分析和设计一种通用的模糊控制器,首先对模糊控制器的工作原理进行分析.然后使用自顶向下的设计方法对模糊控制器的各个模块进行硬件描述语言VHDL分层设计,最后在FPGA芯片上实现了该模糊控制器.结果表明,该模糊控制器的设计方法是可行的,并且对于不同的控制对象,只需修改模糊控制表,就可应用于各种实际的工业生产控制中.
【总页数】3页(P43-44,46)
【作者】张科;靖固
【作者单位】哈尔滨理工大学计算机科学与技术学院,黑龙江,哈尔滨,150080;哈尔滨理工大学计算机科学与技术学院,黑龙江,哈尔滨,150080
【正文语种】中文
【中图分类】TP3
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