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ADC0809模数转换芯片概述ADC0809是8位逐次逼近型A/D 转换器。
它由一个8路模拟开关、一个地址 锁存译码器、一个A/D 转换器和一个三态输出锁存器组成（见下图）。
多路开关 可选通8个模拟通道，允许8路模拟量分时输入，共用A/D 转换器进行转换。
三 态输出锁存器用于锁存A/D 转换完的数字量，当0E 端为高电平时，才可以从三 态输出锁存器取走转换完的数据。
ADC0809内部结构图ADC0809的工作原理图XX 是ADC0809的引脚图。
引脚功能说明如下：• IN0〜IN7： 8个输入通道的模拟输入端 • DO （2一8）〜D7 （2'1）： 8位数字量输出端 • START ：启动信号，加上正脉冲后，A/D 转换开始进行• ALE ：地址锁存信号。
由低至高电平时，把三位地址信号送入通道号地址锁存器，并经译码器得到地址输出，以选择相应的模拟输入通道。
• EOC：转换结束信号，是芯片的输出信号。
转换开始后，EOC 信号变低: 转换结束时，EOC 返回高电平。
这个信号可以作为A/D 转换的状态信号 来査询，也可以直接用作中断请求信号。
• 0E ：输出允许控制端（开数字星输出三态们）。
• CLK ：时钟信号。
最高允许值为640kHzo地锁与码址存译8路二A/D____态 转输换----------------出器----------------存器▲ ▲IN3 EOCIN1DODiIN4 D2IN5D3D4D6 D7LVREFX*)VREFX-)8模 拟开 关• $EF+和％EF-:A/D 转换器的参考电压。
• Vcc-电源电斥。
由于是CMOS 芯片，允许电斥范鬧宽，可以是+5V 〜+15V 。
ADC0809两种封装形式8位模拟开关地址输入通道的关系见表XXo 模拟开关的作用和8选1的 CD4051作用相同表XX 8位模拟开关功能表ADDC ADDB ADDA 输入通道号 0 0 0 INO 0 0 1 INI 0 1 0 IN2 0 1 1 IN3 1 0 0 IN4 1 0 1 IN5 1 1 0 IN6 111IN7ADC0809芯片的转换速度在最高时钟频率卞为lOOus 左右。
目录一、分布智能火灾报警联动系统简介二、火灾报警探测器及模块（一）JTY-GD-AD8001智能光电感烟探测器（二）JTW-ZD-AD8002智能电子感温探测器（三）AD8003手动报警按钮（四）AD8004信号输入模块（五）AD8005总线控制模块（六）AD8006联动切换模块（七）AD8007总线隔离模块（八）AD8008探测器底座（九）AD8009专用编码器三、AD8000分布智能火灾报警联动系统（一）全新概念的报警联动系统（二）AD8000系统的特点（三）AD8000系统控制器的安装尺寸及主要技术参数（四）AD8000报警联动系统主站（五）AD8000IO(输入输出)子站（六）AD8030多线联动控制盘（七）AD8000DY(电源)子站（八）AD8000系统操作说明四、CRT图型显示系统五、消防广播系统六、消防电话系统七、气体灭火控制系统八、系统设计说明及工程调试大纲九、系统设计实例一、分布智能火灾报警联动系统简介纵观火灾报警探测器的发展历史，火灾报警探测器已由传统的“开关量报警方式”到“模拟量报警方式”过渡到现在的“分布智能报警方式”。
所谓“开关量报警方式”是指火灾报警探测器在其内部电路设计过程中，人为地赋予它一个固定的报警阈值。
当报警因素（如：烟雾浓度、环境温度等）达到一定程度时，探测信号超过了探测器内部电路翻转阈值，探测器进入报警状态并通过通讯线路将报警信号传送到火灾自动报警控制器。
这一类火灾自动报警系统所接收的报警信号中只有“火警”和“正常”两种状态，从而不能反应出一个火灾报警的全部发生过程。
当探测器在探测区域内受到诸如潮湿、粉尘、温度及元器件参数变化等非火灾因素影响时，系统将可能发生误报现象。
“模拟量报警方式”与“开关量报警方式”的根本区别在于：模拟量火灾报警探测器内部电路不存在报警阈值，探测器将烟雾浓度或环境温度等报警因素转换成为具有一定值的数据信号，即“模拟量信号”，这个模拟量信号随着报警因素的变化而变化。
课程设计课程名称计算机控制技术题目名称8位AD及其控制接口学生学院_信息工程学院专业班级_应用电子技术一班学号3111002547学生姓名李剑鹏指导教师黄国宏2014 年 5 月11 日目录一、A/D转换器原理----------------------------------------------------------------------31.1、采样-------------------------------------------------------------------------------31.2、量化-------------------------------------------------------------------------------31.2、量化-------------------------------------------------------------------------------31.3、编码-------------------------------------------------------------------------------31.4、量化编码过程-------------------------------------------------------------------3二、ADC装换器分类：-------------------------------------------------------------------42.1、逐次比较型----------------------------------------------------------------------42.2、双积分ADC原理--------------------------------------------------------------42.3、Σ-Δ型ADC原理-------------------------------------------------------------4三、ADC的主要技术指标：-------------------------------------------------------------43.1、分辨率(Resolution) --------------------------------------------------------------43.2、转换速率(Conversion Rate) ----------------------------------------------------5四、8位ADC转换器：ADC0832-------------------------------------------------------54.1、ADC0832简介：----------------------------------------------------------------54.2、ADC0832特点：----------------------------------------------------------------54.3、ADC0832管脚说明：-----------------------------------------------------------54.4、ADC0832的工作控制原理：--------------------------------------------------54.4.1、ADC0832的时序图：---------------------------------------------------54.4.2、ADC0832时序工作说明：---------------------------------------------54.5、ADC0832硬件接口：-----------------------------------------------------------5五、ADC0832软件驱动程序：-----------------------------------------------------------55.1、ADC0832头文件：------------------------------------------------------------65.2、ADC0832驱动程序：----------------------------------------------------------7六、总结--------------------------------------------------------------------------------------8A/D转换器是把模拟电压或电流转换为与之成正比的数字量。
用户手册ADI-8 DS Mk III真正的工业标准高精度24 Bit / 192 kHz参考级别低延迟转换8通道模拟<> AES / ADAT 接口24 Bit / 192 kHz 数字音频ADAT <> AES 格式转换器24 Bit 接口重要的安全说明 (4)概述 (5)1. 介绍 (6)2. 包装清单 (6)3. 简介及主要特点 (6)4. 首次使用——快速上手 (7)4.1 控制、接口与显示 (7)4.2 快速上手 (8)5. 附件 (9)6. 产品保证 (10)7. 附录 (10)CE / FCC符合性声明 (11)使用和操作 (12)8. 前面板操作 (13)8.1 Select（选择）键 (13)8.2 A/D State（A/D状态）- Meters（电平表） (13)8.3 A/D Output（A/D输出） (13)8.4 Patch Mode（批处理模式） (13)8.5 Clock（时钟） (14)8.6 D/A Input（D/A输入） (15)8.7 D/A State（D/A状态）- Meters（电平表） (15)8.8 D/A Reference（D/A参考） (15)输入和输出 (16)9. 模拟输入/输出 (17)9.1 Line In（线路输入） (17)9.2 Line Out（线路输出） (18)10. 数字输入/输出 (19)10.1 AES/EBU (19)10.2 ADAT光纤 (20)11.字时钟 (21)11.1字时钟输入和输出 (21)11.2 技术描述和使用 (22)11.3 布线和终止 (23)技术参考资料 (24)12. 技术指标 (25)12.1 模拟 (25)12.2 数字输入 (26)12.3 数字输出 (27)12.4 数字 (27)12.5 D-Sub AES/EBU接口针脚 (28)13. 技术背景 (30)13.1 技术 (30)13.2 锁定（Lock）与SyncCheck（同步检查） (31)13.3 延时（Latency）与监听（Monitoring） (32)13.4 DS –双倍速 (33)13.5 QS –四倍速 (33)13.6 AES/EBU - SPDIF (34)13.7 DS/QS模式下的噪声电平 (35)13.8 SteadyClock（稳定时钟） (36)14. 框图 (37)重要的安全说明注意! 不要打开底盘，以防触电。
实验十、8路8位A/D转换器接口设计实验一、实验目的1．了解ADC0809转换器的工作原理2．掌握51单片机与ADC0809转换器的接口电路设计及编程二、实验设备1．A/D转换模块（ADC0809）2．单片机最小系统3．静态数码管显示模块三、实验要求要求用单片机最小系统、A/D转换模块、数码管显示模块组成一个简单的“数字电压表”。
将实验箱上可以手动调节的电位器的1、3脚分别连接＋5V和地，2脚输出的0～5V的模拟信号作为“数字电压表”的输入；通过数码管显示测得的当前电压值，精确到0.1V。
从0～5V之间取20个值进行测量，并与校准过的万用表测量值进行比较。
四、实验原理计算机处理的信息为数字量，而对控制现场进行控制时，被控制对象一般是连续变化的模拟量，模拟量必须经过转换，变为数字量送入计算机才能进行处理，将模拟量转变为数字量的过程称为A/D转换。
1．ADC0809工作原理和结构ADC0809单片CMOS数据采集器件，8位8通道复用，控制逻辑微处理器兼容。
8位A/D 转换器的转换技术为逐次逼近法。
具有一个高输入阻抗的比较器。
一个256R具有模拟开关树的分压电阻阵列，以便逼近输入电压。
器件不需要外部调零或满量程调整。
通过锁存、复用地址解码、TTL三态输出，可以很方便的与微处理器接口。
逻辑如图10-1。
图21-1逻辑图D 01D 2D 3D 4D 5D 6D 7图10－1 内部逻辑图图10－2 ADC0809引脚图◆ 单一5V 操作◆ 5V 参考或者外部提供参考。
◆ 非调整误差±1.2 LSB and ±1 LSB ◆ 输入单极性电压0-5V 。
◆ 低功耗15mW 。
◆ 转换时间100uS 。
DIP28封装管脚图如图10-2所示。
管脚定义如表10-1所示。
表10-1 管脚定义2通过地址ADD C ，ADD B 和ADD A ，选择输入的模拟电压通道，如表10-2。
表10-2操作时序图如图10-3，典型应用如图10-4图10-3 操作时序图图10-4 典型应用电路图五、实验步骤1．电路连接硬件连线如图10-5：图10-5：硬件连线图该电路由51单片机、ADC0809电路及七段数码显示电路三部分组成。
JMJK-8DH8通道高速总线采集模块长沙金码测控科技股份有限公司www 产品使用手册版本：V3.0修订日期：2023年4月版权声明 本文件所含信息归长沙金码测控科技股份有限公司所有，文件中所有信息、数据、设计以及所含图样均属长沙金码测控科技股份有限公司所有，未经书面许可，不得以任何形式（包括影印或其他方式）翻印或复制，间接或直接透露给外界个人或团体。
本仪器的安装、维护、操作需由专业技术人员进行，长沙金码测控科技股份有限公司对本产品拥有更改的权利。
长沙金码测控科技股份有限公司版权所有一. 简介1.1. 产品特点1.2. 技术参数1.3.产品说明1.4.产品的使用二. 接口定义及接线2.1. 接线说明2.2. 接口定义2.3. 总线传感器线缆连接说明三. 其它说明3.1.LED灯指示作用四. 维护保养五. 故障说明1112233334444目录 欢迎使用长沙金码测控科技股份有限公司的产品！您拥有金码传感器及其检测设备的同时，就标志着您掌握了最先进的工程检测手段和享有本公司的优质服务，使用本产品之前请详细阅读本说明书或来电垂询，谢谢！ JMJK-8DH型8通道高速总线采集模块，是一种多通道采集总线型传感器或总线型设备的自动化采集模块，完成总线型设备的的自动化测量。
配接的主要设备有位移计、测缝计、量水堰仪、静力水准仪、引张线仪、索力拾振模块等总线型传感器及设备。
本模块据内置微控制系统，具有自动识别本公司传感器的类型、根据不同类型对传感器传回的数据进行处理、存储传感器零点、读取传感器编号等功能。
同时，模块内置时钟，可用上位机软件对模块进行自动测量设置。
一、简介1：高速采集，采集速率可达到1Hz2：防静电防尘设计，适用于各种施工环境。
3：8通道可同步采集，最多可以连接24个总线型传感器。
4：便捷的接入本公司的自动化测试系统，轻松实现远程无人值守自动测量。
5：可远程升级产品固件，方便后期维护。
项目输入接口采集速率采集模式供电电压输出接口工作温度波特率工作湿度机械尺寸JMJK-8DH RS232数字信号输入＜=1Hz 连续采集与单次采集DC9V--DC18V（建议DC12V）RS485数字信号输出-20℃～70℃RS232通讯：115200 RS485通讯：96000%～95%RH 276mm×120mmm×45mm1.1.产品特点1.2.技术参数模块使用的主流程为：注意事项：1、进入配置模式后，方可对设备进行相应的参数配置，两次操作时间间隔不能超过300s，否则自动退出配置模式。
计数式8位A/D转换器的设计与制作1、设计目的：1.1 培养理论联系实际的正确设计思想，训练综合运用已经学过的理论和生产实际知识去分析和解决工程实际问题的能力。
1.2 学习较复杂的电子系统设计的一般方法，提高基于模拟、数字电路等知识解决电子信息方面常见实际问题的能力，由学生自行设计、自行制作和自行调试。
1.3 进行基本技能训练，如基本仪器仪表的使用，常用元器件的识别、测量、熟练运用的能力，掌握设计资料、手册、标准和规范以及使用仿真软件、实验设备进行调试和数据处理等。
1.4 培养学生的创新能力。
2、设计要求：2.1 电源外接±5V；2.2 输出数字量8位；2.3 误差1LSB；2.4 带转换开始控制；2.5 输入电压直流电压0~4V；2.6 主要单元电路和元器件参数计算、选择；2.7 画出总体电路图；2.8 安装自己设计的电路，按照自己设计的电路，在通用板上焊接。
焊接完毕后，应对照电路图仔细检查，看是否有错接、漏接、虚焊的现象；2.9 调试电路；2.10 电路性能指标测试；2.11 提交格式上符合要求，内容完整的设计报告；3、元器件列表555定时器、100欧电阻*2、C473、74161*2、74LS00、DAC0832、LM324、20K电位器、、3k欧电阻、10 k欧电阻*2、10微法电容、0.01微法电容*2、开关1个、导线若干。
3、设计内容3.1 总体设计3.1.1 总体原理图一计数式8位A/D转换器是由555定时器构成的多谐振荡器，产生的方波信号通过74LS00与非门电路将信号与比较器中输出信号处理后送往由两个74161构成的计数器构成的控制电路,方波出现一次上升沿,计数器由零开始向上计数，再由控制电路将信号发送至DAC0832数模转换器,数摸转换器连续的将计数值转换为电压信号，输出的信号再通过LM324构成的比较器与20K的电位器产生的输入电压进行比较,当输入电压大于数模输出电压时，计数器继续计数，直到两者相等的瞬间才停止计数，保存在计数器内的数即代表输入电压值。
March 20, 2008 ADC08D1000High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D ConverterGeneral DescriptionThe ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and in-terpolating architecture, the fully differential comparator de-sign, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, produc-ing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC.The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus-trial (-40°C ≤ T A≤ +85°C) temperature range.Features■Internal Sample-and-Hold■Single +1.9V ±0.1V Operation■Choice of SDR or DDR output clocking■Interleave Mode for 2x Sampling Rate■Multiple ADC Synchronization Capability■Guaranteed No Missing Codes■Serial Interface for Extended Control■Fine Adjustment of Input Full-Scale Range and Offset■Duty Cycle Corrected Sample ClockKey Specifications■Resolution8 Bits ■Max Conversion Rate 1 GSPS (min)■Bit Error Rate10-18 (typ)■ENOB @ 500 MHz Input7.4 Bits (typ)■DNL±0.15 LSB (typ)■Power Consumption■—Operating 1.6 W (typ)—Power Down Mode 3.5 mW (typ) Applications■Direct RF Down Conversion■Digital Oscilloscopes■Satellite Set-top boxes■Communications Systems■Test InstrumentationBlock Diagram20097453© 2008 National Semiconductor ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D ConverterOrdering InformationIndustrial Temperature Range (-40°C < T A < +85°C)NS PackageADC08D1000CIYB 128-Pin Exposed Pad LQFPADC08D1000DEVDevelopment BoardPin Configuration20097401* Exposed pad on back of package must be soldered to ground plane to ensure rated performance. 2A D C 08D 1000Pin Descriptions and Equivalent CircuitsPin Functions Pin No.SymbolEquivalent CircuitDescription3OutV / SCLKOutput Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See 1.1.6 The LVDS Outputs . When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See 1.2 NORMAL/EXTENDEDCONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface.4OutEdge / DDR /SDATADCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. (See 1.1.5.2 OutEdge Setting ). When this pin is floating or connected to 1/2 the supply voltage, DDR clocking is enabled. When the extended control mode is enabled, this pin functions as the SDATA input. See 1.2 NORMAL/EXTENDED CONTROL for details on the extended control mode. See 1.3 THE SERIAL INTERFACE for description of the serial interface.15DCLK_RST/DCLK_RST-DCLK Reset. A positive pulse on this pin is used to reset and synchronize the DCLK outs of multiple converters. See 1.5MULTIPLE ADC SYNCHRONIZATION for detailed description. 26 PDPower Down Pins. A logic high on the PD pin puts the entire device into the Power Down Mode.30CALCalibration Cycle Initiate. A minimum t CAL_L input clock cycles logic low followed by a minimum of t CAL_H input clock cycles high on this pin initiates the self calibration sequence. See 2.4.2 SelfCalibration for an overview of self-calibration and 2.4.2.2 On-Command Calibration for a description of on-command calibration.29 PDQA logic high on the PDQ pin puts only the "Q" ADC into the Power Down mode.14FSR/ECEFull Scale Range Select and Extended Control Enable. In non-extended control mode, a logic low on this pin sets the full-scale differential input range to a reduced V IN input level . A logic high on this pin sets the full-scale differential input range to a higher V IN input level. See Converter Electrical Characteristics. To enable the extended control mode, whereby the serial interface andcontrol registers are employed, allow this pin to float or connect it to a voltage equal to V A /2. See 1.2 NORMAL/EXTENDED CONTROL for information on the extended control mode.ADC08D1000Pin Functions Pin No.SymbolEquivalent CircuitDescription127CalDly / DES /SCSCalibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See 1.1.1 Self-Calibration ).With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). When this pin is floating or connected to a voltage equal to V A /2, DES (Dual Edge Sampling) mode is selected where the "I" input is sampled at twice the input clock rate and the "Q" input is ignored. See 1.1.5.1 Dual-Edge Sampling .1819CLK+CLK-LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See 1.1.2 Acquiring the Input for adescription of acquiring the input and Section 2.3 for an overview of the clock inputs.1110 2223V IN I+V IN I− V IN Q+V IN Q−Analog signal inputs to the ADC. The differential full-scale input range of this input is programmable using the FSR pin 14 in normal mode and the Input Full-Scale Voltage Adjust register in the extended control mode. Refer to the V IN specification in theConverter Electrical Characteristics for the full-scale input range in the normal mode. Refer to 1.4 REGISTER DESCRIPTION for the full-scale input range in the extended control mode.7V CMOCommon Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at V IN + and V IN − when d.c.coupling is used. This pin should be grounded when a.c. coupling is used at the analog inputs. This pin is capable of sourcing or sinking 100μA. See 2.2 THE ANALOG INPUT . 31 V BGBandgap output voltage capable of 100 μA source/sink.126CalRunCalibration Running indication. This pin is at a logic high when calibration is running. 4A D C 08D 1000Pin Functions Pin No.SymbolEquivalent CircuitDescription32R EXTExternal bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1.3435Tdiode_P Tdiode_NTemperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See 2.6.2 Thermal Management .ADC08D1000Pin Functions Pin No.Symbol Equivalent CircuitDescription83 / 7884 / 7785 / 7686 / 7589 / 7290 / 7191 / 7092 / 6993 / 6894 / 6795 / 6696 / 65100 / 61101 / 60102 / 59103 / 58DI7− / DQ7−DI7+ / DQ7+DI6− / DQ6−DI6+ / DQ6+DI5− / DQ5−DI5+ / DQ5+DI4− / DQ4−DI4+ / DQ4+DI3− / DQ3−DI3+ / DQ3+DI2− / DQ2−DI2+ / DQ2+DI1− / DQ1−DI1+ / DQ1+DI0− / DQ0−DI0+ / DQ0+I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs,these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor.104 / 57105 / 56106 / 55107 / 54111 / 50112 / 49113 / 48114 / 47115 / 46116 / 45117 / 44118 / 43122 / 39123 / 38124 / 37125 / 36DId7− / DQd7−DId7+ / DQd7+DId6− / DQd6−DId6+ / DQd6+DId5− / DQd5−DId5+ / DQd5+DId4− / DQd4−DId4+ / DQd4+DId3− / DQd3−DId3+ / DQd3+DId2− / DQd2−DId2+ / DQd2+DId1− / DQd1−DId1+ / DQd1+DId0− / DQd0−DId0+ / DQd0+I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100Ω differential resistor.7980OR+OR-Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±V IN /2 as programmed by the FSR pin in non-extended control mode or the Input Full-Scale Voltage Adjust register setting in the extended control mode).8281DCLK+DCLK-Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. This signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. The DCLK outputs are not active during a calibration cycle, therefore this is not recommended as a system clock.2, 5, 8, 13,16, 17, 20,25, 28, 33,128V AAnalog power supply pins. Bypass these pins to ground.40, 51 ,62,73, 88, 99,110, 121V DROutput Driver power supply pins. Bypass these pins to DR GND.1, 6, 9, 12,21, 24, 27,41GNDGround return for V A . 6A D C 08D 1000ADC08D1000 Pin FunctionsPin No.Symbol Equivalent Circuit Description42, 53, 64,DR GND Ground return for V DR.74, 87, 97,108, 11952, 63, 98,NC No Connection. Make no connection to these pins.109, 120Absolute Maximum Ratings(Notes 1, 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V A , V DR ) 2.2VSupply Difference V DR - V A0V to 100 mVVoltage on Any Input Pin −0.15V to (V A +0.15V)Ground Difference |GND - DR GND|0V to 100 mVInput Current at Any Pin (Note 3)±25 mA Package Input Current (Note 3)±50 mAPower Dissipation at T A ≤ 85°C 2.0 W ESD Susceptibility (Note 4) Human Body Model Machine Model 2500V 250VSoldering Temperature, Infrared, 10 seconds, (Note 5), (Applies to standard plated package only)235°CStorage Temperature−65°C to +150°COperating Ratings(Notes 1, 2)Ambient Temperature Range−40°C ≤ T A ≤ +85°CSupply Voltage (V A )+1.8V to +2.0V Driver Supply Voltage (V DR )+1.8V to V A Analog Input Common Mode Voltage V CMO ±50mV V IN +, V IN - Voltage Range (Maintaining Common Mode)200mV to V AGround Difference (|GND - DR GND|)0V CLK Pins Voltage Range 0V to V ADifferential CLK Amplitude0.4V P-P to 2.0V P-PPackage Thermal ResistancePackage θJAθJC(Top ofPackage)θJ-PAD(Thermal Pad)128-Lead Exposed PadLQFP25°C / W 10°C / W 2.8°C / WSoldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications.Refer to /packaging.Converter Electrical CharacteristicsThe following specifications apply after calibration for V A = V DR = +1.9V DC , OutV = 1.9V, V IN FSR (a.c. coupled) = differential 870mV P-P , C L = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f CLK = 1 GHz at 0.5V P-P with 50% duty cycle, V BG = Floating,Non-Extended Control Mode, SDR Mode, R EXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for T A = T MIN to T MAX . All other limits T A = 25°C, unless otherwise noted. (Notes 6, 7)SymbolParameterConditionsTypical (Note 8)Limits (Note 8)Units (Limits)STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity (Best fit)DC Coupled, 1MHz Sine Wave Over ranged±0.3±0.9LSB (max)DNL Differential Non-Linearity DC Coupled, 1MHz Sine Wave Over ranged ±0.15±0.6LSB (max)Resolution with No Missing Codes 8Bits V OFF Offset Error-0.45−1.50.5LSB (min)LSB (max)V OFF _ADJ Input Offset Adjustment Range Extended Control Mode±45 mV PFSE Positive Full-Scale Error (Note 9)−0.6±25mV (max)NFSE Negative Full-Scale Error (Note 9)−1.31±25mV (max)FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20±15%FS NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICSFPBW Full Power Bandwidth Normal Mode (non DES) 1.7 GHz B.E.R.Bit Error Rate10-18 Error/SampleGain Flatnessd.c. to 500 MHz ±0.5 dBFS d.c. to 1 GHz±1.0 dBFS ENOB Effective Number of Bitsf IN = 100 MHz, V IN = FSR − 0.5 dB 7.5 Bits f IN = 248 MHz, V IN = FSR − 0.5 dB 7.47.0Bits (min)f IN = 498 MHz, V IN = FSR − 0.5 dB 7.47.0Bits (min)SINADSignal-to-Noise Plus Distortion Ratiof IN = 100 MHz, V IN = FSR − 0.5 dB 47 dB f IN = 248 MHz, V IN = FSR − 0.5 dB 46.343.9dB (min)f IN = 498 MHz, V IN = FSR − 0.5 dB46.343.9dB (min) 8A D C 08D 1000Symbol Parameter Conditions Typical(Note 8)Limits(Note 8)Units(Limits)SNR Signal-to-Noise Ratio fIN= 100 MHz, VIN= FSR − 0.5 dB48dBfIN= 248 MHz, VIN= FSR − 0.5 dB47.144.0dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB47.144.0dB (min)THD Total Harmonic Distortion fIN= 100 MHz, VIN= FSR − 0.5 dB-55dBfIN= 248 MHz, VIN= FSR − 0.5 dB-55-47.5dB (max)fIN= 498 MHz, VIN= FSR − 0.5 dB-55-47.5dB (max)2nd Harm Second Harmonic Distortion fIN= 100 MHz, VIN= FSR − 0.5 dB−60dBfIN= 248 MHz, VIN= FSR − 0.5 dB−60dBfIN= 498 MHz, VIN= FSR − 0.5 dB−60dB3rd Harm Third Harmonic Distortion fIN= 100 MHz, VIN= FSR − 0.5 dB−65dBfIN= 248 MHz, VIN= FSR − 0.5 dB−65dBfIN= 498 MHz, VIN= FSR − 0.5 dB−65dBSFDR Spurious-Free dynamic Range fIN= 100 MHz, VIN= FSR − 0.5 dB55dBfIN= 248 MHz, VIN= FSR − 0.5 dB5547.5dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB5547.5dB (min)IMD Intermodulation Distortion fIN1= 321 MHz, VIN= FSR − 7 dBfIN2= 326 MHz, VIN= FSR − 7 dB-50dBOut of Range Output Code (In addition to OR Output high)(VIN+) − (VIN−) > + Full Scale255(VIN+) − (VIN−) < − Full Scale0INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICSFPBW(DES)Full Power Bandwidth Dual Edge Sampling Mode900MHzENOB Effective Number of Bits fIN= 248 MHz, VIN= FSR − 0.5 dB7.3 6.8Bits (min)fIN= 498 MHz, VIN= FSR − 0.5 dB7.3 6.8Bits (min)SINAD Signal to Noise Plus DistortionRatiofIN= 248 MHz, VIN= FSR − 0.5 dB4642.5dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB4642.5dB (min)SNR Signal to Noise Ratio fIN= 248 MHz, VIN= FSR − 0.5 dB46.443dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB46.443dB (min)THD Total Harmonic Distortion fIN= 248 MHz, VIN= FSR − 0.5 dB-58-49dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB-58-49dB (min)2nd Harm Second Harmonic Distortion fIN= 248 MHz, VIN= FSR − 0.5 dB-64dBfIN= 498 MHz, VIN= FSR − 0.5 dB-64dB3rd Harm Third Harmonic Distortion fIN= 248 MHz, VIN= FSR − 0.5 dB-69dBfIN= 498 MHz, VIN= FSR − 0.5 dB-69dBSFDR Spurious Free Dynamic Range fIN= 248 MHz, VIN= FSR − 0.5 dB5747dB (min)fIN= 498 MHz, VIN= FSR − 0.5 dB5747dB (min)ANALOG INPUT AND REFERENCE CHARACTERISTICSV IN Full Scale Analog DifferentialInput RangeFSR pin 14 Low650570mV P-P (min)730mV P-P (max)FSR pin 14 High870790mV P-P (min)950mV P-P (max)V CMI Analog Input Common ModeVoltageVCMOVCMO− 50VCMO+ 50mV (min)mV (max)C IN Analog Input Capacitance,Normal operation (Notes 10, 11)Differential0.02pFEach input pin to ground 1.6pFAnalog Input Capacitance, DESMode (Notes 10, 11)Differential0.08pFEach input pin to ground 2.2pFADC08D1000Symbol ParameterConditionsTypical (Note 8)Limits (Note 8)Units (Limits)R INDifferential Input Resistance10094Ω (min)106Ω (max)ANALOG OUTPUT CHARACTERISTICS V CMO Common Mode Output Voltage I CMO = ±100 µA 1.260.951.45V (min)V (max)V CMO_LVL V CMO input threshold to set DC Coupling modeV A = 1.8V 0.60 V V A = 2.0V0.66 V TC V CMO Common Mode Output Voltage Temperature Coefficient T A = −40°C to +85°C 118 ppm/°C C LOAD V CMO Maximum V CMO load Capacitance80pF V BG Bandgap Reference Output VoltageI BG = ±100 µA 1.26 1.201.33V (min)V (max)TC V BG Bandgap Reference Voltage Temperature Coefficient T A = −40°C to +85°C,I BG = ±100 µA 28 ppm/°C C LOAD V BGMaximum Bandgap Reference load Capacitance80pFTEMPERATURE DIODE CHARACTERISTICSΔV BETemperature Diode Voltage192 µA vs. 12 µA,T J = 25°C 71.23 mV 192 µA vs. 12 µA,T J = 85°C 85.54mVCHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match1LSB Positive Full-Scale Match Zero offset selected in Control Register 1LSB Negative Full-Scale Match Zero offset selected in Control Register 1LSB Phase Matching (I, Q)F IN = 1.0 GHz< 1 Degree X-TALK Crosstalk from I (Aggressor) to Q (Victim) Channel Aggressor = 867 MHz F.S.Victim = 100 MHz F.S.-71 dB X-TALKCrosstalk from Q (Aggressor) to I (Victim) Channel Aggressor = 867 MHz F.S.Victim = 100 MHz F.S.-71dBCLOCK INPUT CHARACTERISTICSV IDDifferential Clock Input LevelSine Wave Clock0.60.42.0V P-P (min)V P-P (max)Square Wave Clock0.60.42.0V P-P (min)V P-P (max)I I Input CurrentV IN = 0 or V IN = V A ±1 µA C INInput Capacitance (Notes 10, 11)Differential0.02 pF Each input to ground 1.5 pF DIGITAL CONTROL PIN CHARACTERISTICS V IH Logic High Input Voltage (Note 12) 0.85 x V A V (min)V IL Logic Low Input Voltage(Note 12)0.15 x V AV (max)C INInput Capacitance (Notes 11, 13)Each input to ground1.2 pF DIGITAL OUTPUT CHARACTERISTICSV ODLVDS Differential Output VoltageMeasured differentially, OutV = V A , V BG = Floating (Note 15)710400mV P-P (min)920mV P-P (max)Measured differentially, OutV = GND,V BG = Floating (Note 15)510280mV P-P (min)720mV P-P (max)Δ V O DIFFChange in LVDS Output Swing Between Logic Levels±1mV 10A D C 08D 1000Symbol Parameter Conditions Typical(Note 8)Limits(Note 8)Units(Limits)V OS Output Offset Voltage, see Figure1VBG= Floating800mVV OS Output Offset Voltage, see Figure1VBG= VA(Note 15)1200mVΔ V OS Output Offset Voltage ChangeBetween Logic Levels±1mVIOSOutput Short Circuit Current Output+ & Output- connected to 0.8V±4mAZODifferential Output Impedance100OhmsVOHCalRun High level output I OH = -400uA (Note 12) 1.65 1.5VVOLCalRun Low level output I OH = 400uA (Note 12)0.150.3V POWER SUPPLY CHARACTERISTICSI A Analog Supply CurrentPD = PDQ = LowPD = Low, PDQ = HighPD = PDQ = High6604301.8765508mA (max)mA (max)mAI DR Output Driver Supply CurrentPD = PDQ = LowPD = Low, PDQ = HighPD = PDQ = High2001120.012275157mA (max)mA (max)mAP D Power ConsumptionPD = PDQ = LowPD = Low, PDQ = HighPD = PDQ = High1.61.03.51.971.27W (max)W (max)mWPSRR1D.C. Power Supply RejectionRatioChange in Full Scale Error with changein VAfrom 1.8V to 2.0V30dBPSRR2A.C. Power Supply RejectionRatio248 MHz, 50mVP-Priding on VA51dBAC ELECTRICAL CHARACTERISTICSfCLK1Maximum Input Clock Frequency Normal Mode (non DES) or DES Mode 1.3 1.0GHz (min)fCLK2Minimum Input Clock Frequency Normal Mode (non DES)200MHzfCLK2Minimum Input Clock Frequency DES Mode500MHzInput Clock Duty Cycle 200 MHz ≤ Input clock frequency ≤ 1GHz (Normal Mode) (Note 12)502080% (min)% (max)Input Clock Duty Cycle 500MHz ≤ Input clock frequency ≤ 1GHz (DES Mode) (Note 12)502080% (min)% (max)tCLInput Clock Low Time(Note 11)500200ps (min)tCHInput Clock High Time(Note 11)500200ps (min)DCLK Duty Cycle(Note 11)504555% (min)% (max)tRSReset Setup Time(Note 11)150pstRHReset Hold Time(Note 11)250pst SD Synchronizing Edge to DCLKOutput DelaytOD+ tOSKt RPW Reset Pulse Width(Note 11)4Clock Cycles(min)t LHT Differential Low to High TransitionTime10% to 90%, CL= 2.5 pF250pst HLT Differential High to Low TransitionTime10% to 90%, CL= 2.5 pF250pst OSK DCLK to Data Output Skew50% of DCLK transition to 50% of Datatransition, SDR Modeand DDR Mode, 0° DCLK (Note 11)±50ps (max)tSUData to DCLK Set-Up Time DDR Mode, 90° DCLK (Note 11)750nst H DCLK to Data Hold Time DDR Mode, 90° DCLK (Note 11)890nsADC08D1000Symbol ParameterConditionsTypical (Note 8)Limits (Note 8)Units (Limits)t AD Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of Data 1.3 ns t AJ Aperture Jitter0.4 ps rms t ODInput Clock to Data Output Delay (in addition to Pipeline Delay)50% of Input Clock transition to 50% of Data transition3.1 nsPipeline Delay (Latency)(Notes 11, 14)DI Outputs 13Input Clock Cycles DId Outputs14DQ Outputs Normal Mode 13DES Mode 13.5DQd OutputsNormal Mode 14DES Mode14.5 Over Range Recovery Time Differential V IN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cyclet WU PD low to Rated Accuracy Conversion (Wake-Up Time) 500 ns DCS(Note 11)1 μs f SCLK Serial Clock Frequency (Note 11)100MHz t SSU Data to Serial Clock Setup Time (Note 11)2.5ns (min)t SH Data to Serial Clock Hold Time (Note 11)1ns (min) Serial Clock Low Time 4ns (min) Serial Clock High Time 4ns (min)t CAL Calibration Cycle Time1.4 x 105Clock Cycles t CAL_L CAL Pin Low Time See Figure 9 (Note 11) 80Clock Cycles(min)t CAL_HCAL Pin High TimeSee Figure 9 (Note 11)80Clock Cycles(min)t CalDlyCalibration delay determined by pin 127CalDly = LowSee 1.1.2 Acquiring the Input , Figure 9,(Note 11)225Clock Cycles(min)CalDly = HighSee 1.1.1 Self-Calibration , Figure 9,(Note 11)231Clock Cycles(max)Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note 2:All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.Note 3:When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V A ), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins.Note 4:Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO Ohms.Note 5:See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.Note 6:The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.20097404Note 7:To guarantee accuracy, it is required that V A and V DR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,achieving rated performance requires that the backside exposed pad be well grounded.A D C 08D 1000Note 8:Typical figures are at T A = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).Note 9:Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.Note 10:The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.Note 11:This parameter is guaranteed by design and is not tested in production.Note 12:This parameter is guaranteed by design and/or characterization and is not tested in production.Note 13:The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances.Note 14:Each of the two converters of the ADC08D1000 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the first bus (Dd0 through Dd7).Note 15:Tying V BG to the supply rail will increase the output offset voltage (V OS ) by 400mv (typical), as shown in the V OS specification above. Tying V BG to the supply rail will also affect the differential LVDS output voltage (V OD ), causing it to increase by 40mV (typical).ADC08D1000Specification DefinitionsAPERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig-nal and goes into the “hold” mode the aperture delay time (t AD ) after the input clock goes low.APERTURE JITTER (t AJ ) is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise.Bit Error Rate (B.E.R.) is the probability of error and is de-fined as the probable number of errors per unit of time divided by the number of bits seen in that amount of time. A B.E.R. of 10-18 corresponds to a statistical error in one bit about every four (4) years.CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one clock pe-riod.DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB.Measured at sample rate = 500 MSPS with a 1MHz input sinewave.EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to a per-fect ADC of this (ENOB) number of bits.FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and Full-Scale Errors:Positive Gain Error = Offset Error − Positive Full-Scale ErrorNegative Gain Error = −(Offset Error − Negative Full-Scale Error)Gain Error = Negative Full-Scale Error − Positive Full-Scale Error = Positive Gain Error + Negative Gain ErrorINTEGRAL NON-LINEARITY (INL)is a measure of worst case deviation of the ADC transfer function from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line is measured from the center of that code value step. The best fit method is used.INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS.LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-est value or weight of all bits. This value isV FS / 2nwhere V FS is the differential full-scale amplitude V IN as set by the FSR input and "n" is the ADC resolution in bits, which is 8 for the ADC08D1000.LVDS DIFFERENTIAL OUTPUT VOLTAGE (V OD ) is the ab-solute value of the difference between the V D + & V D - outputs;each measured with respect to Ground.20097446FIGURE 1.LVDS OUTPUT OFFSET VOLTAGE (V OS ) is the midpoint between the D+ and D- pins output voltage; i.e., [(V D +) +( V D -)]/2.MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes can-not be reached with any input value.MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the last code transition is from the ideal 1/2 LSB above a differential - V IN /2. For the ADC08D1000 the reference volt-age is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.OFFSET ERROR (V OFF ) is a measure of how far the mid-scale point is from the ideal zero voltage differential input.Offset Error = Actual Input causing average of 8k samples to result in an average code of 127.5.OUTPUT DELAY (t OD ) is the time delay (in addition to Pipeline Delay) after the falling edge of DCLK before the data update is present at the output pins.OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V to 0V for the converter to recover and make a conversion with its rated ac-curacy.PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. New data is available at every clock cycle, but the data lags the conversion by the Pipeline Delay plus the t OD .POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential + V IN /2. For the ADC08D1000 the refer-ence voltage is assumed to be ideal, so this error is a combi-nation of full-scale error and reference voltage error.POWER SUPPLY REJECTION RATIO (PSRR) can be one of two specifications. PSRR1 (DC PSRR) is the ratio of the change in full-scale error that results from a power supply voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a measure of how well an a.c. signal riding upon the power supply is rejected from the output and is measured with a 248MHz, 50 mV P-P signal riding upon the power supply. It is the ratio of the output amplitude of that signal at the output to its amplitude on the power supply pin. PSRR is expressed in dB.A D C 08D 1000。
8位双极性D-A转换器-可产生正弦波等波形电路的功能8位双极性DAC的功能是用数字来产生波形。
它形成的波形频率可达1MHZ左右。
本电路除可用作普通中速DA转换外，还可用作数字合成电路的振荡输出电路。
DAC08本身只能输出电流，为了进行电流电压转换，加了调整OP 放大器。
电路工作原理IC1是8位的数据锁存电路。
在同一时刻把8位数据送人DAC08可减少因时间差而引起的误差。
由于电流输出端的稳定时间很短，为85NS，对后级电压转换电路转换速度要求较高，所以后级用了高速OP放大器。
电阻R2用来确定基准电流，通常满量程时为2MA，但本电路取1MA。
数字数据为00H时，+IO=0MA，为FFE时+IO=0.9961MA，IO端输入负极性的电流零电平输出时基本上是数字数据的中心值。
数字数据为8FM时，+IO=0.5MA，IO=0.4961MA，+IO与IO之间有3.9UA的偏差，换算成电压则为19.53MV。
用调节置偏的VR1使电路置信。
为了防止数据改变时过渡特性产生过冲，电路中加了电容C4、C5容量为5~10PF。
十六进制数据大于8FH时，输出电压为正，小于8FH时为负，输出电压的倒相由数字数据完成，也可通过切换DAV08的4、2引线进行模拟倒相。
元件的选择输出电压的精度和稳定度取决于基准电压VRBF和电阻R2~R4，为了改变或VEBF，可把R2的一部分改为可变电阻。
由于分辨率是8位，+1LSB的电压为正负39MV，OP放大器的置信漂移不会产生影响，但选用时要注意其交流特性。
调整本电路是为产生波形而设计的，所以只靠静态调整还不行。
为了把数字数据调整输入IC1中，应把重点放在最终输出的波形上。
为了对各部件进行单体调整，应配备存有波形数据的PROM、地址计数器等，接在时钟计数和锁存器上进行调试。
如果电路组装不好，输出波形就会叠加须状脉冲，在一定程度上可用电容C4和C5除去。
置仿调整（VR1）可通过输入数据7FH或8FH来进行。
快捷式8位高速A-D转换器
电路的功能
高速8位A-D转换器用来处理视频宽带信号或用于高速电路中。
UPD6950C是由C-MOS电路组成的快速ADC，转换速率达15MSFS，模拟信号读入时大约为30NS，并由下一个间时钟脉冲锁存数据。
工作电源为单极
+5V，消耗功率400MW属于快速、低功耗器件。
电路工作原理
IC内部为快捷式，由256个电压比较器、产生基准电压的电阻分压电路、锁存256-8位的编码器或8位数据锁存器组成。
A-D转换原理非常简单，256个比较器接通几个进行转换，其个数可由译码
器译成8位数字数据。
基准电压加在电阻分压电路的两端，其电压范围为2.5V~VDD-1（V），内部电阻为1.5K，所以分压电阻有1.6~2.6MA的电流流过。
如果基准电压为2.56V，1LSB的平均电压为10MV，这从直觉上是很容易理解的。
本电路使用了并联调节器，基准电压可调范围约为：2.5~3.75V。
由于TL431C的内部基准约为2.5V，基准电压不能降到2.5V以下，所以可进行A-D转换的输入电压范围为0V~基准电压。
在测量中，有时要求输入
0~5.0~10V的电压，所以在输入端加了衰减器，0~10V时用1/3.9的分压器，即R1=2.9R2。
要使本电路工作，须加外部时钟脉冲，最高时钟频率可达15MHZ。
应注意
数据的时序问题：第一个时钟周期用于A-D转换，第二个时钟周期用来在8位数据寄存器上寄存转换好的数据，再延迟一个时钟周期才能获得转换数据。
这种时序适用于进行连续，如用触发式转换、则要两个时钟脉冲信号。
目录一．设计的目的和意义----------------------------------2 二．设计的内容与要求----------------------------------2 三．系统的硬件要求-------------------------------------2 （1）所用芯片的功能介绍------------------------3（2）设计原理与硬件电路------------------------3 四．系统的软件设计-------------------------------------5 （1）软件控制流程---------------------------------5（2）程序清单---------------------------------------5 五．系统调试与运行-------------------------------------10 六．设计收获----------------------------------------------11 七．主要参考文献----------------------------------------11一．设计的目的与意义1.加深理解逐次逼近法模数转换器的特征和工作原理。
2.掌握ADC0809的接口方法以及A/D输入程序的设计和调试方法。
3.熟悉DAC0832数模转换器的特性和接口方法。
4.掌握D/A输出程序的设计和调试方法。
5.熟悉LED显示器的星系显示方法。
6.利用对以上知识点的掌握设计出一个自动温控系统。
二．设计的内容与要求利用芯片0832、芯片0809、单片机、温敏电阻或温度传感器、调温器和导线等构建一个完整的全自动的温控系统。
用程序控制0809芯片实现A/D 转换，控制0832芯片实现D/A转换，用程序控制单片机实现温控信号的分析命令的下达，线路实现模拟信号的传输。
三、系统的硬件要求（1）所用芯片的功能介绍ADC0809：ADC0809是采样分辨率为8位的、以逐次逼近原理进行模—数转换的器件。
8位A/D芯片说明主要特点8位逐次逼近型AD转换时间:3uS/bit工作电压范围：2.4V ~ 5.25V4线SPI®/ /MICROWIRE™接口8个模拟输入通道集成采样保持功能可外接参考电压自动低功耗模式4个扩展输出口模拟输入信号变化范围：0~V ref参考电压范围：0V ~ 5.25V16管脚封装DIP/SOP/SSOP功能描述本芯片是一款8位电荷再分布式逐次逼近型AD转换器，AD转换部分使用单电源供电。
它包含一个转换精度为8位的AD 转换器，8个模拟输入通道。
模拟输入电压范围为0到V ref。
V ref的范围为0到VDD。
该芯片通过一个4线SPI®//MICROWIRE™串行接口，与MCU通信。
每次当CS端口为低电平时，在CLK 的激励下，读入DI的控制字，对特定的输入通道作采样保持后，启动一次AD转换，结果通过带三态的输出端口DO传送回MCU。
此外第5至第8通道还具有扩展输出功能，通过设置控制字，实现输出功能。
扩展输出的设置在每次通信CLK最后一个上跳沿（第16个）到来时起效。
每次通信结束，CS变为高电平后，除了扩展输出外，整个芯片将自动进入低功耗模式。
封装示意C SIN1IN2IN3IN4IN5 / V1G N DVD DN CV re fD OD IC LKIN8 / V4IN7/ V3 IN6 / V2芯片结构IN 1IN 2IN 3IN 4IN 5IN 6IN 7IN 8C SC L KD ID OV re fG N DV D DN C管脚说明Pin # 名称 I/O 功能1 CS I 片选信号，低有效2 IN1 I 模拟输入通道13 IN2 I 模拟输入通道24 IN3 I 模拟输入通道35 IN4 I 模拟输入通道46 IN5 / V1 I/O 模拟输入通道5 / IO 输出端17 IN6 / V2 I/O 模拟输入通道6 / IO 输出端28 GND I 接地线9 IN7 / V3 I/O 模拟输入通道7 / IO 输出端3 10 IN8 / V4 I/O 模拟输入通道8 / IO 输出端4 11 CLK I 时钟输入端 12 DI I 数据输入端 13 DO O 数据输出端 14 V ref I 外部基准输入端 15 NC 空脚 16 VDDI电源性能指标(TA=25O C,V ref=5V,VDD=5V)串行通信4线SPI与MCU通信的电路，连接如下图：3线SPI 与MCU 通信的电路，连接如下图：时序波形4线SPI 一次通信的波形图，如下图：C 1C 2C 3C 4C 5C 6C 7C 8D 7D 6D5D 4D 3D 2D 1D 0CS CL KD I D O3线SPI 一次通信的波形图，如下图：C 1C 2C 3C 4C 5C 6C 7C 8D 7D 6D 5D 4D 3D 2D 1D 0CS CL KD O (D I/D O )D I (D I/D O )控制功能8位输入控制字的功能如下表：C1 C2 C3 C4 C5 C6 C7 C8 Addr2 Addr1 Addr0 I/O EN V4 V3 V2 V1解释：1．Addr2，addr1，addr0为三位输入通道选择码，用于指定本次A/D转换的模拟通道。
A/D转换芯片ADC08D1000特性介绍美国国家半导体公司的超高速ADC-ADC08D1000是一款高性能的模/数转换芯片。
它具有双通道结构，每个通道的最大采样率可达到1.6GHz，并能达到8位的分辨率;采用双通道“互插”模式时，采样速率可达2GSPS;采用128脚LQFP 封装，1.9V单电源供电;具有自校准功能，可通过普通方式或扩展方式对其进行控制;可工作在SDR，DDR等多种模式下。
下面对该芯片进行详细介绍。
1ADC08D1000的结构和管脚说明 1.1ADC08D1000的结构 ADC08D1000的美国国家半导体公司的超高速ADC-ADC08D1000是一款高性能的模/数转换芯片。
它具有双通道结构，每个通道的最大采样率可达到1.6 GHz，并能达到8位的分辨率;采用双通道“互插”模式时，采样速率可达2 GSPS;采用128脚LQFP封装，1.9 V单电源供电;具有自校准功能，可通过普通方式或扩展方式对其进行控制;可工作在SDR，DDR等多种模式下。
下面对该芯片进行详细介绍。
1 ADC08D1000的结构和管脚说明1.1 ADC08D1000的结构ADC08D1000的结构，主通道由输入多路模拟开关、采样保持电路、8位ADC和1：2分离器/锁存器组成。
它共有两路相同的通道。
控制逻辑由普通方式或扩展方式进行配置，对整个芯片进行控制。
1.2 ADC08D1000的管脚说明ADC08D500采用128脚LQFP封装，管脚图见图2。
其关键管脚说明如下：(1)OUTV/SCLK：输出电压幅度/串行接口时钟。
高电平时，DCLK和数据信号为普通差分幅度;接地时，差分幅度会降低，从而减少功耗。
当扩展控制模式开启时，此脚为串行时钟脚。
(2)OUTEDGE/DDR/SDATA：DCLK时钟沿选择/DDR功能选择/串行数据输入。
当此脚连接到1/2 VA或者悬空时，进入DDR模式。
扩展控制模式时，这个脚作为SDATA输入。
