IC datasheet pdf-NCP1601A, NCP1601B pdf,detasheet

PDSP1601/PDSP1601A 1The PDSP1601 is a high performance 16-bit arithmetic logic unit with an independent on-chip 16-bit barrel shifter.The PDSP1601A has two operating modes giving 20MHz or 10MHz register-to-register transfer rates.The PDSP1601 supports Multicycle multiprecision operation. This allows a single device to operate at 20MHz for 16-bit fields, 10MHz for 32-bit fields and 5MHz for 64-bit fields.The PDSP1601 can also be cascaded to produce wider words at the 20MHz rate using the Carry Out and Carry In pins. The Barrel Shifter is also capable of extension, for example the PDSP1601 can used to select a 16-bit field from a 32-bit input in 100ns.APPLICATIONS s Digital Signal Processing s Array Processing s Graphicss Database AddressingsHigh Speed Arithmetic ProcessorsFEATURESs 16-bit, 32 instruction 20MHz ALUs 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter s Independent ALU and Shifter Operation s 4 x 16-bit On Chip Scratchpad Registers s Multiprecision Operation; e.g. 200ns 64-bit Accumulates Three Port Structure with Three Internal Feedback Paths Eliminates I/O Bottlenecks s Block Floating Point Supports 300mW Maximum Power Dissipations84-pin Pin Grid Array or 84 Contact LCC Packages or 100 pin Ceramic Quad Flat PackASSOCIATED PRODUCTSPDSP16112Complex MultiplierPDSP1611616 x 16 Complex Multiplier PDSP16318Complex Accumulator PDSP16330Pythagoras ProcessorFig.1 Pin connections - bottom viewORDERING INFORMATIONPDSP1601 MC GGCR 10MHz MIL883 Screened -QFP packagePDSP1601A BO AC 20MHz Industrial - PGA packageN.BFurther details of the Military grade part are available in a separate datasheet (DS3763)PDSP1601/PDSP1601AALU and Barrel ShifterDS3705ISSUE 3.0November 1998PDSP1601/PDSP1601A2FunctionGNDC8C9C10C11C12C13C14C15OEBFPVCCCORA0RA1RA2CIIA0IA1IA2IA3AC pinF9F11E11E10E9D11D10C11B11C10A11B10B9A10A9B8A8B6B7A7C7AC pinJ6J7L7K7L6L8K8L9L10K9L11K10J10K11J11H10H11F10G10G11G9FunctionIS0IS1IS2IS3SV0SV1SV2SV3SVOERS0RS1VCCRS2C0C1C2C3C4C5C6C7AC pinF3G3G1G2F1H1H2J1K1J2L1K2K3L2L3K4L4J5K5L5K6FunctionGNDMSA0MSA1A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0CEAMSCAC pinC6A6A5B5C5A4B4A3A2B3A1B2C2B1C1D2D1E3E2E1F1PIN DESCRIPTIONFunctionIA4MSBMSSB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0CEBCLKGC51525354555657585960616263646566676869707172737475GC26272829303132333435363738394041424344454647484950SIGN/CN/CN/CN/CVCCC0RA0RA1RA2CIIA0IA1IA2IA3IA4MSBMSSB15B14B13B12B11B10B9B8SIGN/CN/CN/CN/CB7B6B5B4B3B2B1B0CEBCLKGNDMSA0MSA1A15A14A13A12A11A10A9A8SIGN/CN/CN/CN/CA7A6A5A4A3A2A1A0CEAMSCIS0IS1IS2IS3SV0SV1SV2SV3SVOERS0RS1GC767778798081828384858687888990919293949596979899100SIGN/CN/CN/CN/CVCCRS2C0C1C2C3C4C5C6C7GNDC8C9C10C11C12C13C14C15OEBFP GC12345678910111213141516171819202122232425N/C = not connected - leave open circuitAll GND and VDD pin must be usedhttps://PDSP1601/PDSP1601A3Symbol MSB MSS B15 - B0CEB CLKMSA0 - MSA1A15 - A0CEA MSC IS0 - IS3SV0 - SV3SVOERS0, RS1RS2C0 - C15OE BFP CO RA0 - RA2CI IA0 - IA3IA4Vcc GND DescriptionALU B-input multiplexer select control.1 This input is latched internally on the rising edge of CLK.Shifter Input multiplexer select control.1 This input is latched internally on the rising edge of CLK.B Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. B15 is the MSB.Clock enable, B Port input register. When low the clock to this register is mon clock to all internal registered elements. All registers are loaded, and outputs change on the rising edge of CLK.ALU A-input multiplexer select control.1 These inputs are latched internally on the rising edge of CLK.A Port data input. Data presented to this port is latched into the input register on the rising edge of CLK. A15 is the MSB.Clock enable, A Port input register. When low the clock to this register is enabled.C-Port multiplexer select control.1 This input is latched internally on the rising edge of CLK.Instruction inputs to Barrel Shifter, IS3 = MSB.1 These inputs are latched internally on the rising edge of CLK.Shift Value I/O Port. This port is used as an input when shift values are supplied fromexternal sources, and as an output when Normalise operations are invoked. The I/O functions are determined by the IS0 - IS3 instruction inputs, and by the SVOE control.The shift value is latched internally on the rising edge of CLK.SV Output enable. When high the SV port can only operate as an input. When low the SV port can act as an input or as an output, according to the IS0 - IS3 instruction. This pin should be tied hihg or low, depending upon the application.Instruction inputs to Barrel Shifter registers.1 These inputs are latched internally on the rising edge of CLK.C Port data output. Data output on this port is selected by the C output multiplexer.C15 is the MSB.Output enable. The C Port outputs are in high impedance condition when this control is high.Block Floating Point Flag from ALU, active high.Carry out from MSB of ALU.Instruction inputs to ALU registers.1 These inputs are latched internally on the rising edge of CLK.Carry in to LSB of ALU.Instruction inputs to ALU.1 IA4 = MSB. These inputs are latched internally on the rising edge of CLK.+5V supply: Both Vcc pins must be connected.0V supply: Both GND pins must be connected.PIN DESCRIPTIONSNOTES1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.https://PDSP1601/PDSP1601A4FUNCTIONAL DESCRIPTIONThe PDSP1601 contains four main blocks: the ALU, the Barrel Shifter and the two Register Files.The ALUThe ALU supports 32 instructions as detailed in Table 1.The inputs to the ALU are selected by the A and B MUXs.Data will fall through from the selected register through the A or B input MUXs and the ALU to the ALU output register file in 50ns for the PDSP1601A (100ns for the PDSP1601).The ALU instructions are latched, such that the instruction will not start executing until the rising edge of CLK latches the instruction into the device.The ALU accepts a carry in from the CI input and supplies a carry out to the CO output. Additionally, at the end of each cycle, the carry out from the ALU is loaded into an internal 1bit register, so that it is available as an input to the ALU on the next cycle. In the manner, multicycle, multiprecision operations are supported. (See MULTICYCLE CASCADE OPERATIONS).BFP FlagThe ALU has a user programmable BFP flag. This flag may be programmed to become active at any one of four conditions. Two of these conditions are intended to support Block Floating Point operations, in that they provide flags indicating that the ALU result is within a factor of two or four of overflowing the 16 bit number range. For multiprecision operations the flag is only valid whilst the most significant 16bit byte is being processed. In this manner the BFP flag may be used over any extended word width.The remaining two conditions detect either an overflow condition or a zero result. For the overflow condition to beactive the ALU result must have overflowed into the 16th (sign)bit, (this flag is only valid whilst the most significant 16 bit byte is being processed). The zero condition is active if the result from the ALU is equal to zero. For multiprecision operations the zero flag must be active for all of the 16 bit bytes of an extended word.The BFP flag is programmed by executing on of the four SBFXX instructions (see Table 1). During the execution of any of these four instructions, the output of the ALU is forced to zero.Multicycle/Cascade OperationThe ALU arithmetic instructions contain two or three options for each arithemtic operation.The ALU is designed to operate with two's complement arithmetic, requiring a one to be added to the LSB for all subtract operations. The instructions set includes instructions that will force a one into the LSB, e.g. MIAX1, AMBX1, BMAX1(see Table 1).These instructions are used for the least significant 16 bit byte of any subtract operation.The user has an option of cascading multiple devices, or multicycling a single device to extend the arithmetic precision.Should the user cascade multiple devices, then the cascade arithmetic instructions using the external CI input should be employed for all but the least significant 16 bit byte, e.g. MIACI,APBCI, BMACI (see Table 1).Should the user multicycle a single device, then the Multicycle Arithmetic instructions, using the internally registered CO bit should be employed for all but the least significant 16 bit byte, e.g. MIACO, APBCO, AMBCO,BMACO (see Table 1).Fig.2 PDSP1601 block diagramhttps://PDSP1601/PDSP1601A5Inst 000102030405060708090A 0B 0C 0D 0E 0FIA4-AI000000000010001000011001000010100110001110100001001010100101101100011010111001111Mnemonic CLRXX MIAX1MIACI MIACO A2SGN A2RAL A2RAR A2RSX APBCI APBCO AMBX1AMBCI AMBCO BMAX1BMACI BMACOOperation RESET MINUS A MINUS A MINUS A A/2A/2A/2A/2A PLUSB A PLUS B A MINUS B A MINUS B A MINUS B B MINUS A B MINUS A B MINUS AMode ---------LSBYTE CASCADE MULTICYCLE MSBYTE MULTICYCLE MULTICYCLE MULTICYCLE CASCADE MULTICYCLE LSBYTE CASCADE MULTICYCLE LSBYTE CASCADE MULTICYCLEFunctionCLEAR ALL REGISTERS NA Plus 1NA Plus CI NA Plus CO A/2 Sign Extend A/2 with RAL LSB A/2 with RAR LSB A/2 with RSX LSB A Plus B Plus CI A Plus B Plus CO A Plus NB Plus 1A Plus NB Plus CI A Plus NB Plus CO NA Plus B Plus 1NA Plus B Plus CI NA Plus B Plus COTable 1 ALU instructions1a. ARITHMETIC INSTRUCTIONSInst 1011121314151617IA4-AI01000010001100101001110100101011011010111Mnemonic ANXAB ANANB ANNAB ORXAB ORNAB XORAB PASXA PASNAOperation A AND B A AND NB NA AND B A OR B NA OR B A XOR B PASS A INVERT AFunction A. B A. NB NA. B A + B NA + B A XOR B A NA1c. CONTROL INSTRUCTIONSInst 18191A 1B 1C 1D 1E 1FIA4-AI01100011001110101101111100111011111011111Mnemonic SBFOV SBFU1SBFU2SBFZE OPONE OPBYT OPNIB OPALTOperationSet BFP Flag to OVR, Force ALU output to zero Set BFP Flag to UND 1 Force ALU output to zero Set BFP Flag to UND 2 Force ALU output to zero Set BFP Flag to ZERO Force ALU output to zero Output 0001 Hex Output 00FF Hex Output 000F Hex Output 5555 HexKEY A = A input to ALU B = B input to ALUCI = External Carry in to ALUCO = Internally Registered Carry out from ALU RAL = ALU Register (Left)RAR = ALU Register (Right)RSX= Shifter Register (Left or Right)MNEMONICSCLRXX Clear All Registers to zero MIAXX Minus A,XX = Carry in to LSB A2XXX A Divided by 2,XXX = Source of MSB APBXX A Plus B,XX = Carry in to LSB AMBXX A Minus B,XX = Carry in to LSB BMAXX B Minus A,XX = Carry in to LSB ANX-Y AND X = Operand 1, Y = Operand 2ORX-Y OR X = Operand 1, Y = Operand 2XORXY Exclusive OR X = Operand 1, Y = Operand 2PASXX Pass XX = Operand SBFXX Set BFP Flag XX = Function OPXXXOutput Constant XXX1b. LOGICAL INSTRUCTIONShttps://PDSP1601/PDSP1601A6Divide by TwoThe ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)instructions used for right shifting (dividing by two) extended precision words. These words, (up to 64 bits) may be stored in the two on-chip register files. When the least significant 16bit word is shifted, the vacant MSB must be filled with the LSB from the next most significant 16 bit byte. This is achieved via the A2RAL, A2RAR or A2RSX instructions which indicate the source of the new MSB (see ALU INSTRUCTION SET).When the most significant 16 bit byte is right shifted, the MSB must be filled with a duplicate of the original MSB so as to maintain the correct sign (Sign Extension). This operation is achieved via the A2SGN instruction (see Table 1).ConstantsThe ALU has four instructions (OPONE, OPBYT, OPNIB,OPALT) that force a constant value onto the ALU output.These values are primarily intended to be used as masks, or the seeds for mask generation, for example, the OPONE instruction will set a single bit in the least significant position.This bit may be rotated any where in the 16 bit field by the Barrel Shifter, allowing the AND function of the ALU to perform bit-pick operations on input data.CLRThe ALU instruction CLRXX is used as a Master Reset for the entire device. This instruction has the effect of:1.Clearing ALU and Barrel Shifter register files to zero.2.Clearing A and B port input registers to zero.3.Clearing the R1 and R2 shift control registers to zero.4.Clearing the internally registered CO bit to zero.5.Programming the BFP flag to detect overflow conditions.The Barrel ShifterThe Barrel Shifter supports 16 instructions as detailed in Table 2. The input to the Barrel Shifter is selected by the S MUX. Data will fall through from the selected register, through the S MUX and the Barrel Shifter to the shifter output register file in 50ns for the PDSP1601A (100ns for the PDSP1601).The Barrel Shifter instructions are latched, such that the instructions will not start executing until the rising edge of CLK latches the instruction into the device.The Barrel Shifter is capable of Logical Arithmetic or Barrel Shifts in either direction.A.Logical shifts discard bits that exit the 16 bit field and fill spaces with zeros.B.Arithmetic shifts discard bits that exit the 16 bit field and fill spaces with duplicates of the original MSB.C.Barrel Shifts rotate the 16 bit fields such that bits tha exit the 16 bit field to the left or right reappear in the vacant spaces on the right or left.The amount of shift applied is encoded onto the 4 bit Barrel Shifter input as illustrated in Table 3. The type of shift and the amount are determined by the shift control block. The shift control block (see Fig.3) accepts and decodes the four bit ISO-3 instruction. The shift control block contains a priority encoder and two user programmable 4 bit registers R1 and R2.There are four possible sources of shift value that can be passed onto the Barrel Shifter, there are:1.The Priority Encoder 2.The SV input 3.The R1 register 4.The R2 register Mnemonic LSRSV LSLSV BSRSV BSLSV LSRR1LSLR1LSRR2LSLR2LR1SV LR2SV ASRSV ASRR1ASRR2NRMXX NRMR1NRMR2IS3-IS00000000100100011010001010110011110001001101010111100110111101111OperationLogical Shift Right by SV Logical Shift Left by SV Barrel Shift Right by SV Barrel Shift Left by SV Logical Shift Right by R1Logical Shift Left by R1Logical Shift Right by R2Logical Shift Left by R2Load Register 1 From SV Load Register 2 From SV Arithmetic Shift Right by SV Arithmetic Shift Right by R1Arithmetic Shift Right by R2Normalise Output PENormalise Output PE, Load R1Normalise Output PE, Load R2Inst 0123456789A B C D E FI/O I I I I X X X X I I I X X O O OTable 2 Barrel shifter instructionsKEY SV = Shift Value R1= Register 1R2= Register 2PE = Priority Encoder OutputI => SV Port operates as an Input O => SV Port operates as an Output X=> SV Port in a High Impedance StateMNEMONICSLSXYY Logical Shift,X = Direction YY = Source of Shift Value BSXYY Barrel Shift,X = Direction YY = Source of Shift Value ASXYY Arithmetic Shift,X = Direction YY = Source of Shift Value LXXYY Load XX = Target YY = SourceNRMYYNormalise by PE, Output PE value on SV Port, Load YY Reghttps://PDSP1601/PDSP1601A7SV30000000011111111SV20000111100001111SV10011001100110011SV00101010101010101Shift No shift 1 place 2 places 3 places 4 places 5 places 6 places 7 places 8 places 9 places 10 places 11 places 12 places 13 places 14 places 15 places(1)Priority encode the 16 bit input to the Barrel Shifter and place the 4 bit value in either of the R1 or R2 registers and output the value on the SV port (if enabled by SVOE ).(2)Shift the 16 bit input by the amount indicated by the Priority Encoder such that the output from the Barrel Shifter is a normalised value.SV InputIf the SV port is selected as the source of the shift value,then the input to the Barrel Shifter is shifted by the value stored in the internal SV register.SVOEThe SV port acts as an input or an output depending upon the IS0-3 instruction. If the user does not wish to use the normalise instructions, then the SV port mat be forced to be input only by typing SVOE control high. In this mode the SV port may be considered an extension of the instruction inputs.R1 and R2 RegistersThe R1 and R2 registers may be loaded from the Priority Encoder (NRMR1 and NRMR2) or from the SV input (LR1SV,LR2SV).Whilst the latter two instructions are executing, the Barrel Shifter will pass its input to the output unshifted.Priority EncoderIf the priority encoder is selected as the source of the shift value (instructions:- NRMXX, NRMR1, MRMRZ), then within one 100ns cycle or two 50ns cycles for the PDSP1601A (one 200ns or two 100ns cycles for the PDSP1601), the shift circuitry will:Table 3 Barrel shifter codesFig.3 Shift control blockhttps://PDSP1601/PDSP1601A8The Register FilesThere are two on-chip register files (ALU and Shifter), each containing two 16 bit registers and each supporting 8instructions (see Table 4). The instructions for the ALU register file and the Barrel Shifter Register file are the same.The Inputs to the register files come from either the ALU or the Barrel Shifter, and are loaded into the Register files on the rising edge of CLK.The register file instructions are latched such that the instruction will not start executing until the rising edge of theCLK latches the instruction into the device.The register file instructions (see Table 4) allow input data to be loaded into either, neither or both of the registers. Data is loaded at the end of the cycle in which the instruction is executing.The register file instructions allow the output to be sourced from either of the two registers, the selected output will be valid during the cycle in which the instruction is executing.OperationLoad Left Reg Output Right Reg Load Right Reg Output Left Reg Load Left Register, Output Left Reg Load Right Register, Output Right Reg Load Both Registers, Output Left Reg No Load Operation, Output Right Reg No Load Operation, Output Left RegNo Load Operation, Pass Barrel Shifter ResultOperationLoad Left Reg Output Right Reg Load Right Reg Output Left Reg Load Left Register, Output Left Reg Load Right Register, Output Right Reg Load Both Registers, Output Left Reg No Load Operation, Output Right Reg No Load Operation, Output Left Reg No Load Operation, Pass ALU ResultInst 01234567RA2-RA0000001010011100101110111Mnemonic LLRRR LRRLR LLRLR LRRRR LBRLR NOPRR NOPLR NOPPSALU REGISTER INSTRUCTIONSInst 01234567RA2-RA0000001010011100101110111Mnemonic LLRRR LRRLR LLRLR LRRRR LBRLR NOPRR NOPLR NOPPSSHIFTER REGISTER INSTRUCTIONSTable 4 ALU and shift register instructions mnemonicsMNEMONICSLXXYY Load XX = Target,YY = Source of Output LBOXX Load Both Registers,XX = Source of Output NOPXX No Load Operation,XX= Source of Outputhttps://PDSP1601/PDSP1601A9MARAX MAAPR MABPR MARSXMultiplexersThere are four user selectable on-chip multiplexers (A-MUX, B-MUX, S-MUX and C-MUX).These four multiplexers support instructions as tabulated in Table 5.The MUX instructions are latched such that the instruction will not start executing until the rising edge of CLK latches the instruction onto the device.MSA10011A-MUXOutputALU REGISTER FILE OUPUT A-PORT INPUT B-PORT INPUTSHIFTER REGISTER FILE OUTPUTMSB01B-MUXOutputB-PORT INPUTSHIFTER REGISTER FILE OUTPUTMSS01S-MUXOutputB-PORT INPUTSHIFTER REGISTER FILE OUTPUTMSC01C-MUXOutputALU REGISTER FILE OUTPUTSHIFTER REGISTER FILE OUTPUTTable 5MSA00101https://PDSP1601/PDSP1601A10INSTRUCTION SETALU Arithmetic Instructions FunctionOn the rising edge of CLK at the end of the cycle in which this instruction is executing, the A Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros.The internal registered CO will also be set to zero, and the BFP flag will be set to activate on overflow conditions.The A input to the ALU is inverted and a one is added to the LSB.The A input to the ALU is inverted and the CI input is added to the LSB.The A input to the ALU is inverted and the CO output from the ALU on the previous cycle is added to the LSB.The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant MSB is filled by duplicating the original MSB (Sign Extension).The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant MSB is filled with the LSB from the ALU register.The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant MSB is filled with the LSB from the ALU register.The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant MSB is filled with the LSB from the B input to the ALU.The A input to the ALU is added to the B input, and the CI input is added to the LSB.The A input to the ALU is added to the B input, and the CO out from the ALU on the previous cycle is added to the LSB.The A input to the ALU is added to the inverted B input, and a one is added to the LSB.The A input to the ALU is added to the inverted B input, and the CI input is added to the LSB.The A input to the ALU is added to the inverted B input, and the CO out from the ALU on the previous cycle is added to the LSB.The inverted A input to the ALU is added to the B input, and a one is added to the LSB.The inverted A input to the ALU is added to the B input, and the CI input is added to the LSB.The inverted A input to the ALU is added to the B input, and the CO out from the ALU on the previous cycle is added to the LSB.Op Code <00><01><02><03><04><05><06><07><08><09><0A><0B><0C><0D><0E><0F>Mnemonic CLRXXMIAX1MIAC1MIACO A2SGN A2RAL A2RAR A2RSX APBCI APBCO AMBX1AMBCI AMBCO BMAX1BMAC1BMACOALU Logical Instructions FunctionThe A input to the ALU is logically 'ANDed' with the B input.The A input to the ALU is logically 'ANDed' with the inverse of the B input.The inverse of the A input to the ALU is logically 'ANDed' with the B input.The A input to the ALU is logically 'ORed' with the B input.The inverse A input to the ALU is logically 'ORed' with the B input.The A input to the ALU is logically Exclusive-ORed with the B input.The A input to the ALU is passed to the output.The inverse of the A input to the ALU is passed to the output.Op Code <10><11><12><13><14><15><16><17>Mnemonic ANXAB ANANB ANNAB ORXAB ORNAB XORAB PASXA PASNAhttps://ALU Control Instructions FunctionThe BFP flag is programmed to activate when an ALU operation causes an overflow of the 16 bit number range. This flag is logically the exclusive-or of the carry into and out of the MSB of the ALU. For the most significant Byte this flag indicates that the result of an arithmetic two's complement operation has overflowed into the sign bit. The output of the ALU is forced to zero for the duration of this instruction.The BFP flag is programmed to activate when an ALU operation comes within a factor of two of causing an overflow of the 16 bit number range. For the most significant Byte this flag indicates that the result of an arithmetic two's complement operation is within a factor of two of overflowing into the sign bit. The output of the ALU is forced to zero for the duration of this instruction.The BFP flag is programmed to activate when an ALU operation comes within a factor of four of causing an overflow of the 16 bit number range. For the most significant Byte this flag indicates that the result of an arithmetic two's complement operation is within a factor of four of overflowing into the sign bit. The output of the ALU is forced to zero for the duration of this instruction.The BFP flag is programmed to activate when an ALU operation causes a result of zero.The output of the ALU is forced to zero for the duration of this instruction. During the execution of this instruction the BFP flag will become active.The ALU will output the binary value 0000000000000001, the MSB on the left.The ALU will output the binary value 0000000011111111, the MSB on the left.The ALU will output the binary value 0000000000001111, the MSB on the left.The ALU will output the binary value 0101010101010101, the MSB on the left.Op Code <18><19><1A><1B><1C><1D><1E><1F>Mnemonic SBFOVSBFU1SBFU2SBFZEOPONE OPBYT OPNIB OPALTBarrel Shifter Instructions FunctionThe 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by the magnitude of the four bit number present in the SV register. The LSBs are dicarded,and the vacant MSBs are filled with zeros.The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the magnitude of the four bit number present in the SV register. The LSBs are dicarded, and the vacant MSBs are filled with zeros.The 16 bit input to the Barrel Shifter is rotated to the right by the number of places indicated by the magnitude of the four bit number present in the SV register. The LSBs that exit the 16 bit field to the right, reappear in the vacant MSBs on the left.The 16 bit input to the Barrel Shifter is rotated to the left by the number of places indicated by the magnitude of the four bit number present in the SV register. The LSBs that exit the 16 bit field to the right, reappear in the vacant MSBs on the right.The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by the magnitude of the four bit number resident within the R1 register. The LSBs are discarded, and the vacant MSBs are filled with zeros.The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the magnitude of the four bit number resident within the R1 register. The LSBs are discarded,and the vacant LSBs are filled with zeros.The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by the magnitude of the four bit number resident within the R2 register. The LSBs are discarded, and the vacant MSBs are filled with zeros.The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the magnitude of the four bit number resident within the R2 register. The LSBs are discarded,and the vacant LSBs are filled with zeros.Op Code <0><1><2><3><4><5><6><7>Mnemonic LSRSVLSLSVBSRSVBSLSVLSRR1LSLR1LSRR2LSLR2https://。

龙源期刊网
功率因数校正控制器ＮＣＰ１６０１
作者：祝大卫
来源：《电子世界》2005年第04期
采用桥式整流器和大容量电容滤波的荧光灯电子镇流器、开关电源和电机调速器，在滤波电容上的直流电压纹波近似锯齿波，并且最小值（远远大于零）与最大值相差不大。

根据桥式整流二极管的单向导电性，只有在交流输入电压（Vac）瞬时幅度高于滤波电容上的电压时，二极管才会因正向偏置而导通。

因此，桥式二极管只是在AC线路供电电压的峰值附近才会导通，导通角不是90°。

这虽然不影响AC输入电压的正弦波形，但AC输入电流（Iac）却发生严重失真，不再为正弦波，而呈高幅度的尖峰脉冲，如图1所示。

这种电流波形的基波成份很低，而高次谐波含量很大，对供电系统造成污染，使电磁干扰问题十分突出，同时引起系统功率因数下降，通常仅为0.55～0.6。

NCP1601型功率因数校正控制器的原理及应用1 概述安森美半导体公司推出的NCP1601型功率因数功率因数校正（PFC）控制器能不连续传导模式（DCM）和临界传导模式（CRM或BCM）下工作，它兼有二种工作模式的优点。

因固定频率DCM可限制最高开关频率开关频率，从而限制污染系统环境的传导辐射和EMI噪声。

而不定频率CRM则可限制升压MOSFET、二极管和电感器的最大电流，以降低成本，提高电路的可靠性。

NCP1601结合DCM与CRM的优点及高安全性保护特征，适合于电子镇流器，AC适配器、TV与临视器等中低功率电源PFC预调节器应用。

可在DCM和CRM下工作是NCP1601的主要创新点。

NCP1601的其他特点如下：&middot;在电压工作模式下能提供简单的电压模式反馈；&middot;启动电流（典型值为17&mu;A）和关闭电流（典型值为24&mu;A）低；&middot;DCM开关频率可编程；&middot;可同步模式工作（OSC脚可以接收外部数字信号）；&middot;具有保护（OVO）功能，其门限电平是PFC级输出电压正常值的107%；&middot;通过其欠保护（UVP）功能可在输出电压降至正常调节电平的92%以下时，自动关闭；&middot;具有可编程过电流保护（OCP）；&middot;过热关闭（OTSD）功能可在结温结温超过140℃时截止IC并当结温降至95℃以下时使器件恢复工作；&middot;满足IEC1000-3-2标准规定的输入电流谐波限制要求。

MCP1601有NCP1601A和NCP1601B二种型号，二者的Vcc欠压锁定（UVLO）滞后电压不同。

NCP1601A的UVLO带4.75V的滞后，而NCP1601B的UVLO滞后则是1.5V。

2 基本结构及引脚排列NCP1601采用8引脚PDIP和8引脚SO封装（结温范围为-40℃～+125℃），引脚排列。

TMFEATURESAPPLICATIONSDESCRIPTIONTHD+N–TotalHarmonicDistortion+Noise–%1070G0120.010.12010.110P O – Output Power – W1TAS5186ASLES156–OCTOBER2005 6-Channel,210-W,Digital-Amplifier Power StageThe TAS5186A requires only simple passivedemodulation filters on its outputs to deliver •Total Output Power@10%THD+Nhigh-quality,high-efficiency audio amplification.The –5×30W@6Ω+1×60W@3Ωdevice efficiency of the TAS5186A is greater than90%when driving6-Ωsatellites and a3-Ωsubwoofer •105-dB SNR(A-Weighted)speaker.•0.07%THD+N@1WThe TAS5186A has an innovative protection system •Power Stage Efficiency>90%Intointegrated on-chip,safeguarding the device against a Recommended Loads(SE)wide range of fault conditions that could damage the •Integrated Self-Protection Circuits system.These safeguards are short-circuit protection,–Undervoltage overload protection,undervoltage protection,andovertemperature protection.The TAS5186A has a –Overtemperaturenew proprietary current-limiting circuit that reduces –Overloadthe possibility of device shutdown during high-level –Short Circuit music transients.A new programmable overcurrentdetector allows the use of lower-cost inductors in the •Integrated Active-Bias Control to Avoid DCdemodulation output filter.Pop•Thermally Enhanced44-Pin HTSSOP Package TOTAL HARMONIC DISTORTION+NOISEvs•EMI-Compliant When Used WithOUTPUT POWER Recommended System Design•DVD Receiver•Home Theater in a BoxThe TAS5186A is a high-performance,six-channel,digital-amplifier power stage with an improvedprotection system.The TAS5186A is capable ofdriving a6-Ω,s ingle­ended load up to30W per eachfront/satellite channel and a3-Ω,single-endedsubwoofer greater than60W at10%THD+Nperformance.A low-cost,high-fidelity audio system can be builtusing a TI chipset comprising a modulator(e.g.,TAS5086)and the TAS5186A.This device does notrequire power-up sequencing because of the internalpower-on reset.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DDV PACKAGE (TOP VIEW)P0016-03TAS5186ASLES156–OCTOBER 2005These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.The TAS5186A is available in a thermally enhanced 44-pin HTSSOP PowerPAD™package.The heat slug is located on the top side of the device for convenient thermal coupling to a heatsink.2TAS5186ASLES156–OCTOBER 2005GENERAL INFORMATION (continued)TERMINAL FUNCTIONSTERMINAL TYPE (1)DESCRIPTIONNAME NO.AGND 12P Analog groundBST_A 23P HS bootstrap supply (BST),capacitor to OUT_A required BST_B 29P HS bootstrap supply (BST),external capacitor to OUT_B required BST_BIAS 21P BIAS bootstrap supply,external capacitor to OUT_BIAS required BST_C 30P HS bootstrap supply (BST),external capacitor to OUT_C required BST_D 37P HS bootstrap supply (BST),external capacitor to OUT_D required BST_E 38P HS bootstrap supply (BST),external capacitor to OUT_E required BST_F 44P HS bootstrap supply (BST),external capacitor to OUT_F required GND 11P Chip groundGVDD_ABC 20P Gate drive voltage supply GVDD_DEF 3P Gate drive voltage supply M110I Mode selection pin M29I Mode selection pin M38I Mode selection pinOC_ADJ 14O Overcurrent threshold programming pin,resistor to ground required OTW 16O Overtemperature warning open-drain output signal,active-low OUT_A 25O Output,half-bridge A,satellite OUT_B 27O Output,half-bridge B,satellite OUT_BIAS 22O BIAS half-bridge output pin OUT_C 32O Output,half-bridge C,subwoofer OUT_D 35O Output,half-bridge D,satellite OUT_E 40O Output,half-bridge E,satellite OUT_F42OOutput,half-bridge F,satellite1,26,PGND 33,P Power ground34,41PVDD_A 24P Power-supply input for half-bridge A PVDD_B 28P Power-supply input for half-bridge B PVDD_C 31P Power-supply input for half-bridge C PVDD_D 36P Power-supply input for half-bridge D PVDD_E 39P Power-supply input for half-bridge E PVDD_F 43P Power-supply input for half-bridge F PWM_A 19I PWM input signal for half-bridge A PWM_B 18I PWM input signal for half-bridge B PWM_C 17I PWM input signal for half-bridge C PWM_D 6I PWM input signal for half-bridge D PWM_E 5I PWM input signal for half-bridge E PWM_F 2I PWM input signal for half-bridge F RESET 7I Reset signal (active-low logic)SD 15O Shutdown open-drain output signal,active-low VDD 4P Power supply for digital voltage regulator VREG 13ODigital regulator supply filter pin,output(1)I =input;O =output;P =power3PACKAGE HEAT DISSIPATION RATINGS (1)ABSOLUTE MAXIMUM RATINGSTAS5186ASLES156–OCTOBER 2005Table 1.MODE Selection PinsMODE PINS (1)MODEM2M3NAMEDESCRIPTION00 2.1mode Channels A,B,and C enabled;channels D,E,and F disabled01 5.1mode All channels enabled10/1Reserved(1)M1must always be connected to GND.0indicates a pin connected to GND;1indicates a pin connected to VREG.PARAMETERTAS5186ADDVR θJC (°C/W)—1satellite (sat.)FET only 10.3R θJC (°C/W)—1subwoofer (sub.)FET only5.2R θJC (°C/W)—1sat.half-bridge 5.2R θJC (°C/W)—1sub.half-bridge 2.6R θJC (°C/W)—5sat.half-bridges +1sub.1.74Typical pad area (2)34.9mm 2(1)JC is junction-to-case,CH is case-to-heatsink.(2)R θCH is an important consideration.Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink.The R θCH with this condition is typically 2°C/W for this package.over operating free-air temperature range (unless otherwise noted)(1)TAS5186AVDD to AGND –0.3V to 13.2V GVDD_X to AGND –0.3V to 13.2V PVDD_X to PGND_X (2)–0.3V to 50V OUT_X to PGND_X (2)–0.3V to 50V BST_X to PGND_X (2)–0.3V to 63.2V VREG to AGND –0.3V to 4.2V PGND to GND –0.3V to 0.3V PGND to AGND –0.3V to 0.3V GND to AGND–0.3V to 0.3V PWM_X,OC_ADJ,M1,M2,M3to AGND –0.3V to 4.2V RESET,SD,OTW to AGND–0.3V to 7V Maximum operating junction temperature range (T J )0to 125°C Storage temperature–40°C to 125°CLead temperature –1,6mm (1/16inch)from case for 10seconds 260°C Minimum PWM pulse duration,low 30ns(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)These voltages represent the dc voltage +peak ac waveform measured at the terminal of the device in all conditions.4M1M2RESETSD OTWAGND OC_ADJVREG VDDGVDD_DEF M3GNDPWM_FOUT_F PGND PVDD_FBST_FPWM_EOUT_E PGND PVDD_E BST_EPWM_DOUT_D PGND PVDD_D BST_DPWM_COUT_C PGND PVDD_C BST_CPWM_BOUT_B PGND PVDD_B BST_BPWM_AOUT_APVDD_A BST_AOUT_BIASBST_BIASB0034-03GVDD_ABC TAS5186ASLES156–OCTOBER 2005TYPICAL SYSTEM DIAGRAMA schematic diagram for a typical system is appended at the end of the data sheet.FUNCTIONAL BLOCK DIAGRAM5RECOMMENDED OPERATING CONDITIONSAUDIO SPECIFICATIONTAS5186ASLES156–OCTOBER 2005MINTYPMAX UNIT PVDD_X Half-bridge supply,SEDC supply voltage at pin(s)040V GVDD Gate drive and guard ring supply voltage DC voltage at pin(s)10.81213.2V VDD Digital regulator supply DC supply voltage at pin 10.81213.2V Any value of R PU,EXT within VPU Pullup voltage supply35 5.5V recommended rangeResistive load impedance,satellite Recommended demodulation filter R L,SAT 46Ωchannels (1)Resistive load impedance,subwoofer Recommended demodulation filter R L,SUB 2.253ΩchannelMinimum output inductance under L output Demodulation filter inductance 522µH short-circuit conditionC output,sat Demodulation filter capacitance 1µF C output,sub Demodulation filter capacitance 1µF F PWM PWM frame rate192384432kHz(1)Load impedance outside range listed might cause shutdown due to OLP,OTE,or NLP.PVDD_X =40V,GVDD =12V,audio frequency =1kHz,AES17measurement filter,F PWM =384kHz,case temperature =75°C.Audio performance is recorded as a chipset,using TAS5086PWM processor with an effective modulation index limit of 97%.All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified.PARAMETERCONDITIONSMINTYP MAXUNITR L =6Ω,10%THD,clipped input signal30R L =8Ω,10%THD,clipped input signal 25P O,satPower output per satellite channelWR L =6Ω,0dBFS,unclipped input signal 25R L =8Ω,0dBFS,unclipped input signal 20R L =3Ω,10%THD,clipped input signal60R L =4Ω,10%THD,clipped input signal 52P O,subPower output,subwooferW R L =3Ω,0dBFS,unclipped input signal 50R L =4Ω,0dBFS,unclipped input signal40R L =6Ω,P O =25W 0.3%Total harmonic distortion +noise,satelliteR L =6Ω,1W 0.07%THD +NR L =3Ω,P O =50W 0.5%Total harmonic distortion +noise,subwooferR L =3Ω,1W 0.05%Output integrated noise,satellite A-weighted 55V n µV Output integrated noise,subwoofer A-weighted 60SNR System signal-to-noise ratio A-weighted105dB Dynamic range (1)A-weighted,–60dBFS input signal,105DNRdB measured with TAS5086PWM processor P O =0W,all channels running 5.1mode (2).22-µH Kwang-Sung inductors (see 4.5W Power dissipation due to idle losses schematic for information)P idle(IPVDDX)P O =0W,2.1mode.22-µH Kwang-Sung 2.2W inductors (see schematic for information)(1)SNR is calculated relative to 0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.6ELECTRICAL CHARACTERISTICSTAS5186ASLES156–OCTOBER 2005F PWM =384kHz,GVDD =12V,VDD =12V,T C (case temperature)=75°C,unless otherwise noted.All performance is in accordance with recommended operating conditions,unless otherwise specified.SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR ANDCURRENT CONSUMPTIONVREG Voltage regulator,only used as reference node VDD =12V33.3 3.6V Operating,50%duty cycle 720IVDD VDD supply currentmA Idle,reset mode 61650%duty cycle 522IGVDD_XGate supply current per half-bridgemAIdle,reset mode1350%duty cycle,without output filter or load,5.1110mode.22-µH Kwang-Sung inductorsIPVDD_X Half-bridge idle currentmA50%duty cycle,without output filter or load,2.160mode.22-µH Kwang-Sung inductors OUTPUT STAGE MOSFETs R DSon ,LS Sat Drain-to-source resistance,low side,satellite T J =25°C,includes metallization resistance 210m ΩR DSon ,HS Sat Drain-to-source resistance,high side,satellite T J =25°C,includes metallization resistance 210m ΩR Dson ,LS Sub Drain-to-source resistance,low side,subwoofer T J =25°C,includes metallization resistance 110m ΩR Dson ,HS Sub Drain-to-source resistance,high side,subwooferT J =25°C,includes metallization resistance110m ΩI/O PROTECTION V UVP,G Undervoltage protection limit GVDD_X 10V V UVP,hyst (1)Undervoltage protection hysteresis 250mV OTW (1)Overtemperature warning125°C Temperature drop needed below OTW temp.for OTW hyst (1)25°C OTW to be inactive after the OTW event OTE (1)Overtemperature error155°C Temperature drop needed below OTE temp.for SD OTE HYST (1)25°C to be released after the OTE event OLCP Overload protection counter 1.25ms Overcurrent limit protection,satellite Rocp =18k Ω 4.5A I OC Overcurrent limit protection,subwoofer Rocp =18k Ω8A I OCT Overcurrent response time 210ns Rocp OC programming resistor range Resistor tolerance =5%18k ΩSTATIC DIGITAL SPECIFICATIONV IH High-level input voltage 2PWM_X,M1,M2,M3,RESET V V IL Low-level input voltage 0.8I LEAKInput leakage currentStatic condition–8080µAOTW/SHUTDOWN (SD)Internal pullup resistor to DREG (3.3V)for SD and R INT_PU 26k ΩOTWInternal pullup resistor only3 3.33.6V OH High-level output voltage External pullup:4.7-k Ωresistor to 5V 4.55V V OL Low-level output voltage I O =4mA 0.20.4FANOUTDevice fanout OTW,SDNo external pullup30Devices (1)Specified by design.7TYPICAL CHARACTERISTICS,5.1MODET H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1040G0010.010.12010.110P O – Output Power – W1T H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1070G0020.010.12010.110P O – Output Power – W1PVDD – Supply Voltage – V 024681012141618202224262830323436P O – O u t p u t P o w e r – WG003PVDD – Supply Voltage – V510152025303540455055606570G004P O – O u t p u t P o w e r – WTAS5186ASLES156–OCTOBER 2005TOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsOUTPUT POWEROUTPUT POWERFigure 1.Figure 2.OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 3.Figure 4.8PVDD – Supply Voltage – V 0246810121416182022242628G005P O – O u t p u t P o w e r – WPVDD – Supply Voltage – V0510152025303540455055G006P O – O u t p u t P o w e r – W20406080100120140160180200220240S y s t e m E f f i c i e n c y – %G007P O – Total Output Power – W051015202530354020406080100120140160180200220240S y s t e m P o w e r L o s s – WG008P O – Total Output Power – WTAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsSUPPLY VOLTAGESUPPLY VOLTAGEFigure 5.Figure 6.SYSTEM EFFICIENCYSYSTEM POWER LOSSvsvsTOTAL OUTPUT POWERTOTAL OUTPUT POWERFigure 7.Figure 8.9T C – Case Temperature – °C 0510********35402030405060708090100110G009P O – O u t p u t P o w e r – WT C – Case Temperature – °C010203040506070802030405060708090100110G010P O – O u t p u t P o w e r – Wf – Frequency – kHz−150−140−130−120−110−100−90−80−70−60−50−40−30−20−1000246810121416182022A m p l i t u d e – d BG011TAS5186ASLES156–OCTOBER 2005TYPICAL CHARACTERISTICS,5.1MODE (continued)OUTPUT POWEROUTPUT POWERvsvsCASE TEMPERATURECASE TEMPERATUREFigure 9.Figure 10.AMPLITUDEvsFREQUENCYFigure 11.10 THEORY OF OPERATIONPOWER SUPPLIESSYSTEM POWER-UP/DOWN SEQUENCE Powering Down Error Reporting TAS5186ASLES156–OCTOBER 2005reliability,it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same To facilitate system design,the TAS5186A needsside of the PCB as the TAS5186A.It is only a 12-V supply in addition to a typical 39-Vrecommended to follow the PCB layout of the power-stage supply.An internal voltage regulatorTAS5186A reference design.For additional provides suitable voltage levels for the digital andinformation on the recommended power supply and low-voltage analog circuitry.Additionally,all circuitryrequired components,see the application diagrams requiring a floating voltage supply,e.g.,the high-sidegiven in this data sheet.The 12-V supply should be gate drive,is accommodated by built-in bootstrappowered from a low-noise,low-output-impedance circuitry requiring only a few external capacitors.voltage regulator.Likewise,the 39-V power-stage supply is assumed to have low output impedance and In order to provide outstanding electrical and acousticlow noise.The power-supply sequence is not critical characteristics,the PWM signal path including gatedue to the internal power-on-reset circuit.Moreover,drive and output stage is designed as identical,the TAS5186A is fully protected against erroneous independent half-bridges.For this reason,eachpower-stage turnon due to parasitic gate charging.half-bridge has separate bootstrap pins (BST_X)andThus,voltage-supply ramp rates (dv/dt)are typically power-stage supply pins (PVDD_X).Furthermore,annoncritical.additional pin (VDD)is provided as power supply forall common circuits.Although supplied from the same12-V source,it is highly recommended to separateGVDD_X and VDD on the printed-circuit board (PCB)The TAS5186A does not require a power-up by RC filters (see application diagram for details).sequence.The outputs of the H-bridge remain in a These RC filters provide the recommendedhigh-impedance state until the gate-drive supply high-frequency isolation.Special attention should bevoltage (GVDD_X)and VDD voltage are above the paid to placing all decoupling capacitors as close toundervoltage protection (UVP)voltage threshold (see their associated pins as possible.In general,the Electrical Characteristics section of this data inductance between the power-supply pins andsheet).Although not specifically required,it is decoupling capacitors must be avoided.(Seerecommended to hold RESET in a low state while reference board documentation for additionalpowering up the rmation.)When the TAS5186A is being used with TI PWM For a properly functioning bootstrap circuit,a smallmodulators such as the TAS5086,no special ceramic capacitor must be connected from eachattention to the state of RESET is required,provided bootstrap pin (BST_X)to the power-stage output pinthat the chipset is configured as recommended.(OUT_X).When the power-stage output is low,thebootstrap capacitor is charged through an internaldiode connected between the gate-drivepower-supply pin (GVDD_X)and the bootstrap pin.The TAS5186A does not require a power-down When the power-stage output voltage is high,thesequence.The device remains fully operational as bootstrap capacitor voltage is shifted above thelong as the gate-drive supply (GVDD_X)voltage and output voltage potential and thus provides a suitableVDD voltage are above the undervoltage protection voltage supply for the high-side gate driver.In an(UVP)threshold level (see the Electrical application with PWM switching frequencies in theCharacteristics section of this data sheet).Although range 352kHz to 384kHz,it is recommended to usenot specifically required,it is a good practice to hold 33-nF ceramic capacitors,size 0603or 0805,for theRESET low during power down,thus preventing bootstrap capacitor.These 33-nF capacitors ensureaudible artifacts including pops and clicks sufficient energy storage,even during minimal PWMWhen the TAS5186A is being used with TI PWM duty cycles,to keep the high-side power stage FETmodulators such as the TAS5086,no special (LDMOS)fully started during all of the remaining partattention to the state of RESET is required,provided of the PWM cycle.In an application running at athat the chipset is configured as recommended.reduced switching frequency,generally 250kHz to192kHz,the bootstrap capacitor might need to beincreased in value.Special attention should be paidto the power-stage power supply;this includesThe SD and OTW pins are both active-low,component selection,PCB placement and routing.Asopen-drain outputs.Their function is for indicated,each half-bridge has independentprotection-mode signaling to a PWM controller or power-stage supply pins (PVDD_X).For optimalother system-control device.electrical performance,EMI compliance,and systemDevice Protection SystemOVERCURRENT (OC)PROTECTION WITH TAS5186ASLES156–OCTOBER 2005Any fault resulting in device shutdown is signaled bytwo protection systems.The first protection system the SD pin going low.Likewise,OTW goes low whencontrols the power stage in order to prevent the the device junction temperature exceeds 125°C (seeoutput current from further increasing.i.e.,it performs the following table).a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker SDOTW DESCRIPTION load-impedance drops.If the high-current situation persists,i.e.,the power stage is being overloaded,a 00Overtemperature (OTE)or overload (OLP)or undervoltage (UVP)second protection system triggers a latching shutdown,resulting in the power stage being set in 01Overload (OLP)or undervoltage (UVP)the high-impedance (Hi-Z)state.10Overtemperature warning.Junction temperature higher than 125°C,typical For added flexibility,the OC threshold is 11Normal operation.Junction temperature lower thanprogrammable within a limited range using a single 125°C,typical external resistor connected between the OC_ADJ pinand AGND.It should be noted that asserting RESET low forces OC-Adjust Resistor ValuesMaximum Peak Current Before the SD and OTW signals high independently of faults (k Ω)OC Occurs (A)being present.It is recommended to monitor the 18 4.5(sat.),8(sub.)OTW signal using the system microcontroller and torespond to an overtemperature warning signal by,It should be noted that a properly functioning e.g.,turning down the volume to prevent furtherovercurrent detector assumes the presence of a heating of the device that would result in deviceproperly designed demodulation filter at the shutdown (OTE).To reduce external componentpower-stage output.Short-circuit protection is not count,an internal pullup resistor to 3.3V is providedprovided directly at the output pins of the power stage on both the SD and OTW outputs.Level compliancebut only on the speaker terminals (after the for 5-V logic can be obtained by adding externaldemodulation filter).It is required to follow certain pullup resistors to 5V (see the Electricalguidelines when selecting the OC threshold and an Characteristics section of this data sheet for furtherappropriate demodulation inductor.specifications).•For the lowest-cost bill of materials in terms of component selection,the OC threshold current should be limited,considering the power output The TAS5186A contains advanced protection circuitryrequirement and minimum load impedance.carefully designed to facilitate system integration andHigher-impedance loads require a lower OC ease of use,as well as safeguarding the device fromthreshold.permanent failure due to a wide range of fault•The demodulation filter inductor must retain at conditions such as short circuit,overload,andleast 5µH of inductance at twice the OC undervoltage.The TAS5186A responds to a fault bythreshold setting.immediately setting the power stage in ahigh-impedance state (Hi-Z)and asserting the SD pinMost inductors have decreasing inductance with low.In situations other than overload,the deviceincreasing temperature and increasing current automatically recovers when the fault condition has(saturation).To some degree,an increase in been removed,e.g.,the supply voltage has increasedtemperature naturally occurs when operating at high or the temperature has dropped.For highest possibleoutput currents,due to inductor core losses and the reliability,recovering from an overload fault requiresdc resistance of the inductor copper winding.A external reset of the device no sooner than 1secondthorough analysis of inductor saturation and thermal after the shutdown (see the Device Reset section ofproperties is strongly recommended.this data sheet).Setting the OC threshold too low might cause issuessuch as lack of output power and/or unexpectedshutdowns due to sensitive overload detection.CURRENT LIMITING AND OVERLOAD DETECTION In general,it is recommended to follow closely theexternal component selection and PCB layout asThe device has independent,fast-reacting currentgiven in the application section.detectors with programmable trip threshold (OCthreshold)on all high-side and low-side power-stageFETs.See the following table for OC-adjust resistorvalues.The detector outputs are closely monitored by Overtemperature ProtectionUNDERVOLTAGE PROTECTION (UVP)AND DEVICE RESET ACTIVE-BIAS CONTROL (ABC)TAS5186ASLES156–OCTOBER 2005element in the audio path,i.e.,split-cap capacitors or series capacitor,to the desired potential before The TAS5186A has a two-levelswitching is started on the PWM outputs.(For temperature-protection system that asserts anrecommended configuration,see the typical active-low warning signal (OTW)when the deviceapplication schematic included in this data sheet).junction temperature exceeds 125°C (typical),and Ifthe device junction temperature exceeds 155°CThe start-up sequence can be controlled through (typical),the device is put into thermal shutdown,sequencing the M3and RESET pins according to resulting in all half-bridge outputs being set in theTable 2and Table 3.high-impedance state (Hi-Z)and SD being assertedlow.Table 2.5.1Mode—All Output Channels ActiveM3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_FPOWER-ON RESET (POR)00Hi-Z Hi-Z Hi-Z All outputsdisabled,The UVP and POR circuits of the TAS5186A fully nothing isprotect the device in any power-up/down and switching.brownout situation.While powering up,the POR 10Active Hi-Z Hi-Z OUT_BIAScircuit resets the overload circuit (OLP)and ensures enabled,allthat all circuits are fully operational when the other outputsdisabledGVDD_X and VDD supply voltages reach 10V (typical).Although GVDD_X and VDD are 11Hi-Z Active Active OUT_BIASdisabled,allindependently monitored,a supply voltage drop other outputsbelow the UVP threshold on any VDD or GVDD_Xswitching pin results in all half-bridge outputs immediately beingset in the high-impedance (Hi-Z)state and SD beingTable 3.2.1Mode—Only Output Channels A,B,asserted low.The device automatically resumesand C Active operation when all supply voltages have increasedabove the UVP threshold.M3RESET OUT_BIAS OUT_A,OUT_D,COMMENT _B,_C _E,_F00Hi-Z Hi-Z Hi-Z All outputsdisabled,When RESET is asserted low,the output FETs in all nothing ishalf-bridges are forced into a high-impedance (Hi-Z)switching.state.10Active Hi-Z Hi-Z OUT_BIASenabled,allAsserting the RESET input low removes any fault other outputsinformation to be signaled on the SD output,i.e.,SD disabledis forced high.01Hi-Z Active Hi-ZOUT_BIASdisabled,allA rising-edge transition on the RESET input allows other outputsthe device to resume operation after an overloadswitching fault.When the TAS5186A is used with the TAS5086PWM modulator,no special attention to start-up sequencing is required,provided that the chipset is configured as Audible pop noises are often associated withrecommended.single-rail,single-ended power stages at power-up orat the start of switching.This commonly knownproblem has been virtually eliminated byincorporating a proprietary active-bias control circuitryas part of the TAS5186A feature set.By the use ofonly a few passive external components (typicallyresistors),the ABC can pre-charge the dc-blocking。