74VHC00 — Quad 2-Input NAND GateQuad 2-Input NAND GateFeatures■ High Speed: t PD = 3.7ns (typ.) at T A = 25°C ■ High noise immunity: V NIH = V NIL = 28% V CC (min.) ■ Power down protection is provided on all inputs ■ Low noise: V OLP = 0.8V (max)■ Low power dissipation: I CC = 2µA (max.) at T A = 25°C ■ Pin and function compatible with 74HC00General DescriptionThe VHC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technol-ogy. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is com-posed of 3 stages, including buffer output, which provide high noise immunity and stable output. An input protec-tion circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.Ordering InformationDevice also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.All packages are lead free per JEDEC: J-STD-020B standard.Order NumberPackage NumberPackage Description74VHC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow74VHC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC00MTC MTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74VHC00NN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide元器件交易网Pin DescriptionTruth Table Pin Names DescriptionA n,B n Inputs O n Outputs A B O L L H L H H H L H H H L元器件交易网74VHC00 — Quad 2-Input NAND Gate74VHC00 — Quad 2-Input NAND GateRecommended Operating Conditions (1)The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Note:1.Unused inputs must be held HIGH or LOW. They may not float.V CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5VI IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±50mAT STG Storage Temperature–65°C to +150°CT LLead Temperature (Soldering, 10 seconds)260°CSymbol ParameterRatingV CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CCT OPR Operating Temperature –40°C to +85°C t r , t fInput Rise and Fall Time, V CC = 3.3V ± 0.3V V CC = 5.0V ± 0.5V0ns/V ∼ 100ns/V 0ns/V ∼20ns/V元器件交易网74VHC00 — Quad 2-Input NAND GateNoise CharacteristicsNote:2.Parameter guaranteed by design.Voltage3.0–5.50.7 x V CC0.7 x V CCV IL LOW Level Input Voltage 2.00.500.50V3.0–5.50.3 x V CC0.3 x V CCV OHHIGH Level Output Voltage2.0V IN = V IH or V ILI OH = –50µA 1.9 2.0 1.9V 3.0 2.9 3.0 2.94.5 4.4 4.54.43.0I OH = –4mA 2.58 2.484.5I OH = –8mA3.943.80V OLLOW Level Output Voltage2.0V IN = V IH or V ILI OL = 50µA 0.00.10.1V3.00.00.10.14.50.00.10.13.0I OL = 4mA 0.360.444.5I OL = 8mA0.360.44I IN Input Leakage Current 0–5.5V IN = 5.5V or GND ±0.1±1.0µA I CCQuiescent Supply Current5.5V IN = V CC or GND2.020.0µASymbolParameterV CC (V)ConditionsT A = 25°CUnitsTyp.LimitsV OLP (2) Quiet Output Maximum Dynamic V OL5.0C L = 50pF 0.30.8V V OLV (2) Quiet Output Minimum Dynamic V OL5.0C L = 50pF –0.3–0.8V V IHD (2) Minimum HIGH Level Dynamic Input Voltage 5.0C L = 50pF 3.5V V ILD (2)Maximum LOW Level Dynamic Input Voltage5.0C L =50pF1.5V元器件交易网74VHC00 — Quad 2-Input NAND GateNote:3.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (opr.) = C PD • V CC • f IN + I CC / 4 (per gate).C L = 50pF 8.011.4 1.013.05.0 ± 0.5C L = 15pF 3.7 5.5 1.0 6.5ns C L = 50pF 5.27.5 1.08.5C IN Input Capacitance V CC = Open41010pF C PDPower Dissipation Capacitance(3)19pF元器件交易网Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or LAND PATTERN RECOMMENDATIONNOTES:UNLESS OTHERWISE SPECIFIEDA)THIS PACKAGE CONFORMS TO JEDECMS-012,VARIATION AB,ISSUE C,B)ALL DIMENSIONS ARE IN MILLIMETERS.C)DIMENSIONS DO NOT INCLUDE MOLDFLASH OR BURRS.D)LANDPATTERN STANDARD:SOIC127P600X145-14ME)DRAWING CONFORMS TO ASME Y14.5M-1994F)DRAWING FILE NAME:M14AREV13INDICATOR8°0°SEATING PLANEDETAIL ASCALE:20:1GAGE PLANE 0.25X 45°0.10C CB C AMSEE DETAIL A(0.33)1.270.510.351.75MAX1.501.250.250.100.250.19(1.04)0.900.500.36R0.10R0.100.500.25Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orFigure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.C.DIMENSIONS ARE EXCLUSIVE OF BURRS,MOLD FLASH,AND TIE BAR EXTRUSIONSF.DRAWING FILE NAME:MTC14REV6R0.09min12.00°TOP&BOTTOM1.00D.DIMENSIONING AND TOLERANCES PER ANSI Y14.5M,1982R0.09minNDPATTERN STANDARD:SOP65P640X110-14M 6.100.45A.CONFORMS TO JEDEC REGISTRATION MO-153,VARIATION AB,REF NOTE 6B.DIMENSIONS ARE IN MILLIMETERSFigure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.NOTES:UNLESS OTHERWISE SPECIFIEDA)THIS PACKAGE CONFORMS TO JEDEC MS-001VARIATION BAB)ALL DIMENSIONS ARE IN MILLIMETERS.C)DIMENSIONS ARE EXCLUSIVE OF BURRS,MOLD FLASH,AND TIE BAR EXTRUSIONS.D)DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994E)DRAWING FILE NAME:MKT-N14AREV78.127.620.350.203.563.305.33MAX 0.38MIN1.771.140.580.352.543.813.178.82(1.74)subsidiaries,and is not intended to be an exhaustive list of all such trademarks.ACEx ®Build it Now ™CorePLUS ™CROSSVOLT ™CTL™Current Transfer Logic™EcoSPARK ®EZSWITCH™*™®Fairchild®Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore ™FlashWriter ®*FPS ™FRFET ®Global Power Resource SM Green FPS ™Green FPS ™e-Series ™GTO ™i-Lo ™IntelliMAX ™ISOPLANAR ™MegaBuck™MICROCOUPLER ™MicroFET ™MicroPak ™MillerDrive™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®PDP-SPM™Power220®Power247®POWEREDGE ®Power-SPM ™PowerTrench ®Programmable Active Droop ™QFET ®QS ™QT Optoelectronics ™Quiet Series ™RapidConfigure ™SMART START ™SPM ®STEALTH™SuperFET ™SuperSOT ™-3SuperSOT ™-6SuperSOT ™-8SyncFET™®The Power Franchise ®TinyBoost ™TinyBuck ™TinyLogic ®TINYOPTO ™TinyPower ™TinyPWM ™TinyWire ™µSerDes ™UHC ®Ultra FRFET ™UniFET ™VCX ™*EZSWITCH™and FlashWriter ®are trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body or (b)support or sustain life,and (c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status DefinitionAdvance InformationForm First Productionative or In DesignThis datasheet contains the design specifications for productdevelopment.Specifications may change in any manner without notice.PreliminaryThis datasheet contains preliminary data;supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.74VHC00 — Quad 2-Input NAND Gate。
