计算机组成原理作业
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《计算机组成原理》大作业学号:_________________ 班级:_________________ 姓名:_________________摘要输入两个数,取出,先后经过总线到达运算器,运算结果再从运算器经过总线到达存储器,整个过程由微程序控制,并达到自动控制。
目录摘要 (1)总体设计 (3)原理图 (5)管脚分配 (6)微程序设计 (7)一、总体设计根据冯一诺伊曼计算机体系的基本思想,计算机硬件系统由运算器,控制器,存储器,输入设备和输出设备组成。
它采用存储程序的方式,程序和数据放在同一个存储器中,指令和数据一样可以送到运算器运算,即由指令组成的程序是可以修改的。
同时,数据以二进制码表示,指令由操作码和地址码组成。
指令在存储器中按执行顺序存放,由指令计数器指明要执行的指令所在的单元地址。
机器以运算器为中心,输入输出设备与存储器间的数据传送都是通过运算器。
这个程序的过程是:从两个reg_74244中先后输入、取出两个数经过总线,分别到达两个寄存器reg_74373。
再由两个寄存器到达运算器alu_74181,在运算器里经过运算得出结果,结果再由总线传输进入存储器mem_256x8、three_state_buf,经data_out输出,或由总线输出。
整个过程由微程序控制。
鉴于运算器为四位,为统一位数,故将原八位的reg_74244,reg_74373,以及data_bus由微程序控制由8位改为四位,而romc则由原来的四位输出改为二十位,即:s0、 s1、s2、s3、oen1、oen2、cs、we、out1、gwe1、gwe2、oen_n1、M、s00、s01、s02、s03、we1、we2、we3。
根据微程序控制,二的五次方大于二十,故需要五位输入,即s0、s1、s2、s3、s4。
书写控制代码,发现romc四位输入控制即可,但未防止调试过程中出现考虑不周等问题,将仍采用五位输入,绘制原理图时将s4放开。
当它们分别在相同时刻有效或无效时,表示一条微指令,则在不同时刻有不同微指令,而这些微指令则组成了实现程序过程的指令,从而实现程序。
为了省去人工输入的麻烦,将使用计数器,自身数据跳动控制,节省人力和时间。
二、原理图三、管脚分配###------------CLOCK-----------NET "clk" LOC = "L15";####-------------Atlys led output-------------------#NET "atlys_led[0]" LOC = U18; #Atlys LD0#NET "atlys_led[1]" LOC = M14; #Atlys LD1#NET "atlys_led[2]" LOC = N14; #Atlys LD2#NET "atlys_led[3]" LOC = L14; #Atlys LD3#NET "atlys_led[4]" LOC = M13; #Atlys LD4#NET "atlys_led[5]" LOC = D4; #Atlys LD5#NET "atlys_led[6]" LOC = P16; #Atlys LD6#NET "atlys_led[7]" LOC = N12; #Atlys LD7####-----------Atlys Switch input-------------------#NET "atlys_sw[0]" LOC = A10; # Atlys sw0#NET "atlys_sw[1]" LOC = D14; # Atlys sw1#NET "atlys_sw[2]" LOC = C14; # Atlys sw2#NET "atlys_sw[3]" LOC = P15; # Atlys sw3#NET "atlys_sw[4]" LOC = P12; # Atlys sw4#NET "atlys_sw[5]" LOC = R5; # Atlys sw5#NET "atlys_sw[6]" LOC = T5; # Atlys sw6#NET "atlys_sw[7]" LOC = E4; # Atlys sw7####------------EES261 switch input----------#NET "swt[19]" LOC = "U11"; #SW20#NET "swt[18]" LOC = "R10"; #SW19#NET "swt[17]" LOC = "U10"; #SW18#NET "swt[16]" LOC = "R8"; #SW17#NET "Address[3]" LOC = "M8"; #SW16NET "Address[2]" LOC = "U8"; #SW15NET "Address[1]" LOC = "U7"; #SW14NET "Address[0]" LOC = "N7"; #SW13#NET "Din2[3]" LOC = "T6"; #SW12NET "Din2[2]" LOC = "R7"; #SW11NET "Din2[1]" LOC = "N6"; #SW10NET "Din2[0]" LOC = "U5"; #SW9#NET "Din1[3]" LOC = "V5"; #SW8NET "Din1[2]" LOC = "P7"; #SW7NET "Din1[1]" LOC = "T7"; #SW6NET "Din1[0]" LOC = "V6"; #SW5#NET "C_n" LOC = "P8"; #SW4#NET "swt[2]" LOC = "V7"; #SW3NET "CE" LOC = "V8"; #SW2NET "rst" LOC = "N8"; #SW1###----------EES261 leds output------------ NET "data_out[0]" LOC = "U16"; #LED1 NET "data_out[1]" LOC = "U15"; #LED2 NET "data_out[2]" LOC = "U13"; #LED3 NET "data_out[3]" LOC = "M11"; #LED4#NET "led<4>" LOC = "R11"; #LED5#NET "led<5>" LOC = "T12"; #LED6#NET "led<6>" LOC = "N10"; #LED7NET "C_n_plus4" LOC = "M10"; #LED8####-------hex7seg-------------------# NET "an<0>" LOC = "V16";# NET "an<1>" LOC = "V15";# NET "an<2>" LOC = "V13";# NET "an<3>" LOC = "N11";## NET "a_to_g<0>" LOC = "T8"; #a# NET "a_to_g<1>" LOC = "V10"; #b# NET "a_to_g<2>" LOC = "T10"; #c# NET "a_to_g<3>" LOC = "V11"; #d# NET "a_to_g<4>" LOC = "N9"; #e# NET "a_to_g<5>" LOC = "P11"; #f# NET "a_to_g<6>" LOC = "V12"; #g# NET "dp" LOC = "T11"; #dp###--------------END----------四、微程序设计library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all; entity romc isPort ( s0 : in STD_LOGIC;s1 : in STD_LOGIC;s2 : in STD_LOGIC;s3 : in STD_LOGIC;oen1 : out STD_LOGIC; oen2 : out STD_LOGIC; cs : out STD_LOGIC; we : out STD_LOGIC;out1 : out STD_LOGIC;gwe1 : out STD_LOGIC;gwe2 : out STD_LOGIC;oen_n1 : out STD_LOGICoen_n2 : out STD_LOGIC;M : out STD_LOGIC;s00 : out STD_LOGIC;s01 : out STD_LOGIC;s02 : out STD_LOGIC;s03 : out STD_LOGIC;we1 : out STD_LOGIC;we2 : out STD_LOGIC;we3 : out STD_LOGIC);end romc;architecture Behavioral of romc is signal addr :std_logic_vector(3 downto 0);--inputsignal rdata :std_logic_vector(16 downto 0); --outputbeginaddr <= s3 & s2 & s1 & s0 ;process(addr)begincase (addr) iswhen "0000" => rdata <= "01000001110111000";when "0001" => rdata <= "01000110110111100";when "0010" => rdata <= "01000010110111100";when "0011" => rdata <= "10000011110111010";when "0100" => rdata <= "10000010110111010";when "0101" => rdata <= "11000010110111000";when "0110" => rdata <= "11110000010111001";when others => rdata <= "00000000010111000";end case;end process;oen1 <= rdata(0);oen2 <= rdata(1);cs <= rdata(2);we <= rdata(3);out1 <= rdata(4);gwe1 <= rdata(5);gwe2 <= rdata(6);oen_n1 <= rdata(7);oen_n2 <= rdata(8);M <= rdata(9);s00 <= rdata(10);s01 <= rdata(11);s02 <= rdata(12);s03 <= rdata(13);we1 <= rdata(14);we2 <= rdata(15);we3 <= rdata(16);end Behavioral;。