AD0809应用原理－－很全面的资料1. 0809的芯片说明：ADC0809是带有8位A/D转换器、8路多路开关以及微处理机兼容的控制逻辑的CMOS 组件。
它是逐次逼近式A/D转换器，可以和单片机直接接口。
（1）ADC0809的内部逻辑结构由上图可知，ADC0809由一个8路模拟开关、一个地址锁存与译码器、一个A/D转换器和一个三态输出锁存器组成。
多路开关可选通8个模拟通道，允许8路模拟量分时输入，共用A/D转换器进行转换。
三态输出锁器用于锁存A/D转换完的数字量，当O E端为高电平时，才可以从三态输出锁存器取走转换完的数据。
（2）．引脚结构IN0－IN7：8条模拟量输入通道如下图所示，从ADC0809的通道IN3输入0－5V之间的模拟量，通过ADC0809转换成数字量在数码管上以十进制形成显示出来。
ADC0809的VREF接＋5V电压。
4．电路原理图5.程序设计：（1）．进行A/D转换时，采用查询EOC的标志信号来检测A/D转换是否完毕，若完毕则把数据通过P0端口读入，经过数据处理之后在数码管上显示。
（2）．进行A/D转换之前，要启动转换的方法：ABC＝110选择第三通道ST＝0，ST＝1，ST＝0产生启动转换的正脉冲信号 .（3）. 关于0809的计算：ad0809是根据逐位逼近的方法产生数据的。
参考电压为0-5V的话。
以0809八位255的转换精度每一位的电压值为(5-0)/255≈0. 0196V设输入电压为X则：X-27*0.0196>=0则AD7=1否则AD7=0。
X-26*0.0196>=0则AD6=1否则AD6=0。
X-20*0.0196>=0则AD0=1否则AD0=0。
（27指2的7次方。
26-------20同理）若参考电压为0-1V(1-0)/255≈0.0039V精度自然高了。
可测量范围小了。
1）汇编源程序：CH EQU 30HDPCNT EQU 31HDPBUF EQU 33HGDATA EQU 32HST BIT P3.0精品文档OE BIT P3.1EOC BIT P3.2ORG 00HLJMP STARTORG 0BHLJMP T0XORG 30HSTART: MOV CH,#0BCHMOV DPCNT,#00HMOV R1,#DPCNTMOV R7,#5MOV A,#10MOV R0,#DPBUFLOP: MOV @R0,AINC R0DJNZ R7,LOPMOV @R0,#00HINC R0MOV @R0,#00HINC R0MOV @R0,#00HMOV TMOD,#01HMOV TH0,#(65536-4000)/256MOV TL0,#(65536-4000) MOD 256SETB TR0SETB ET0SETB EAWT: CLR STSETB STCLR STWAIT: JNB EOC,WAITSETB OEMOV GDATA,P0CLR OEMOV A,GDATAMOV B,#100DIV ABMOV 33H,AMOV A,BMOV B,#10DIV ABMOV 34H,AMOV 35H,BSJMP WTT0X: NOPMOV TH0,#(65536-4000)/256MOV TL0,#(65536-4000) MOD 256MOV DPTR,#DPCDMOV A,DPCNTADD A,#DPBUFMOV R0,AMOV A,@R0MOVC A,@A+DPTRMOV P1,AMOV DPTR,#DPBTMOV A,DPCNTMOVC A,@A+DPTRMOV P2,AINC DPCNTMOV A,DPCNTCJNE A,#8,NEXTMOV DPCNT,#00HNEXT: RETIDPCD: DB 3FH,06H,5BH,4FH,66HDB 6DH,7DH,07H,7FH,6FH,00HDPBT: DB 0FEH,0FDH,0FBH,0F7HDB 0EFH,0DFH,0BFH,07FHEND2）C语言源程序#includeunsigned char code dispbitcode[]={0xfe,0xfd,0xfb,0xf7, 0xef,0xdf,0xbf,0x7f};unsigned char code dispcode[]={0x3f,0x06,0x5b,0x4f,0x66, 0x6d,0x7d,0x07,0x7f,0x6f,0x00};unsigned char dispbuf[8]={10,10,10,10,10,0,0,0}; unsigned char dispcount;sbit ST="P3"^0;sbit OE="P3"^1;sbit EOC="P3"^2;unsigned char channel="0xbc";//IN3 unsigned char getdata;void main(void){TMOD=0x01;TH0=(65536-4000)/256;TL0=(65536-4000)%256;TR0=1;ET0=1;EA=1;P3=channel;while(1){ST=0;ST=1;ST=0;while(EOC==0);OE=1;getdata=P0;OE=0;dispbuf[2]=getdata/100;getdata=getdata%10;dispbuf[1]=getdata/10;dispbuf[0]=getdata%10;}}void t0(void) interrupt 1 using 0 {TH0=(65536-4000)/256;TL0=(65536-4000)%256;P1=dispcode[dispbuf[dispcount]]; P2=dispbitcode[dispcount]; dispcount++;if(dispcount==8){dispcount=0;}}3）FPGA实现的程序：（verilog）module AD0809(clk, //脉宽（至少100ns）rst_n,EOC, //约100us后EOC变为高电平转换结束START, //启动信号，上升沿有效（至少100ns）OE, //高电平打开三态缓冲器输出转换数据ALE, //高电平有效，选择信道口ADDA,//因为ADDB,ADDC都接地了，这里只有ADDA为变量DATA,// //转换数据DATA_R);output START,OE,ALE,ADDA;input EOC,clk,rst_n;input[7:0] DATA;output[7:0] DATA_R;reg START,OE,ALE,ADDA;reg[7:0] DATA_R;reg[4:0] CS,NS;parameter IDLE=5''b00001,START_H=5''b00010,START_L=5''b00100, CHECK_END=5''b01000,GET_DATA=5''b10000;always @(*)case(CS)IDLE:NS=START_H;START_H:NS=START_L;START_L:NS=CHECK_END;CHECK_END:if(EOC)NS=GET_DATA;elseNS=CHECK_END;GET_DATA:NS=IDLE;default:NS=IDLE;endcasealways @(posedge clk)if(!rst_n)CS<=IDLE;elseCS<=NS;always @(posedge clk)case(NS)IDLE:beginOE<=0;START<=0;ALE<=0;ADDA<=1;endSTART_H:beginOE<=0;START<=1; //产生启动信号ALE<=1;ADDA<=1;//选择信道口IN0 endSTART_L:beginOE<=0;START<=0;ALE<=1;//启动信号脉宽要足够长,在启动的时候ALE要一直有效endCHECK_END:beginOE<=0;START<=0;ALE<=0;endGET_DATA:beginOE<=1; //高电平打开三态缓冲器输出转换数据DATA_R<=DATA;//提取转换数据START<=0;ALE<=0;enddefault:beginOE<=0;START<=0;ALE<=0;ADDA<=0;endendcaseendmodule4）FPGA实现的程序：（VHDL）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY AD0809 ISPORT( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);CLK,EOC: IN STD_LOGIC; CLOCK:IN STD_LOGIC;ALE,START,OE,LOCK0: OUT STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));END AD0809;ARCHITECTURE behav OF AD0809 ISTYPE states IS (st0,st1,st2,st3,st4);SIGNAL current_state,next_state:states:=st0; SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK :STD_LOGIC;SIGNAL CNT1:STD_LOGIC_VECTOR(0 DOWNTO 0); SIGNAL A :INTEGER RANGE 0 TO 1;SIGNAL LOWDATA:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HIGHDATA:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL LOWLED7S:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL HIGHLED7S:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGINLOCK0<=LOCK;PROCESS(REGL)BEGINLOWDATA<=REGL(3 DOWNTO 0);HIGHDATA<=REGL(7 DOWNTO 4);CASE LOWDATA ISWHEN "0000" => LOWLED7S<="0111111";WHEN "0001" => LOWLED7S<="0000110";WHEN "0010" => LOWLED7S<="1011011";WHEN "0011" => LOWLED7S<="1001111";WHEN "0100" => LOWLED7S<="1100110";WHEN "0101" => LOWLED7S<="1101101";WHEN "0110" => LOWLED7S<="1111101";WHEN "0111" => LOWLED7S<="0000111";WHEN "1000" => LOWLED7S<="1111111";WHEN "1001" => LOWLED7S<="1101111";WHEN "1010" => LOWLED7S<="1110111";WHEN "1011" => LOWLED7S<="1111100";WHEN "1100" => LOWLED7S<="0111001";WHEN "1101" => LOWLED7S<="1011110";WHEN "1110" => LOWLED7S<="1111001";WHEN "1111" => LOWLED7S<="1110001";WHEN OTHERS => Null;END CASE;CASE HIGHDATA ISWHEN "0000" => HIGHLED7S<="0111111";WHEN "0001" => HIGHLED7S<="0000110";WHEN "0010" => HIGHLED7S<="1011011";WHEN "0011" => HIGHLED7S<="1001111";WHEN "0100" => HIGHLED7S<="1100110";WHEN "0101" => HIGHLED7S<="1101101";WHEN "0110" => HIGHLED7S<="1111101";WHEN "0111" => HIGHLED7S<="0000111";WHEN "1000" => HIGHLED7S<="1111111";WHEN "1001" => HIGHLED7S<="1101111";WHEN "1010" => HIGHLED7S<="1110111";WHEN "1011" => HIGHLED7S<="1111100";WHEN "1100" => HIGHLED7S<="0111001";WHEN "1101" => HIGHLED7S<="1011110";WHEN "1110" => HIGHLED7S<="1111001";WHEN "1111" => HIGHLED7S<="1110001";WHEN OTHERS => Null;END CASE;END PROCESS;PROCESS(CLOCK)BEGINIF CLOCK'EVENT AND CLOCK='1' THEN CNT1<=CNT1+1; END IF;END PROCESS;PROCESS(CNT1)BEGINCASE CNT1 ISWHEN "0" =>SEL<="111"; A<=0;WHEN "1" =>SEL<="110";A<=1;WHEN OTHERS =>NULL;END CASE;END PROCESS;PROCESS(A)BEGINCASE A ISWHEN 0 =>DOUT<=LOWLED7S;WHEN 1 =>DOUT<=HIGHLED7S;WHEN OTHERS =>NULL;END CASE;END PROCESS;COM:PROCESS(current_state,EOC)BEGINCASE current_state ISWHEN st0=>ALE<='0';START<='0';LOCK<='1';OE<='0';next_state<=st 1;WHEN st1=>ALE<='1';START<='0';LOCK<='1';OE<='0';next_state<=st 2;WHEN st2=>ALE<='0';START<='1';LOCK<='0';OE<='0';IF (EOC='1') THEN next_state<=st3;ELSE next_state<=st2;END IF;WHEN st3=>ALE<='0';START<='0';LOCK<='0';OE<='1';next_state<=st 4;WHEN st4=>ALE<='0';START<='0';LOCK<='1';OE<='1';next_state<=st 0;WHEN OTHERS=>next_state<=st0;END CASE;END PROCESS COM;REG: PROCESS(CLK)BEGINIF(CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF;END PROCESS REG;LATCH1: PROCESS(LOCK)BEGINIF LOCK='1' AND LOCK'EVENT THEN REGL<=D;END IF;END PROCESS LATCH1;END behav;。
