计算机组织与系统结构 (A-1 卷)

考试科目名称 计算机组织与系统结构 （A卷）2008——2009学年第 2 学期 教师 袁春风/窦万春考试方式：闭卷系（专业） 计算机科学与技术年级 2007班级学号 姓名 成绩题号一二三四五六分数一、填空题（本大题共10小题，每空1分，共20分）得分1. 在计算机系统层次结构中，指令集体系结构（或ISA，或指令系统）处于硬件和软件交界面，硬件所有功能由它集中体现，软件通过它在硬件上执行。

2. 任何高级语言源程序或汇编语言源程序都必须翻译成机器代码才能在硬件上执行。

完成这种翻译转换任务的程序有汇编程序、解释程序（或解释器）和编译程序（或编译器）三类。

3. 响应时间和吞吐率（或带宽，或数据传输率）是衡量一个计算机系统好坏的两个基本性能。

不同应用场合，用户关心的性能不同。

例如，对于银行、证券等事务处理系统来说，事务处理用户主要关心的是响应时间。

4. 一个变量在计算机内部用0或1编码表示的数被称为机器数，变量真正的值被称为真值。

5. 假定某变量x存放在寄存器R1中为1111 1111 1111 1111 1111 1011 1100 0000B，则变量x在屏幕上用16进制显示为0x FFFFFBC0 。

若x的类型为int，则x的值为 -1088；对R1进行算术左移4位后的值在屏幕上显示为0x FFFFBC00 ；对R1算术右移4位后为0x FFFFFFBC ；对R1逻辑右移4位后为0x 0FFFFFBC 。

6. 与硬连线路控制器相比，微程序控制器的缺点是速度慢。

7. 假定某计算机采用小端方式，按字节编址。

若某变量x的主存地址为00001000H，其数据类型为float，已知x=-1.5，则主存地址00001000H和00001003H中存放的内容分别是00 H和BF H。

8. 可以用一个特殊的Cache来记录最近使用页的页表项，因为页表项主要用于地址转换，所以把这种特殊的Cache称为转换后援缓冲器，简称TLB （或快表）。

《计算机组成与系统结构》课程考试试卷( A 卷) 本试卷适用专业 ：计科、网络、物联、软工 年级 ： 考试时间：110分钟 考试方式： 闭卷 一、 单项选择题（每小题1分，共10分） 1．用于直接给出内存地址寻找内存中操作数的寻址方式称为______寻址。

A. 直接 B. 间接 C. 寄存器直接 D. 寄存器间接 2．______可区分存储单元中存放的是指令还是数据。

A ．用户 B ．运算器 C ．存储器 D ．控制器 3．系统总线中地址线的功用是 。

A. 用于指定主存单元和I/O 设备接口电路的地址 B. 用于传送主存物理地址和逻辑地址 C. 用于选择进行信息传输的设备 D. 用于选择主存单元 4．某计算机字长是16位，它的存储容量是512KB ，按字编址，它的寻址范围是______。

A ．128K ；B ．256K ；C ．256KB ；D ．128KB 。

5．在小数定点机中，下述第______种说法是正确的。

A ．原码和反码不能表示 -1，补码可以表示 -1 B ．三种机器数均可表示 -1 C ．三种机器数均可表示 -1，且三种机器数的表示范围相同 D ．三种机器数均不可表示 -1 6．相对寻址方式中，操作数的有效地址是______。

A ．基址寄存器内容加上形式地址（位移量） B ．程序计数器内容加上形式地址 C ．变址寄存器内容加上形式地址 D ．以上都不对 7．一个节拍信号的宽度是指______。

A ．存储周期 B ．时钟周期 C ．机器周期 D ．指令周期 8．将微程序存储在EPROM 中的控制器是______控制器。

A ．硬布线 B ．毫微程序 C ．静态微程序 D ．动态微程序 9．地址总线的宽度由总线的 定义。

A. 功能特性B. 电气特性C. 物理特性D. 时间特性10．三种集中式总线控制中，______方式对电路故障最敏感。

A ．以下都不对B ．计数器定时查询C ．独立请求D ．链式查询二 填空题（每小题3分，共15分）1．存储器和CPU 连接时，要完成______的连接、______的连接和______的连接，方能正常工作。

计算机系统结构复习题和重点（附答案）一、单项选择题1．实现汇编语言源程序变换成机器语言目标程序是由（）A．编译程序解释B．编译程序翻译C．汇编程序解释D．汇编程序翻译2．系列机软件必须保证（）A．向前兼容，并向上兼容B．向前兼容，并向下兼容C．向后兼容，力争向上兼容D．向后兼容，力争向下兼容3．浮点数尾数基值r m=8，尾数数值部分长6位，可表示规格化正尾数的个数是（）A．56个B．63个C．64个D．84个4．在IBM370系统中，支持操作系统实现多进程共用公用区管理最有效的指令是（）A．“执行”指令B．“程序调用”指令C．“比较与交换”指令D．“测试与置定”指令5．关于非专用总线三种控制方式中，下列叙述错误．．的是（）A．集中式定时查询，所有部件共用同一条“总线忙”线B．集中式定时查询，所有部件都用同一条“总线请求”线C．集中式独立请求，所有部件都用同一条“总线请求”线D．集中式串行链接，所有部件都用同一条“总线请求”线6．磁盘外部设备适合于连接到（）A．字节多路通道B．数组多路通道或选择通道C．选择通道或字节多路通道D．数组多路通道或字节多路通道7．在Cache存储器中常用的地址映象方式是（）A．全相联映象B．页表法映象C．组相联映象D．段页表映象8．在指令级高度并行的超级处理机中，下列叙述正确的是（）A．超标量处理机利用资源重复，要求高速时钟机制B．超流水线处理机利用资源重复，要求高速时钟机制C．超标量处理着重开发时间并行性，要求高速时钟机制D．超流水线处理机着重开发时间并行性，要求高速时钟机制9．间接二进制n方体网络是一种（）A．多级立方体网络B．多级全排列网络C．单级立方体网络D．多级混洗交换网络10．多端口存储器适合于连接A．紧耦合多处理机B．松耦合多处理机C．机数很多的处理机D．机数可变的多处理机二、填空题11．多处理机实现的是___________、___________间的并行。

前二章作业1.计算机的四个基本功能（Functions）是什么？2.在计算机的top-level structure view中，四个structural components 是什么？3.谁提出了store-program concept ?你能用汉语简单地描述这个存储程序的概念吗？4.CPU的英文全称是什么？汉语意义是什么？5.ALU的英文全称是什么？汉语意义是什么？6.V on Neumann 的IAS机的五大部件都是什么？7.在第一章中我们认识到的四个结构性部件（第2题）与V on Neumann的IAS机（第6题）中部件有本质差别吗？8.Fundamental Computer Elements 有哪几个？它们与计算机的四个基本功能的关系是什么？9.Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？10.本书的次标题和第二章第二节标题均为“Designing for Performance”,Performance 主要指什么？Performance Balance的（balance）平衡要平衡什么？11.本书作者将他要研究的范围局限在“desktop, workstation , server“中，它们的中文名称是什么？各自的工作范围是什么？Chapter 3Homework1.PC means _________.A. personal computerB. programming controllerC. program counterD. portable computer2. PC holds _______________ .A. address of next instructionB. next instructionC. address of operandD. operand3. At the end of fetch cycle, MAR holds _____.A. address of instructionB. instructionC. address of operandD. operand4. Interrupt process steps are __________.A. suspending , resuming , branching & processingB. branching , suspending , processing & resumingC. suspending , branching , processing & resumingD. processing , branching , resuming & suspending5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .A. 0 to n-1B. 1 to nC. 0 to 2n-1D. 1 to 2n6.The length of the address code is 32 bits, so addressing range (or the range of address) is________________.A. 4GB.from –2G to 2GC.4G-1D. from 1 to 4G7.There are three kinds of BUSes. Which is not belong to them?A. address busB. system busC. data busD. control busQuestions1.Translate the following terms (Note: function)PC, MAR, MBR, IR, AC, bus, system bus, data bus , address bus , control bus , handler*, opcode, Bus arbitrate* , multiplexed bus* , interrupt, ISR, Instruction cycle , fetch cycle , execute cycle (带“*”为选做题)2.Page90 problems3.1What general categories of functions are specified by computer instruction?3. Describe simply the operations of PC and IR in an instruction cycle.4.Suppose the length of word is n-bit, describe simply operand(操作数) format and instruction format.5. Describe simply the procedure of the interruption6. Describe simply the types and functions of the BUS.一：选择题1.The computer memory system refers to _________A.RAMB.ROMC.Main memoryD.Register , main memory, cache, external memory2.If the word of memory is 16 bits, which the following answer is right ?A.The address width is 16 bitsB.The address width is related with 16 bitsC.The address width is not related with 16 bitsD.The address width is not less than 16 bits3.The characteristics of internal memory compared to external memoryA.Big capacity, high speed, low costB.Big capacity, low speed, high costC.small capacity, high speed, high costD.small capacity, high speed, low cost4．On address mapping of cache, any block of main memory can be mapped toany line of cache, it is ___________ .A) Associative Mapping B) Direct MappingC) Set Associative Mapping D) Random Mapping5. Cache’s write-through polity means write operation to main memory _______.A)as well as to cacheB)only when the cache is replacedC)when the difference between cache and main memory is foundD)only when direct mapping is used6.Cache’s writ e-back polity means write operation to main memory ______________.a)as well as to cacheb)only when the relative cache is replacedc)when the difference between cache and main memory is foundd)only when using direct mapping7. On address mapping of cache, the data in any block of main memory can be mapped to fixed line of cache, it is _________________.associative mapping B) direct mappingC)set associative mapping D) random mapping8.On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is _________________.associative mapping B) direct mappingD)set associative mapping D) random mapping二：计算题(from page 126)Problem 4.1 , Problem 4.3 , Problem 4.4 , Problem 4.5 , , Problem 4.7, Problem 4.10第五章作业1.which type of memory is volatile?A.ROMB. E2PROMC. RAMD. flash memory2.which type of memory has 6-transistor structure?A. DRAMB. SRAMC. ROMD. EPROMing hamming code, its purpose is of one-bit error.A. detecting and correctingB. detectingC. correctingD. none of all4.Flash memory is .A. read-only memoryB. read-mostly memoryC. read-write memoryD. volatile5.Which answer about internal memory is not true?A. RAM can be accessed at any time, but data would be lost when power down..B. When accessing RAM, access time is non-relation with storage location.C. In internal memory, data can’t be modified.D. Each addressable location has a unique address.Page161 Problems: 5.4 5.5 5.6 5.7 5.8第六章作业一、选择题1. RAID levels_________make use of an independent access technique.A. 2B. 3C. 4D. all2. In RAID 4, to calculate the new parity, involves _________reads.A. oneB. twoC. threeD.four3. During a read/write operation, the head is ___________A. movingB. stationaryC. rotatingD. above all4. On a movable head system, the time it takes to position the head at the track is know as______.A. seek timeB. rotational delayC. access timeD. transfer time5. RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.A. parityB. user dataC. OSD. anyone6. Recording and retrieval via _________called a headA. conductive coilB. aluminiumC. glassD. Magnetic field7.In Winchester disk track format, _________is a unique identifier or address used to locate a particular sector.A. SYNCHB. GapC. ID fieldD. Data field8. Data are transferred to and from the disk in ________.A. trackB. sectorC. gapD. cylinder9. In _________, each logical strip is mapped to two separate physical disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 410. With _________, the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 411. The write-once read-many CD, known as ________.A. CD-ROMB. CD-RC. CD-R/WD. DVD二、How are data written onto a magnetic disk?三、In the context of RAID, what is the distinction between parallel access and independent access? Homework in Chapter 71.“When the CPU issues a command to the I/O module, it must wait until the I/O operation iscomplete”. It is programmed I/O , the word “wait” means ___________________.a. the CPU stops and does nothingb. the CPU does something elsec. the CPU periodically reads & checks the status of I/O moduled. the CPU wait the Interrupt Request Signal2.See Figure 7.7. To save (PSW & PC) and remainder onto stack, why the operations of restore them isreversed? Because the operations of stack are ________________.a. first in first outb. randomc. last in first outd. sequenceding stack to save PC and remainder, the reason is ____________________ .a.some information needed for resuming the current program at the point of interruptb.when interrupt occurs, the instruction is not executed over, so the instruction at the point ofinterrupt must be executed once againc.the stack must get some information for LIFOd.the start address of ISR must transfer by stack4.The signals of interrupt request and acknowledgement exchange between CPU and requesting I/Omodule. The reason of CPU’s acknowledgement is ________________a.to let the I/O module remove request signalb. to let CPU get the vector from data busc.both a & bd. other aims5.In DMA , the DMA module takes over the operations of data transferring from CPU, it means_________________________a.the DMA module can fetch and execute instructions like CPU doesb.the DMA module can control the bus to transfer data to or from memory using stealing cycletechniquec.the DMA module and CPU work together(co-operate) to transfer data into or from memoryd.when DMA module get ready, it issues interrupt request signal to CPU for getting interruptservice6.Transfer data with I/O modules, 3 types of techniques can be used. Which one is not belong them?a. Interrupt-driven I/Ob. programmed I/Oc. direct I/O accessd. DMA7.Think 2 types of different data transferring, to input a word from keyboard and to output a data blockof some sectors to harddisk. The best choice is to use ___________.a. interrupt-driven I/O and DMAb. DMA and programmed I/O C. both interrupt-driven I/Os d. both DMAsparing with interrupt-driven I/O, DMA further raises the usage rate of CPU operations, because__________a. it isn’t necessary for CPU to save & restore sceneb. it isn’t necessary for CPU to intervene the dada transferc. it isn’t necessary for CPU to read & check status repeatedlyd. both a and b9.Simply script the all actions when using Interrupt-driven I/O technique to transferring data with I/Omodule.(please insert the “vector “at step3 & step5)10.See Figure 7.7 & 7.8. Redraw figure 7.8, and mark the sequence number according to Figure 7.7, toindicate the sequence of the information flowing.11. According to DMA technique, write all information of CPU sending to DMA module, and write at which time the DMA module issues interrupt request signal to CPU and why the INTR is issued ?. Chapter9 homework1.Suppose bit long of two’s complement is 5 bits, which arithmetic operation brings OVERFLOW?A. 5+8B. (-8)+(-8)C. 4-(-12)D.15-72.Overflow occurs sometime in ______arithmetic operation.A. addB. subtractC. add and subtractD. multiply3. In twos complement, two positive integers are added, when does overflow occurs?A. There is a carryB. Sign bit is 1C. There is a carry, and sign bit is 0D. Can’t determine4. An 8-bit twos complement 1001 0011 is changed to a 16-bit that equal to____.A.1000 0000 1001 0011B. 0000 0000 1001 0011C.1111 1111 1001 0011D.1111 1111 0110 1101 115. An 8-bit twos complement 0001 0011 is changed to a 16-bit that equal to____.A. 1000 0000 1001 0011B. 0000 0000 0001 0011C. 1111 1111 0001 0011D. 1111 1111 1110 11016.Booth’s algorithm is us ed for Twos complement ______.A. additionB. subtractionC. multiplicationD. division7. In floating-point arithmetic, addition can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. compare exponent, shift significand, add significands and normalizeC. fetch instruction, indirectly address operand, execute instruction and interruptD. process scheduling states: create, get ready, is running and is blocked8. In floating-point arithmetic, multiplication can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. fetch instruction, indirectly address operand, execute instruction and interruptC. process scheduling states: create, get ready, is running and is blockedD. check for zero, add exponents, multiply significands, normalize, and round.9.The main functions of ALU are?A. LogicB. ArithmeticC. Logic and arithmeticD. Only addition10. Which is true?A. Subtraction can not be finished by adder and complement circuits in ALUB. Carry and overflow are not sameC.In twos complement, the negation of an integer can be formed with the following rules: bitwise not(excluding the sign bit), and add 1.D. In twos complement, addition is normal binary addition, but monitor sign bit for overflowPage326：9.4, 9.5 and 9.7(其中9.4选作)To prove: in twos complement, sign-extension rule (converting between different bit length) and negation rule ( (-X)补= X补+ 1).Chapter 10 and Chapter 111: In instruction, the number of addresses is 0, the operand(s)’address is implied, which is(are) in_______.A. accumulatorB. program counterC. top of stackD. any register2: Which the following addressing mode can achieve the target of branch in program?A.Direct addressing modeB.Register addressing modeC.Base-register addressing modeD.Relative addressing mode （有问题）3: In index-register addressing mode , the address of operand is equal toA.The content of base-register plus displacementB.The content of index-register plus displacementC.The content of program counter plus displacementD.The content of AC plus displacement4: The address of operand is in the instruction, it is_________ ?A.Direct addressing modeB.Register indirect addressing modeC.Stack addressing modeD.Displacement addressing mode5: Which the following is not the area that the source and result operands can be stored in ?A.Main or virtual memoryB.CPU registerC.I/O deviceD.Instruction6: Compared with indirect addressing mode , the advantage of register indirect addressing mode isrge address spaceB.Multiple memory referenceC.Limit address spaceD.Less memory access7:With base-register ADDRESSING , the ______________ register can be used.A. BASEB. INDEXC. PCD. ANY8:The disadvantage of INDIRECT ADDRESSING is ____________.A. large addressing rangeB. no memory accessC. more memory accessD. large value range9:Which is not an advantage with REGISTER INDIRECT?A. just one times of operand’s accessB. large memory spaceC. large value rangeD. no memory reference10:The REGISTER ADDRESSING is very fast, but it has _________________.A. very less value rangeB. very less address spaceC. more memory accessD. very complex address’ calculating11:The disadvantage of IMMEDIATE ADDRESSING is ___________.A. limited address rangeB. more memory accessC. limit value rangeD. less memory access12:In instruction, the number of addresses is 2, one address does double duty both _______________.A. a result and the address of next instructionB.an operand and a resultC.an operand and the address of next instructionD.two closed operands13.In instruction, the number of addresses is 3, which are _______________.A. two operands and one resultB. two operands and an address of next instructionC. one operand, one result and an address of next instructionD. two operands and an address of next instruction14.The address is known as a type of data, because it is represented by __________.A. a number of floating pointB. a signed integerC. an unsigned integerD. a number of hexadecimal15.Which is not a feature of Pentium .A. complex and flex addressingB. abundant instruction setC. simple format and fixed instruction lengthD. strong support to high language16. Which is not a feature of Power PC .A. less and simple addressing modeB. basic and simple instruction setC. variable instruction length and complex formatD. strong support to high languageChapter 12 and Chapter 181. After the information flow of fetch subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand2. After the information flow of instruction subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand3. The worse factor that limits the performance of instruction pipeline is _________________.A.conditional branch delaying the operation of target addressB. the stage number of pipeline can’t exceed 6C. two’s complement arithmetic t oo complexD. general purpose registers too few4.The most factor to affect instruction pipeline effectiveness is __________.A. The number of stagesB. the number of instructionC. the conditional branch instructionD. the number of pipelines5. RISC rejects ______.A. few, simple addressing modesB. a limited and simple instruction setC. few, simple instruction formatsD. a few number of general purpose registers6. RISC rejects ______.A.a large number of general-purpose registersB. indirect addressingC. a single instruction sizeD. a small number of addressing mode7. Which is NOT a characteristic of RISC processor.A. a highly optimized pipeline.B. Register to register operationsC. a large number of general-purpose registersD. a complexed instruction format8.Control unit use some input signals to produce control signals that open the gates of informationpaths and let the micro-operations implement. Which is NOT the input signals of control unit/A.clock and flagsB.instruction registerC.interrupt request signalD.memory read or write9.Control unit use some output signals to cause some operations. Which is not included in the outputsignals?A.signals that cause data movementB.signals that activ ate specific functions(e.g. add/sub/…)C.flagsD.read or write or acknowledgement 10. Symmetric Multi-Processor (SMP) system is tightly coupled by _______.A. high-speed data-link and distributed memoryB. shared RAIDs and high-speed data-linkC. distributed caches and shared memoryD. interconnect network and distributed memory11. The SMP means __________.A.Sharing Memory ProcessesB.Split Memory to PartsD.Stack and Memory Pointer D.Symmetric Multi-Processo r12.The “MESI” means states of ____________ .A.Modified, Exclusive, Stored and InclusiveB.Modified, Expected, Shared and InterruptedC.Modified, Exclusive, Shared and InvalidD.Moved, Exchanged, Shared and Invalid13.The protocol “MESI” is also called __________.A. write back policyB. write-update protocolC. write-invalidate protocolD. write through policyChapter 121.Which register is user –visible but is not directly operated in 8086 ?A. DSB. SPC. IPD. BP2.The indirect sub-cycle is occurred _____________ ?A. before fetch sub-cycleB. after execute sub-cycleC. after interrupt sub-cycleD. after fetch sub-cycle and before execute sub-cycle3.Within indirect sub-cycle , the thing the CPU must do is ______________?A. fetch operand or store resultB. fetch operand’s address from memoryC. fetch next instruction from memoryD. nothing4.In general, which register is used for relative addressing ---- the content in this register plus theA supplied by instruction to make a target address in branch or loop instructions.A. SPB. IRC. BRD. PC5.The Memory Address Register connects to ____________ BUS .A. systemB. addressC. dataD. control6.The Memory Buffer Register links to ________ BUS.A. systemB. addressC. dataD. control7.After Indirect cycle , there is a ______________ cycle .A. FetchB. IndirectC. ExecuteD. Interrupt8.The Interrupt cycle is __________ ______ Execute cycle .A. always afterB. never afterC. sometime afterD. maybe before9.The correct cycle sequence is _________________ .A. Fetch , Indirect , Execute and InterruptB. Fetch , Execute , Indirect and InterruptC. Fetch , Indirect , Interrupt and ExecuteD. Indirect , Fetch , Execute and Interrup10.The aim of the indirect cycle is to get __________________.A. an operandB. an instructionC. an address of an instructionD. an address of an operand11.Which is not in the ALU ?A. shifterB. adderC. complementerD. accumulator12.The registers in the CPU is divided _____registers and ________registers .A. general purpose , user-visibleB. user-visible , control and statusC. data , addressD. general purpose , control and status13.The Base register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control14.The Instruction Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control15.The Index register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control16.The Stack Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control17.The Accumulator is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control18.The Programming Status Word is a(n) __________ register .A. general purposeB. dataC. addressD. controlShow all the micro-operations and control signals for the following instruction:1. ADD AX, X; —The contents of AC adds the contents of location X, result is stored to AC.2. MOV AX, [X];—Operand pointed by the content of location X is moved to AX, that means ((X))->AX—[ ] means indirect addressing.3. ADD AX, [BX];—Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX —[ ] means register indirect addressing.4. JZ NEXT1; —If (ZF)=0,then jump to (PC)+ NEXT1.5. CALL X; —Call x function, save return address on the top of stack.6. RETURN; —From top of stack return to PC.。

计算机系统结构自考真题及答案解析（一）总分：140分题量：55题一、单选题（共39题，共78分）1.IBM370系统将中断的类型分为（）A.3类B.4类C.5类D.6类正确答案：D本题解析：暂无解析2.下列属于总线标准的是（）A.电气B.速率C.流量D.吞吐率正确答案：A本题解析：暂无解析3.为了解决主存的容量满足不了要求，采用的技术是（）A.寄存器B.虚拟存储器C.高速缓存D.控制存储器正确答案：B本题解析：暂无解析4.标量流水处理机的性能指标主要有（）A.吞吐率、加速比、时间延迟B.吞吐率、效率、时间延迟C.吞吐率、加速比、效率D.加速比、效率、时间延迟正确答案：C本题解析：暂无解析5.多处理机属于（）A.SISD系统B.SIMD系统C.MISD系统D.MIMD系统正确答案：D本题解析：暂无解析6.在计算机系统多级层次结构中,机器级从低级到高级，相对顺序正确的是()。

A.汇编语言——操作系统——高级语言B.微程序一传统机器语言一汇编语言C.传统机器语言——高级语言——汇编语言D.汇编语言——应用语言——高级语言正确答案：B本题解析：暂无解析7.下列对系统程序员不透明的是()。

A.Cache存储器B.数据通路宽度C.指令缓冲寄存器D.虚拟存储器正确答案：D本题解析：暂无解析8.下列予寻址方式的三种面向的是()。

A.面向主存B.面向辅存C.面向寄存器D.面向堆栈正确答案：B本题解析：暂无解析9.浮点数尾数的基值rm=-8，尾数的计算机位数m=8位，可表示的尾数的个数为()。

A.23×7B.24×7C.25×7D.26×7正确答案：C本题解析：暂无解析10.IBM370系统中，通道动作故障引起的中断属于()。

A.机器校验中断B.访管中断C.程序性中断D.I/O中断正确答案：A本题解析：暂无解析11.程序员编写程序时使用的地址是()。

A.主存地址B.逻辑地址C.物理地址D.有效地址正确答案：B本题解析：暂无解析12.对指令间“一次重叠”描述不正确的是()。

计算机科学技术：计算机体系结构真题1、问答题简述自上而下的设计方法？答案：从用户的需求出发，先确定应用级虚拟机所具有的基本功能特性,然后逐级向下设计。

对于以下的每一级，都必须考虑使上一级优化实现。

2、填空题根据指令系统功能结构的不同，计算机体系结构发展趋势呈现（）和（）两种截然不同的方向，相同的指令系统可以通过“（）”或“（）”的方法来实现。

答案：复杂指令集计算技术；精简指令集计算技术；微程序控制器；硬布线3、问答题多机系统的耦合度可以分为哪几类？答案：（1）最低耦合：除通过某种中间存储介质之外，各计算机之间没有物理连接，也无共享的联机硬件资源。

（2）松散耦合：通过通道或通信线路实现计算机间互连，共享某些外围设备，机间的相互作用是在文件或数据集一级进行。

（3）紧密耦合：机间物理连接的频带较高，往往通过总线或高速开关实现互连，可以共享主存。

4、问答题在分布式存储器结构的机器中，对应于两种地址空间的组织方案，分别有哪两种通信机制？它们是怎么实现的？答案：（1）共享地址空间的机器：可利用1oad和StOre指令中的地址隐含地进行数据通信，因而可称为共享存储器机器。

（2）多个地址空间的机器：根据简单的网络协议，通过传递消息来请求某些服务或传输数据，从而完成通信。

因而这种机器常称为消息传递机器。

5、问答题请叙述设计一个I/O子系统的步骤。

答案：A、列出将要链接到计算机的I/O设备的类型，或者列出机器将要支持的标准总线。

B、列出每种I/O设备的物理要求，包括：容量、电源、连接器、总线槽、扩展机箱等等。

C、列出每种I/O设备的开销，包括设备所需要的控制器的开销。

D、记录每种I/O设备对CPU资源的要求。

E、列出每种I/O设备对存储器和总线资源的要求。

F、按照不同的方法组织I/O设备，并计算其性能和开销。

6、填空题对于采用预取技术来降低失效率的方法，目的是要使O,预取优化的主要对象是（）。

答案：执行指令和读取数据能重叠执行；循环7、问答题什么是“程序的动态定位方式”？答案：利用类似变址寻址方法，有硬件支持完成。

考试科目名称计算机组织与系统结构（A卷）2010——2011学年第1学期教师袁春风/杨若瑜考试方式：闭卷系（专业）计算机科学与技术年级2009班级学号姓名成绩题号一二三四五分数得分一、选择题（每小题2分，共36分）1.-1022的32位补码用十六进制表示为（ D ）。

A. 0000 03FEHB. 0000 FC02HC. FFFF 03FEHD. FFFF FC02H2.假定变量f的数据类型为float，f=-4.093e3，则变量f的机器数表示为（ B ）。

A. 457FD000HB. C57F D000HC. C5FF D000HD. C67FE800H3.某8位计算机中，假定带符号整数变量x和y的机器数用补码表示，[x]补=F5H，[y]补=7EH，则x–y的值及其相应的溢出标志OF分别是（ D ）。

A. 115、0B. 119、0C. 115、1D. 119、14.考虑以下C语言代码：short si= –8196;int i=si;执行上述程序段后，i的机器数表示为（D）。

A. 0000 9FFCHB. 0000DFFCHC.FFFF 9FFCHD. FFFF DFFCH5.以下几种存储结构中，采用相联存取方式访问信息的是（ C ）。

A.堆栈B.直接映射cacheC.分支历史记录表D.主存页表6.假定用若干个16K×8位的存储器芯片组成一个64K×8位的存储器，按字节编址，芯片内各单元交叉编址，则地址BFFFH所在的芯片的最小地址为（D）。

A. 0000HB. 0001HC. 0002HD. 0003H7.假定主存地址位数为32位，按字节编址，主存和cache之间采用全相联映射方式，主存块大小为一个字，每字32位，采用回写（Write Back）方式和随机替换策略，则能存放32K字数据的cache的总容量至少应有多少位？（ D）A. 1536KB. 1568KC. 2016KD. 2048K8.某计算机按字节编址，采用小端方式存储信息。

南昌航空大学20XX —20XX 学年第一学期期末考试课程名称：操作系统 闭 卷 A 卷 120分钟一、 单项选择题（共60分，每小题2分）1.系统为某进程分配了4个页框，该进程已访问的页号序列为2,0,2,9,3,4,2,8,2,3,8,4,5，若进程要访问的下一页的页号为7，依据LRU 算法，应淘汰页的页号是（B ）。

A ．2B ．3C ．4D ．82. 操作系的I/O 子系统通常由四个层次组成，每一层明确定义了与邻近层次的接口，其合理的层次组织排列顺序是（ A ）。

A. 用户级I/O 软件、设备无关软件、设备驱动程序、中断处理程序B. 用户级I/O 软件、设备无关软件、中断处理程序、设备驱动程序C. 用户级I/O 软件、设备驱动程序、设备无关软件、中断处理程序D. 用户级I/O 软件、中断处理程序、设备无关软件、设备驱动程序 3. 在请求分页系统中，页面分配策略与页面置换策略不能组合使用的是（ A ）。

A ．可变分配，全局置换 B ．可变分配，局部置换C ．固定分配，全局置换D ．固定分配，局部置换4. 某计算机处理器主频为50 MHz ，采用定时查询方式控制设备A 的I/O ，查询程序运行一次所用的时钟周期数至少为500。

在设备A 工作期间，为保证数据不丢失，每秒需对其查询至少200次，则CPU 用于设备A 的I/O 的时间占整个CPU 时间的百分比至少是（ C ）。

A ．0.02%B ．0.05%C ．0.20%D ．0.50%5. 下列选项中，满足短任务优先且不．会发生饥饿现象的调度算法是（ ）。

A ．先来先服务 B ．高响应比优先 C ．时间片轮转D ．非抢占式短任务优先 6. 下列选项中，在用户态执行的是（ A ）。

A ．命令解释程序B ．缺页处理程序C ．进程调度程序D ．时钟中断处理程序 7. 在支持多线程的系统中，进程P 创建的若干个线程不．能共享的是（ D ）。

A ．进程P 的代码段 B ．进程P 中打开的文件 C ．进程P 的全局变量D ．进程P 中某线程的栈指针8．用户程序发出磁盘I/O 请求后，系统的正确处理流程是（ B ）。

2012-2013 1 计算机系统结构A （A 卷）信息科学技术学院 胡乃平 计算机科学与技术 周艳平 （答案写在答题纸上，写在试题纸上无效）一、 选择题（60分，每小题2分）1、下面关于计算机发展趋势的说法，不可能的是____。

A. 计算机的智能程度越来越高，未来可以取代人脑进行思考。

B. 计算机的速度越来越快，每秒可以完成几十亿次基本运算。

C. 计算机的体积越来越小，可以放到口袋里。

D. 计算机的价格越来越便宜。

2、下列属于计算机特点的是_____。

A.计算机的速度快B.具有复杂的逻辑判断能力C.计算机可靠性高D. 能完成任何工作3、若十进制数为132.75，则相应的十六进制数为____。

A 、21.3B 、84.C C 、24.6D 、84.64、关于奇偶校功能的正确描述是____。

A 、均能检测奇数个错B 、均能检测偶数个错C 、奇校验检测奇数个错，偶校验检测偶数个错D 、能检算出奇数个错的个数5、[X]补=X 0.X 1X 2…X n (n 为整数)，它的模是____。

A 、2n-1B 、2nC 、1D 、26、设寄存器位数为8位，机器数补码表示（含1位符号位）。

对应于十进制数-27，寄存器内容为____。

A 、27HB 、9BHC 、E5HD 、C6H7、在下列有关补码和移码关系的叙述中，____是不正确的A 、相同位数的补码和移码表示具有相同数据表示范围B 、零的补码和移码表示相同C 、同一个数的补码和移码表示，其数值部分相同，而符号相反D 、一般用移码表示浮点数的阶，而补码表示定点整数8、存储器是计算机系统的记忆设备，主要用来____。

A 、存放数据B 、存放程序C 、存放数据和程序D 、存放微程序9、在存储器分层体系结构中，存储器容量从最小到最大的排列顺序是____。

A 、寄存器-主存-cache-辅存B 、寄存器-主存-辅存-cache课程考试试题 学期 学年 拟题人:校对人: 拟题学院（系）: 适 用 专 业:C、寄存器-cache-辅存-主存D、寄存器-cache-主存-辅存10、用户程序所放的主存空间属于____。