此文档下载后即可编辑目录1.秒表设计要求 (1)2.设计思路 (1)2.1功能模块 (1)2.1.1分频器 (1)2.1.2计数器 (1)2.1.3数据锁存器 (2)2.1.4控制器 (2)2.1.5扫描显示的控制电路 (2)2.1.6显示电路 (3)2.1.7按键消抖电路 (3)3.电路实现 (4)4.程序仿真 (13)4.1分频器 (13)4.1.1计数器电路综合 (15)4.1.2计数器电路仿真 (15)4.2同步计数器 (17)4.2.1计数器实现 (17)4.2.2计数器仿真 (20)4.2.3同步计数器电路综合 (22)4.3按键消抖电路 (23)4.3.1按键消抖电路实现 (23)4.3.2按键消抖电路仿真 (24)4.3.3按键消抖电路综合 (26)4.4八段译码器 (27)4.4.1八段译码器实现 (27)4.4.2八段译码器仿真 (28)4.4.3八段译码器电路综合 (28)4.5控制器 (30)4.5.1控制器 (30)4.5.1控制器仿真 (31)4.5.3控制器电路综合 (33)5.2View Technology Schematic ： (34)5.3管脚锁定： (35)6.实验结论 (35)1.秒表设计要求（1）秒表的计时范围为00：00：00 ~ 59：59：99。
（2）两个按钮开关Start/Stop和Split/Reset，控制秒表的启动、停止、分段和复位：在秒表已经被复位的情况下，按下“Start/Stop”键，秒表开始计时。
在秒表正常运行的情况下，如果按下“Start/Stop”键，则秒表暂停计时；再次按下该键，秒表继续计时。
在秒表正常运行的情况下，如果按下“Split/Reset”键，显示停止在按键时的时间，但秒表仍然在计时；再次按下该键，秒表恢复正常显示。
在秒表暂停计时的情况下，按下“Split/Reset”键，秒表复位归零。
2.设计思路2.1功能模块2.1.1分频器对晶体振荡器产生的时钟信号进行分频，产生时间基准信号2.1.2计数器对时间基准脉冲进行计数，完成计时功能2.1.3数据锁存器锁存数据使显示保持暂停2.1.4控制器通过产生锁存器的使能信号来控制计数器的运行、停止以及复位设计分析：2.1.5扫描显示的控制电路包括扫描计数器、数据选择器和7段译码器，控制8个数码管以扫描方式显示计时结果，原理图如下：实验电路板上的按键2.1.6显示电路2.1.7按键消抖电路消除按键输入信号抖动的影响，输出单脉冲按键按下时，FPGA 的输入为低电平；松开按键时，FPGA 的输入为高电平但是在按下按键和松开按键的瞬间会出现抖动现象2.2电路框图3.电路实现 ---------------------------------------------------------------------------------- 实验板上的数码管为共阳LED数码管-- Company:-- Engineer:---- Create Date: 09:08:39 03/12/2011-- Design Name:-- Module Name: stopwatch_1 - Behavioral-- Project Name:-- Target Devices:-- Tool versions:-- Description:---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:------------------------------------------------------------------------------------ library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity stopwatch_1 isPort (Clk : in STD_LOGIC;start_stop : in STD_LOGIC;split_reset : in STD_LOGIC;ncs : out STD_LOGIC;s : out STD_LOGIC_VECTOR(2 downto 0);seg : out STD_LOGIC_VECTOR (7 downto 0) );end stopwatch_1;architecture Behavioral of stopwatch_1 issignal k1,k2,k3,k4: STD_LOGIC;signal cnt_1,cnt_2 : STD_LOGIC_VECTOR(1 downto 0);signal start_stop_out,split_reset_out: STD_LOGIC;signal count: STD_LOGIC_VECTOR(15 downto0):=(others=>'0');signal clk_1k: STD_LOGIC;signal z0,z1,z2,z3,z4,z5,z6,q1,q2,q3,q4,q5,q6 :STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');signal count_2: STD_LOGIC_VECTOR(2 downto0 ):=(others=>'0');signal in_7: STD_LOGIC_VECTOR(3 downto 0);signal sreg: STD_LOGIC_VECTOR(2 downto 0):="111";signal snext: STD_LOGIC_VECTOR(2 downto 0);Begin---------------------------------------------------------为三八译码器置入使能信号ncs <= '0';---------------------------------------------------------分频电路process(clk)beginif rising_edge(clk) thenif count = 47999 thencount <=(others=>'0');elsecount <= count+1;end if;end if;end process;clk_1k <= count(15);---------------------------------------------------------同步计数电路process(clk_1k,sreg(2))beginif rising_edge(clk_1k) thenif sreg(2) = '1' thenz0<=(others=>'0');z1<=(others=>'0');z2<=(others=>'0');z3<=(others=>'0');z4<=(others=>'0');z5<=(others=>'0');z6<=(others=>'0');elsif sreg(1) = '1' thenz0 <= z0+1;if z0 = 9 thenz0 <=(others=>'0');z1 <= z1+1;if z1 = 9 thenz1 <=(others=>'0');z2 <= z2+1;if z2 = 9 thenz2 <=(others=>'0');z3 <= z3+1;if z3 = 9 thenz3 <= (others=>'0');z4 <= z4+1;if z4 = 5 thenz4 <= (others=>'0');z5 <= z5+1;if z5 = 9 thenz5 <= (others=>'0');z6 <= z6+1;if z6 = 5 thenz6 <= (others=>'0');end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;---------------------------------------------------------扫描计数器process(clk_1k)beginif rising_edge(clk_1k) thencount_2 <= count_2+1;end if;end process;s <= count_2;---------------------------------------------------------锁存器process(sreg(0),z1,z2,z3,z4,z5,z6)beginif sreg(0) = '1' thenq1 <= z1;q2 <= z2;q3 <= z3;q4 <= z4;q5 <= z5;q6 <= z6;end if;end process;---------------------------------------------------------process(count_2,q1,q2,q3,q4,q5,q6)begincase count_2 iswhen "000" => in_7 <= q1;when "001" => in_7 <= q2;when "011" => in_7 <= q3;when "100" => in_7 <= q4;when "110" => in_7 <= q5;when "111" => in_7 <= q6;when others => in_7 <= "1111";end case;end process;---------------------------------------------------------八段译码器process(in_7)begincase in_7 iswhen "0000" => seg <="00000011";when "0001" => seg <="10011111";when "0010" => seg <="00100101";when "0011" => seg <="00001101";when "0100" => seg <="10011001";when "0101" => seg <="01001001";when "0110" => seg <="01000001";when "0111" => seg <="00011111";when "1000" => seg <="00000001";when "1001" => seg <="00001001";when others => seg <="11111101";end case;end process;---------------------------------------------------------按键去抖电路process(clk_1k,start_stop)beginif clk_1k'event and clk_1k='0' thenif cnt_1 = 3 thenk1 <= '1';elsek1 <= '0';cnt_1 <= cnt_1+1;end if;k2 <= k1;end if;if start_stop = '0' thencnt_1 <= "00";end if;end process;start_stop_out <= not k1 and k2;process(clk_1k,split_reset)beginif clk_1k'event and clk_1k='0' thenif cnt_2 = 3 thenk3 <= '1';elsek3 <= '0';cnt_2 <= cnt_2+1;end if;k4 <= k3;end if;if split_reset = '0' thencnt_2 <= "00";end if;end process;split_reset_out <= not k3 and k4;---------------------------------------------------------控制器process(clk_1k,start_stop_out,split_reset_out)beginif rising_edge(clk_1k) thensreg <= snext;end if;end process;process(start_stop_out,split_reset_out,sreg)begincase sreg iswhen "111" => if start_stop_out = '1' andsplit_reset_out = '0' thensnext <= "011";else snext <= sreg;end if;when "011" => if start_stop_out = '1' andsplit_reset_out = '0' then snext <= "001";elsif start_stop_out = '0' andsplit_reset_out = '1' then snext <= "010";else snext <= sreg;end if;when "001" => if start_stop_out = '0' andsplit_reset_out = '1' then snext <= "111";elsif start_stop_out = '1' andsplit_reset_out = '0' then snext <= "011";else snext <= sreg;end if;when "010" => if start_stop_out = '0' andsplit_reset_out = '1' then snext <= "011";else snext <= sreg;end if;when others => snext <= "111";end case;end process;end Behavioral;注：控制器设计时，巧妙地将状态编码和控制器输出的控制信号编码合二为一，即状态编码也是控制信号编码，使得程序形式上更为简单、清晰。
