256Mb Mobile LPDDR TABLE OF CONTENTS1. GENERAL DESCRIPTION (4)2. FEATURES (4)3. PIN CONFIGURATION (5)3.1 Ball Assignment: LPDDR x16 (5)3.2 Ball Assignment: LPDDR x32 (5)4. PIN DESCRIPTION (6)4.1 Signal Descriptions (6)4.2 Addressing Table (7)5. BLOCK DIAGRAM (8)5.1 Block Diagram (8)5.2 Simplified State Diagram (9)6. FUNCTION DESCRIPTION (10)6.1 Initialization (10)6.1.1 Initialization Flow Diagram (11)6.1.2 Initialization Waveform Sequence (12)6.2 Register Definition (12)6.2.1 Mode Register Set Operation (12)6.2.2 Mode Register Definition (13)6.2.3. Burst Length (13)6.3 Burst Definition (14)6.4 Burst Type (15)6.5 Read Latency (15)6.6 Extended Mode Register Description (15)6.6.1 Extended Mode Register Definition (16)6.7 Status Register Read (16)6.7.1 SRR Register (A[n:0] = 0) (17)6.7.2 Status Register Read Timing Diagram (18)6.8 Partial Array Self Refresh (19)6.9 Automatic Temperature Compensated Self Refresh (19)6.10 Output Drive Strength (19)6.11 Commands (19)6.11.1 Basic Timing Parameters for Commands (19)6.11.2 Truth Table - Commands (20)6.11.3 Truth Table - DM Operations (21)6.11.4 Truth Table - CKE (21)6.11.5 Truth Table - Current State BANKn - Command to BANKn (22)6.11.6 Truth Table - Current State BANKn, Command to BANKn (23)7. OPERATION (24)7.1. Deselect (24)7.2. No Operation (24)7.2.1 NOP Command (25)7.3 Mode Register Set (25)256Mb Mobile LPDDR7.3.1 Mode Register Set Command (25)7.3.2 Mode Register Set Command Timing (26)7.4. Active (26)7.4.1 Active Command (26)7.4.2 Bank Activation Command Cycle (27)7.5. Read (27)7.5.1 Read Command (28)7.5.2 Basic Read Timing Parameters (28)7.5.3 Read Burst Showing CAS Latency (29)7.5.4 Read to Read (29)7.5.5 Consecutive Read Bursts (30)7.5.6 Non-Consecutive Read Bursts (30)7.5.7 Random Read Bursts (31)7.5.8 Read Burst Terminate (31)7.5.9 Read to Write (32)7.5.10 Read to Pre-charge (32)7.6 Write (33)7.6.1 Write Command (34)7.6.2 Basic Write Timing Parameters (34)7.6.3 Write Burst (min. and max. tDQSS) (35)7.6.4 Write to Write (35)7.6.5 Concatenated Write Bursts (36)7.6.6 Non-Consecutive Write Bursts (36)7.6.7 Random Write Cycles (37)7.6.8 Write to Read (37)7.6.9 Non-Interrupting Write to Read (37)7.6.10 Interrupting Write to Read (38)7.6.11 Write to Precharge (38)7.6.12 Non-Interrupting Write to Precharge (38)7.6.13 Interrupting Write to Precharge (39)7.7 Precharge (39)7.7.1 Precharge Command (40)7.8 Auto Precharge (40)7.9 Refresh Requirements (40)7.10 Auto Refresh (40)7.10.1 Auto Refresh Command (41)7.11 Self Referesh (41)7.11.1 Self Refresh Command (42)7.11.2 Auto Refresh Cycles Back-to-Back (42)7.11.3 Self Refresh Entry and Exit (43)7.12 Power Down (43)7.13 Deep Power Down (44)7.13.1 Deep Power-Down Entry and Exit (44)7.14 Clock Stop (45)7.14.1 Clock Stop Mode Entry and Exit (45)8. ELECTRICAL CHARACTERISTIC (46)8.1 Absolute Maximum Ratings (46)8.2 Input/Output Capacitance (46)8.3 Electrical Characteristics and AC/DC Operating Conditions (47)8.3.1 Electrical Characteristics and AC/DC Operating Conditions (47)8.4 IDD Specification Parameters and Test Conditions (48)8.4.1 IDD Specification Parameters and Test Conditions (48)8.5 AC Timings (51)8.5.1 CAS Latency Definition (With CL=3) (54)8.5.2 Output Slew Rate Characteristics (55)8.5.3 AC Overshoot/Undershoot Specification (55)8.5.4 AC Overshoot and Undershoot Definition (55)9. PACKAGE DIMENSIONS (56)9.1: LPDDR X 16 (56)9.2: LPDDR X 32 (57)10. ORDERING INFORMATION (58)11. REVISION HISTORY (59)1. GENERAL DESCRIPTIONW948D6FB / W948D2FB is a high-speed mobile double data rate synchronous dynamic random access memory (LPDDR SDRAM), Using pipelined architecture , An access to the LPDDR SDRAM is burst oriented. Consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the pre-charging time. By setting programmable Mode Registers, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The device supports special power saving functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR).2. FEATURESVDD = 1.7~1.95VVDDQ = 1.7~1.95VData width: x16 / x32Clock rate: 200MHz(-5),166MHz (-6), 133MHz (-75)Partial Array Self-Refresh(PASR)Auto Temperature Compensated Self-Refresh(ATCSR) Power Down ModeDeep Power Down Mode (DPD Mode)Programmable output buffer driver strengthFour internal banks for concurrent operationData mask (DM) for write dataClock Stop capability during idle periodsAuto Pre-charge option for each burst accessDouble data rate for data outputDifferential clock inputs (CK and CK)Bidirectional, data strobe (DQS)CAS Latency: 2 and 3Burst Length: 2, 4, 8 and 16Burst Type: Sequential or Interleave 64 ms Refresh periodInterface: LVCMOSSupport package:Operating Temperature Range3. PIN CONFIGURATION3.1 Ball Assignment: LPDDR x16(Top View) Pin Configuration 3.2 Ball Assignment: LPDDR x32(Top View) Pin Configuration4. PIN DESCRIPTION 4.1 Signal Descriptions4.2 Addressing Table5. BLOCK DIAGRAM 5.1 Block Diagram5.2 Simplified State Diagram6. FUNCTION DESCRIPTION6.1 InitializationLPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other than those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below.The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has been properly initialized from Step 1 through 11.●Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought upsimultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also Assert and hold Clock Enable (CKE) to a LVCMOS logic high level ●Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to applystable clock.●Step 3: There must be at least 200μs of valid clocks before any command may be given to the DRAM. During thistime NOP or DESELECT commands must be issued on the command bus.●Step 4: Issue a PRECHARGE ALL command.●Step 5: Provide NOPs or DESELECT commands for at least tRP time.●Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the initialization sequence there must be two Auto Refresh commands issued.The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.●Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.●Step 8: Provide NOPs or DESELECT commands for at least tMRD time.●Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note theorder of the base and extended mode register programmed is not important.●Step 10: Provide NOP or DESELECT commands for at least tMRD time.●Step 11: The DRAM has been properly initialized and is ready for any valid command.分销商库存信息:WINBONDW948D6FBHX5E W948D2FBJX5E。
1.Product profile1.1General descriptionNPN/NPN resistor-equipped transistors.1.2FeaturesBuilt-in bias resistors Simplifies circuit design Reduces component countReduces pick and place costs1.3ApplicationsLow current peripheral driver Control of IC inputsReplaces general-purpose transistors in digital applications1.4Quick reference dataPEMH20; PUMH20NPN/NPN resistor-equipped transistors; R1 = 2.2 k Ω, R2 = 2.2 k ΩRev. 04 — 15 November 2009Product data sheetTable 1.Product overviewType number Package NPN/PNP complement PNP/PNP complement NXPJEITA PEMH20SOT666-PEMD20PEMB20PUMH20SOT363SC-88PUMD20PUMB20Table 2.Quick reference data Symbol ParameterConditions Min Typ Max Unit V CEO collector-emitter voltage open base--50V I O output current (DC)--100mA R1bias resistor 1 (input) 1.54 2.2 2.86k ΩR2/R1bias resistor ratio0.811.22.Pinning information3.Ordering information4.Marking[1]* = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in ChinaTable 3.PinningPin Description Simplified outlineSymbol1GND (emitter) TR12input (base) TR13output (collector) TR24GND (emitter) TR25input (base) TR26output (collector) TR1001aab555645132sym063Table 4.Ordering informationType number Package NameDescriptionVersion PEMH20-plastic surface mounted package; 6 leads SOT666PUMH20SC-88plastic surface mounted package; 6 leadsSOT363Table 5.Marking codesType numberMarking code [1]PEMH206K PUMH20H7*5.Limiting valuesTable 6.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max UnitPer transistorV CBO collector-base voltage open emitter-50VV CEO collector-emitter voltage open base-50VV EBO emitter-base voltage open collector-10VV I input voltagepositive-+12Vnegative-−10VI O output current (DC)-100mAI CM peak collector current-100mAP tot total power dissipation T amb≤ 25 °CSOT363[1]-200mWSOT666[1][2]-200mW T stg storage temperature−65+150°CT j junction temperature-150°CT amb ambient temperature−65+150°CPer deviceP tot total power dissipation T amb≤ 25 °CSOT363[1]-300mWSOT666[1][2]-300mW[1]Device mounted on a FR4 printed-circuit board, single-sided copper, tin-plated and standard footprint.[2]Reflow soldering is the only recommended soldering method.6.Thermal characteristics[1]Device mounted on a FR4 printed-circuit board, single-sided copper, tin-plated and standard footprint.[2]Reflow soldering is the only recommended soldering method.7.CharacteristicsTable 7.Thermal characteristics Symbol ParameterConditionsMinTypMaxUnitPer transistorR th(j-a)thermal resistance from junction to ambient in free air SOT363[1]--625K/W SOT666[1][2]--625K/WPer device R th(j-a)thermal resistance from junction to ambient in free air SOT363[1]--416K/W SOT666[1][2]--416K/WTable 8.CharacteristicsT amb = 25 °C unless otherwise specified.Symbol ParameterConditions Min Typ Max Unit Per transistorI CBO collector-base cut-off currentV CB = 50 V; I E = 0 A --100nA I CEOcollector-emitter cut-off current V CE = 30 V; I B = 0 A --1μA V CE = 30 V; I B = 0 A; T j =150°C --50μA I EBO emitter-base cut-off current V EB = 5 V; I C = 0 A --2mAh FE DC current gain V CE = 5 V; I C = 20 mA 30--V CEsat collector-emitter saturation voltage I C = 10 mA; I B = 0.5 mA --150mV V I(off)off-state input voltage V CE = 5 V; I C = 1 mA - 1.20.5V V I(on)on-state input voltage V CE = 0.3 V; I C = 20 mA2 1.6-V R1bias resistor1 (input) 1.54 2.2 2.86k ΩR2/R1bias resistor ratio 0.81 1.2C ccollector capacitanceV CB = 10 V; I E = i e = 0 A; f =1MHz -- 2.5pF8.Package outline9.Packing informationTable 9.Packing methodsThe indicated -xxx are the last three digits of the 12NC ordering code.[1]Type number Package Description Packing quantity30004000800010000 PEMH20SOT666 2 mm pitch, 8 mm tape and reel---315-4 mm pitch, 8 mm tape and reel--115--PUMH20SOT363 4 mm pitch, 8 mm tape and reel; T1[2]-115---1354 mm pitch, 8 mm tape and reel; T2[3]-125---165[1]For further information and the availability of packing methods, see Section12.[2]T1: normal taping[3]T2: reverse taping10.Revision historyTable 10.Revision historyDocument ID Release date Data sheet status Change notice SupersedesPEMH20_PUMH20_420091115Product data sheet-PEMH20_PUMH20_3 Modifications:•This data sheet was changed to reflect the new company name NXP Semiconductors,including new legal definitions and disclaimers. No changes were made to the technicalcontent.•Figure 5 “Package outline SOT363 (SC-88)”: updatedPEMH20_PUMH20_320050214Product data sheet-PUMH20_2PUMH20_220040414Product specification-PUMH20_1PUMH20_120031016Product specification--11.Legal information11.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design. [2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL .11.2DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.11.3DisclaimersGeneral — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.Quick reference data — The Quick reference data is an extract of theproduct data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.11.4TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.12.Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheetProductionThis document contains the product specification.13.Contents1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 11.1General description . . . . . . . . . . . . . . . . . . . . . 11.2Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4Quick reference data . . . . . . . . . . . . . . . . . . . . 12Pinning information. . . . . . . . . . . . . . . . . . . . . . 23Ordering information. . . . . . . . . . . . . . . . . . . . . 24Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 36Thermal characteristics . . . . . . . . . . . . . . . . . . 47Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 69Packing information . . . . . . . . . . . . . . . . . . . . . 610Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 711Legal information. . . . . . . . . . . . . . . . . . . . . . . . 811.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 811.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 811.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 812Contact information. . . . . . . . . . . . . . . . . . . . . . 813Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2009.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@分销商库存信息: NXPPUMH20,115。
1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V) –1.8 (V CC = 1.8V to 3.6V)•Internally Organized 16,384 x 8 and 32,768 x 8 •Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•1 MHz (5V), 400 kHz (2.7V , 2.5V) and 100 kHz (1.8V) Compatibility •Write Protect Pin for Hardware and Software Data Protection •64-byte Page Write Mode (Partial Page Writes Allowed) •Self-timed Write Cycle (5 ms Max) •High Reliability–Endurance: One Million Write Cycles –Data Retention: 40 Years•Extended Temperature and Lead-free/Halogen-free Devices Available•8-lead JEDEC PDIP, 8-lead JEDEC and EIAJ SOIC, 8-lead MAP , 8-lead TSSOP , 8-lead SAP and 8-ball dBGA2 Packages•Die Sales: Wafer Form, Waffle Pack, and Bumped WafersDescriptionThe AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8bits each. The device’s cascadable feature allows up to 4 devices to share a common Two-wire bus. The device is optimized for use in many industrial and commercial appli-cations where low power and low voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP (24C128), 8-lead TSSOP , 8-lead SOIC Array Package and 8-ball dBGA2 packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.Table 1. Pin ConfigurationPin NameFunctionA0 - A1Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GNDGround8-lead SAPBottom View8-lead PDIP8-lead SOIC8-ball dBGA2Bottom View8-lead TSSOPBottom View2AT24C128/2560670T–SEEPR–3/07Figure 1. Block DiagramAbsolute Maximum Ratings*Operating T emperature.................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C128/2560670T–SEEPR–3/07Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hard-wired or left not connected for hardware compatibility with other AT24CXX devices. When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-necting the address pins to GND.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to V CC , all write operations to the memory are inhib-ited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-necting the pin to GND.Memory OrganizationAT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word address.4AT24C128/2560670T–SEEPR–3/07Table 2. Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.Table 3. DC Characteristics (1)Notes:1.V IL min and V IH max are reference only and are not tested.2.The A T24C128/256 bearing the process letter “B” on the package (the mark is located in the lower right corner on the top-side of the package) are approved for operation in the extended temperature range.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V; T AE = –40°C to +125°C (2), V CC = +2.7V to +5.5V(unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 3.6V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 4.55.5V I CC1Supply Current V CC = 5.0V READ at 400 kHz 1.0 2.0mA I CC2Supply Current V CC = 5.0V WRITE at 400 kHz 2.0 3.0mA I SB1Standby Current (1.8V option)V CC = 1.8V V IN = V CC or V SS0.2µAV CC = 3.6V 2.0I SB2Standby Current (2.5V option)V CC = 2.5V V IN = V CC or V SS 0.5µA V CC = 5.5V 6.0I SB3Standby Current (5.0V option)V CC = 4.5 - 5.5V V IN = V CC or V SS6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2V5AT24C128/2560670T–SEEPR–3/07Table 4. AC Characteristics – Industrial TemperaturesNotes:1.This parameter is characterized and is not 100% tested.2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.5V , 5V), 10 k Ω (1.8V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤ 50 nsInput and output timing reference voltages: 0.5 V CC3.The Write Cycle Time of 5 ms only applies to the A T24C128/256 devices bearing the process letter “B” on the package (themark is located in the lower right corner on the top side of the package).4.The A T24C128/256 bearing the process letter “B” in the package (the mark is located in the lower right corner on the topside of the package), guarantees 1 million write cycle endurance (1.8 – 3.6V).Applicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.Symbol Parameter1.8-volt2.5-volt5.0-voltUnits MinMax MinMax MinMax f SCL Clock Frequency, SCL 1004001000kHz t LOW Clock Pulse Width Low 4.7 1.30.4µs t HIGH Clock Pulse Width High 4.00.60.4µs t AA Clock Low to Data Out Valid 0.1 4.50.050.90.050.55µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.30.5µs t HD.ST A Start Hold Time 4.00.60.25µs t SU.ST A Start Set-up Time 4.70.60.25µs t HD.DA T Data In Hold Time 000µs t SU.DAT Data In Set-up Time 200100100ns t R Inputs Rise Time (1) 1.00.30.3µs t F Inputs Fall Time (1)300300100ns t SU.STO Stop Set-up Time 4.70.60.25µs t DH Data Out Hold Time 1005050ns t WRWrite Cycle Time 20 or 5(3)10 or 5(3)10 or 5(3)ms Endurance (1)25°C, Page Mode100k or 1,000,000(4)Write Cycles6AT24C128/2560670T–SEEPR–3/07Table 5. AC Characteristics (5) – Extended TemperaturesNotes:1.This parameter is characterized and is not 100% tested.2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.5V , 5V), 10 k Ω (1.8V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤ 50 nsInput and output timing reference voltages: 0.5 V CC3.The Write Cycle Time of 5 ms only applies to the A T24C128/256 devices bearing the process letter “B” on the package (themark is located in the lower right corner on the top side of the package).4.The A T24C128/256 bearing the process letter “B” in the package (the mark is located in the lower right corner on the topside of the package), guarantees 1 million write cycle endurance (1.8 – 3.6V).5.The A T24C128/256 bearing the process letter “B” on the package (the mark is located in the lower right corner on the top-side of the package) are approved for operation in the extended temperature range.Applicable over recommended operating range from T AE = –40°C to +125°C, V CC = +2.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.Symbol Parameter2.7-volt5.0-voltUnits MinMax MinMax f SCL Clock Frequency, SCL 4001000kHz t LOW Clock Pulse Width Low 1.30.4µs t HIGH Clock Pulse Width High 0.60.4µs t AA Clock Low to Data Out Valid0.050.90.050.55µs t BUF Time the bus must be free before a new transmission can start (1) 1.30.5µs t HD.ST A Start Hold Time 0.60.25µs t SU.ST A Start Set-up Time 0.60.25µs t HD.DA T Data In Hold Time 00µs t SU.DAT Data In Set-up Time 100100ns t R Inputs Rise Time (1)0.30.3µs t F Inputs Fall Time (1)300100ns t SU.STO Stop Set-up Time 0.60.25µs t DH Data Out Hold Time 5050ns t WRWrite Cycle Time 10 or 5(3)10 or 5(3)ms Endurance (1)25°C, Page Mode100k or 1,000,000(4)Write Cycles7AT24C128/2560670T–SEEPR–3/07Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 9). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 9).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 5 on page 9).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C128/256 features a low power standby mode which is enabled:a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.8AT24C128/2560670T–SEEPR–3/07Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O ®)Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.9AT24C128/2560670T–SEEPR–3/07Figure 4. Data ValidityFigure 5. Start and Stop DefinitionFigure 6.Output Acknowledge10AT24C128/2560670T–SEEPR–3/07DeviceAddressingThe 128K/256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7 on page 11). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all two-wire EEPROM devices.The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A1and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC .WriteOperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 9 on page 12).The data word address lower 6 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.分销商库存信息:ATMELAT24C128-10TU-1.8AT24C128-10TU-2.7AT24C128N-10SU-1.8AT24C128N-10SU-2.7AT24C256-10TU-1.8AT24C256-10TU-2.7AT24C256N-10SU-1.8AT24C256N-10SU-2.7AT24C128-10PU-1.8AT24C128W-10SU-1.8AT24C128-10PU-2.7AT24C128N-10SU-2.7SL383AT24C128W-10SU-2.7AT24C256-10PU-1.8AT24C256-10PU-2.7AT24C256W-10SU-1.8AT24C256W-10SU-2.7AT24C128-10TU-1.8 SL383AT24C128Y1-10YU-1.8 AT24C128-10TU-2.7 SL383AT24C128Y1-10YU-1.8SL383。
