基于STC89C52单片机的太阳能智能充电系统外文翻译毕业论文

本科毕业设计（论文）AT89S52单片机应用中英文翻译专业名称：电气工程及其自动化年级班级：学生姓名：指导老师：二O一二年六月九日AT89S52 MCU ApplicationsFunction Characteristic DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that areexternally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during eachaccess to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information o n the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDFTimer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart and stabilize.Idle ModIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.AT89S52单片机应用功能特征描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

at89c52单片机简介中英文对照外文翻译文献中英文资料对照外文翻译A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。

Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。

Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。

中文翻译STC89C52处理芯片电气工程的研究和解决方案中心（ceers）艾哈迈德为吉.波特首要性能：与MCS-51单片机产物兼容、8K字节在系统可编程视频存储器、1000次擦拭周期，全静态操作：0Hz~33Hz、三级加密程序存储器，32个可编程I/O接口线、三个16位定时器（计数器），八个中断源、低功能耗空闲和掉电模式、掉电后间断可唤醒，看门狗定时器、双数值指针，掉电标示符。

关键词：单片机，UART串行通道，掉电标示符等前言可以说，二十世纪跨越了三个“点”的时代，即电气时代，电子时代和现已进入的电脑时代。

不过，这种电脑，通常指的是个人计算机，简称PC机。

还有就是把智能赋予各种机械的单片机（亦称微控制器）。

顾名思义，这种计算机的最小系统只用了一片集成电路，即可进行简单的运算可控制。

因为它体积小，通常都是藏在被控机械的内部里面。

它在整个装置中，起着有如人类头脑的作用，他出了毛病，整个装置就会瘫痪。

现在，单片机的种类和适用领域已经十分广泛，如智能仪表、实施工控、通讯设备、导航系统、家用电器等。

各种产品一旦用上了单片机，就你能起到产品升级换代的功效，常在产品名称前冠以形容词——“智能型”，如智能洗衣机等。

接下来就是关于国产STC89C52单片机的一些基本参数。

功能特性描述:STC89C52单片机是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程视频播放存贮器使用高密度非易失性存储器技术制造，与工业80C51 产物指令和引脚完全兼容。

片上反射速度允许程序存储器在系统可编程，也适用于常规的程序编写器。

在其单芯片上，拥有灵敏小巧的八位中央处理器和在线系统可编程反射，这些使用上STC89C52微控制器为众多嵌入式的控制应用系统提供高度矫捷的、更加有用的解决方案。

STC89C52微控制器具有以下的标准功效：8K字节的反射速度，256字节的随机存取储存器，32位I/O串口线，看门狗定时器，2个数值指针，三个16为定时器、计数器，一个6向量2级间断结构，片内晶振及钟表电路。

外文翻译：The monolithic In order to prevent without authorization the visit or the copy monolithic integrated circuit machine in the procedure, the majority of monolithic integrated circuits all has the encryption to lock the localization or the encryption byte, by protects the internal procedure. If in programming time encrypts locks the localization to enable (locking), is unable with the ordinary programming directly reading in the monolithic integrated circuit the procedure, this is the so-called copy protection or says the fixed function. In fact, such protective measures are very frail, is very easily explained. The monolithic integrated circuit aggressor with the aid of the special purpose equipment or the self-made equipment, using the monolithic integrated circuit chip design in loophole or the software flaw, through the many kinds of technical method, may withdraw the essential information from the chip, gains in the monolithic integrated circuit the procedure. Therefore, has the newest technology extremely as electronic products project engineer which the essential understanding current monolithic integrated circuit attacks, achieves knows oneself and the other side, knows fairly well, can effectively prevent oneself spends the product which the massive moneys and the time laboriously designs the matter occurrence which is counterfeited by a others night between.monolithic integrated circuits attacks technology：At present, attacks the monolithic integrated circuit mainly to have four kind of technologies, respectively is:This technical usual use processor correspondence connection and in the use agreement, the encryption algorithm or these algorithm security loophole carries on the attack. The software attack obtains the success a case in point is to early A T M E L A the T 89 C series monolithic integrated circuit attack. The aggressor has used in this series monolithic integrated circuit cleaning operation succession design loophole, uses from arranges the procedure to lock the localization after the cleaning encryption, stops the next step of cleaning internal program memory data the operation, thus makes to add the dense monolithic integrated circuit not to turn the encryption monolithic integrated circuit, then use programming read-out internal procedure.This technology usually monitors the processor by the high time resolution when the normal operation all power sources and the connection connection simulation characteristic, and through monitors its electromagnetic radiation characteristic to implement the attack. Because the monolithic integrated circuit is an active electronic device, when it carries out the different instruction, the corresponding mains input consumption also correspondingly changes. Like this analyzes and examines these changes through the use special electronic surveying instrument and mathematics statistical method, then gains in the monolithic integrated circuit the specific essential information.the mistake has the technology This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may usefor to forbid the protection circuit work or to fortected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the ece the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is proxecution.This technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kind of attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may use for to forbid the protection circuit work or to force the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is protected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the execution.(4) probe technologyThis technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kindof attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.3 invasions attacks general process：The invasion attack first step uncovers the chip seal. Some two methods may achieve this goal: The first kind is dissolves the chip seal completely, the exposed metal segment. The second kind is only moves above the silicon nucleus plastic seal. The first method needs the chip to tests on the jig, with the aid of Taiwan to operate. The second method except needs to have the aggressor certain knowledge and Wants outside skill, but also needs individual wisdom and the patience, but operates relatively quite is convenient.Above the chip plastic may use the knife to open, around the chip epoxy resin may use the aqua fortis perish. The hot aqua fortis can dissolve the chip seal but not to be able to affect the chip and the segment. This process carries on generally under the extremely dry condition, because the water existence possibly can corrode already the aluminum wire connection which exposes.Then first uses the acetone in the supersonic pond to clean this chip by except the remaining nitric acid, then cleans with the clear water by and is dry except the salinity. Not the supersonic pond, jumps over generally this step. In this kind of situation, the chip surface can a little dirty, but not too affects the ultraviolet ray to the chip operation effect.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.If does not have the microscope, then uses the chip different partially exposes to the ultraviolet ray under and the observed result way carries on the simple search. When operation applies not the opaque slip of paper cover chipby to protect the program memory not by the ultraviolet ray cleaning. Will protect the melt silk to expose in the ultraviolet ray next 5 ~ 10 minutes can broken the protection position protective function, afterwards, will use the simple programming to be possible the direct readout program memory content.Regarding used the protective layer to protect E E P R O the M unit the monolithic integrated circuit to say that, the use ultraviolet ray repositioned the protection circuit is not feasible. Regarding this kind of type monolithic integrated circuit, uses the micro probe technology reading the memory content generally. Opens after the chip seal, puts in the chip under the microscope to be able very easy finding中文翻译单片机为了防止未经授权访问或拷贝单片机的机内程序，大部分单片机都带有加密锁定位或者加密字节，以保护片内程序。

STC89C52处理芯片——单片机类毕业设计外文翻译、中英文翻译外文资料翻译STC89C52 processing chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number pointer, power identifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-controller, 8K in system programmable Flash memory. Use high-density nonvolatile storage technology, and industrial 80C51 product instruction and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and online system programmable Flash, increase STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/counters, serial, continuous to work. Protection asana pattern, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way open drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impedance input. When access to external programs and numerical memory, also known as low P0 mouth eight address/numerical reuse. In this mode, with the internal P0 resistor. In the flash when programming, also used for P0 mouth; absorb instruction bytes In the process, the output command byte calibration. When the program requires external, calibration on pull-up resistors. Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O buffers can drive, P1 output four TTL logic level. To write "1" P1 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In addition, P1.0 and P1.2 respectively timer/counter 2 external counting input (P1.0 / T2) and when the trigger editor/counter P1.1 input (2), specific T2EX/are shown below. In programming and calibration, flash P1mouth absorb eight address low byte. Efficacy: the foot. P1.0 T2 (timer/counter T2 external counting input), clock output P1.1 T2EX (timer/counter T2 capture/overloaded triggered signals and direction control), P1.5 MOSI (with) online system programming, P1.6 MISO (with) online system programming, P1.7 SCK (with) online system programming, Mouth: P2 P2 mouth is an internal resistance of the eight two-way I/O buffers and P2 output can drive four TTL logic level. To write "1" P2 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In the external program memory access or use 16bit external numerical memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use strong pull send 1. In using 8-bit address (such as MOVX @ RI) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some control signal. P3: a P3 mouth on the inside of the eight two-way pull-up resistors I/O buffers can drive, p2 output four TTL logic level. For P3 port to write "1", the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). P3 mouth AT89S52 special functions (also as the second efficacy), are shown below. In programming and calibration, flash also absorb some P3 mouth controlsignals. Port pin second efficacy: P3.0 RXD (serial input) P3.1 TXD (serial export), P3.2 INTO the discontinuous (0) P3.3 INT1 (1) the discontinuous P3.4 (time/counter TO 0) P3.5 T1 (1) time/counter, P3.6 WR (external numerical memory write for) P3.7 RD (external numerical memory read for) In addition, also absorb some used in mp3 mouth FLASH memory programming and calibration of program control signals. RST, reset input: when the vibrator, RST pin appeared two machine cycle above high level will be reset the chip. ALE/PROG - when access to external program memory or numerical memory, ALE (address latch allow) output pulses are used to latch address of low eight bytes. Normally, ALE with clock frequencies are 1/6 output pulse si。

基于单片机智能充电器的外文文献翻译--（英文+中文）译文电池充电器集成电路的改进跟上移动手机功能快速增长的速度在全球无线连接的时代，几乎没有什么比让一个智能手机或移动互联网设备保持带电更重要了。

便携式和手持设备功能的扩展性不断提高成为电池充电器集成电路设计者的一个重大挑战。

高分辨率的屏幕和更大的储存能力并加上新的功能赋予电池，这就需要对电池充电器的技术要求，不仅要更有效率，同时要具有配电管理的能力。

通过优化电源消耗来延长电池的寿命是掌上型电源管理的驱动力。

但是当把手持的设备插入墙上，期望对他们进行充电时有有效地变化。

最新一代采用高效率开关设计的充电器会代替传统的线性充电器。

今天的客户仍旧需求更短的充电周期对其电池充电。

相比传统的线性充电器，采用开关充电器的好处，除了效率高之外，还有一个很大的优点是通过电源提供能够促进充电电流。

特别重要的是，当供电结束时接口处的电流可以实现被限制在小于。

更高的充电电USB500mA 流等于充电周期更短，这就满足了客户的期望。

当今有两种被大多数手持设备使用的电池充电器线性充电器和开关充电--- 器。

线性充电器有一段较长的历史。

他们通常提供了相对高效，简单的方式对便携设备充电，同时产生噪音极小且不需要很多的外部元器件。

但是，随着便携式设备变得更加复杂和添加新的功能层，他们就需要更大的电池容量。

由于功能损耗，线性充电器呈现出不足，这很容易知道，假如用户想要对设备充电，且在同一时间又使用。

同时使用设备和对其进行充电产生的热量会损坏系统或电池。

这将会导致不好的结果。

另一种选择是开关充电器，或者是开关模式电池充电器集成电路，它可以提供更高的电流水平，但却需要尽可能少的功率。

历史上，这些类型的集成电路经常存在一些噪音的问题。

此外，一些早期的几代开关模式的设备需要一些外部元件。

1然而，开关模式的电池拓扑结构的好处是显而易见的。

它们包括提高效率和降低功耗，以及快速的充电周期。

这些器件也都能够由高的输入电压进行充电，这就可以允许使用较低成本无管制的适配器。

成都学院（成都大学）学士学位论文（设计）学士学位论文（设计）基于单片机的太阳能电池板自动对光跟踪系统摘要：本文是以A T89C52单片机为核心，设计了一个太阳能电池板自动对光跟踪系统。

系统主要包括光敏传感器、模数转换部分、单片机微处理器、步进电机和电机的驱动电路等，传感器采用光敏二极管作为光-电转换器件，将三个完全相同的光敏二极管分别放置于电池板三个方向分别对光照强度采集，然后由光敏传感器电路将光照强度转换为电压信号，再由ADC0809将电压信号转换为数字信号送入单片机，最后单片机将数字信号进行对比控制电机转动。

该系统精度为4°，系统结构简单、操作方便、测量精度高、速度快。

关键词：太阳能自动跟踪；A/D转换；光敏二极管；单片机微处理器；步进电机Solar Panel Automatically Tracking System Based onMicrocontrollerAbstract: Solar Panel Automatically Tracking System is designed based on AT89C52 microcontroller in this paper.The system includes photosensitive sensor, A/D converter, SCM,stepping motor , drive circuit of motor and so on. Photodiode as a light sensor - power conversion devices, the three identical photodiodes were placed in three directions panels were collected on the light intensity, then the light intensity will be converted to V oltage signal by the light sensor circuit, V oltage signal is put into SCM by the ADC0809 to convert digital signals,the SCM compare digital signals with digital signals to control motor rotation. The system accuracy of 4 °, the system is simple , easy operation , high accuracy, high speed.Keywords：Automatic tracking solar ; A / D conversion; Photodiode ;SCM;Stepping motor目录第1章绪论 (1)1.1 课题背景 (1)1.1.1 能源现伏及发展 (1)1.1.2 我国太阳能资源 (1)1.1.3 目前太阳能的开发和利用 (1)1.1.4 太阳能的特点 (2)1.2 课题研究的目的 (2)1.3 课题研究的意义 (2)1.3.1 新环保能源 (2)1.3.2 提高太阳能的利用率 (3)1.4 太阳能光伏发电国内外的现状 (3)1.5 太阳能追踪系统国内外研究现状 (4)1.6 论文的研究内容 (4)1.7 论文结构 (5)第2章太阳能自动跟踪系统总体设计 (6)2.1 太阳运行的规律 (6)2.2 跟踪器机械执行部分 (6)2.2.1 立柱转动式要跟踪器 (6)2.2.2 陀螺仪式跟踪器 (7)2.2.3 齿圈转动式跟踪器 (7)2.3 太阳能跟踪设计 (9)2.3.1 常用太阳能跟踪方案 (9)2.3.2 太阳能跟踪方案的确定 (10)2.4 太阳能跟踪传感器的设计 (10)2.4.1 光线和影子的关系 (10)2.4.2 跟踪传感器的跟踪精度 (11)2.4.3 太阳跟踪方案的确定 (12)2.4.4 太阳光照强度的检测 (14)2.4.5 太阳能跟踪传感器的设计制作 (15)2.4.6 太阳能传感器电路设计 (19)第3章系统硬件设计 (21)3.1 太阳能自动跟踪控制 (21)3.2 电源 (21)3.3 信号采集电路 (22)3.4 控制器 (24)3.4.1 单片机简介 (24)3.4.2 单片机外围电路设计 (25)3.5 模数转换 (25)3.5.1 ADC0809说明 (26)3.6 步进电机及驱动 (28)3.6.1 驱动电路 (28)3.6.2 步进电机 (29)第4章系统软件设计 (32)4.1 A/D转换部分 (32)4.2 光敏二极管比较法 (33)4.3 系统流程图 (35)第5章总结 (37)5.1 结论 (37)5.2 展望 (37)致谢 (38)参考文献 (40)附录1 系统硬件电路图 (42)附录2 程序清单 (43)第1章绪论1.1 课题背景1.1.1 能源现伏及发展能源是人类社会赖以生存和发展的物质基础。

中英文资料对照外文翻译文献综述Design of a Lead-Acid Battery Charging and Protecting IC in Photovoltaic System1.IntroductionSolar energy as an inexhaustible, inexhaustible source of energy more and more attention. Solar power has become popular in many countries and regions, solar lighting has also been put into use in many cities in China. As a key part of the solar lighting, battery charging and protection is particularly important. Sealed maintenance-free lead-acid battery has a sealed, leak-free, pollution-free, maintenance-free, low-cost, reliable power supply during the entire life of the battery voltage is stable and no maintenance, the need for uninterrupted for the various types of has wide application in power electronic equipment, and portable instrumentation. Appropriate float voltage, in normal use (to prevent over-discharge, overcharge, over-current), maintenance-free lead-acid battery float life of up to 12 ~ 16 years float voltage deviation of 5% shorten the life of 1/2. Thus, the charge has a major impact on this type of battery life. Photovoltaic, battery does not need regular maintenance, the correct charge and reasonable protection, can effectively extend battery life. Charging and protection IC is the separation of the occupied area and the peripheral circuit complexity. Currently, the market has not yet real, charged with the protection function is integrated on a single chip. For this problem, design a set of battery charging and protection functions in one IC is very necessary.2.System design and considerationsThe system mainly includes two parts: the battery charger module and the protection module. Of great significance for the battery as standby power use of the occasion, It can ensure that the external power supply to the battery-powered, but also in the battery overcharge, over-current and an external power supply is disconnected the battery is to put the state to provide protection, the charge and protection rolled into one to make the circuit to simplify and reduce valuable product waste of resources. Figure 1 is a specific application of this Ic in the photovoltaic powergeneration system, but also the source of this design.Figure1 Photovoltaic circuit system block diagramMaintenance-free lead-acid battery life is usually the cycle life and float life factors affecting the life of the battery charge rate, discharge rate, and float voltage. Some manufacturers said that if the overcharge protection circuit, the charging rate can be achieved even more than 2C (C is the rated capacity of the battery), battery manufacturers recommend charging rate of C/20 ~ C/3. Battery voltage and temperature, the temperature is increased by 1 °C, single cell battery voltage drops 4 mV , negative temperature coefficient of -4 mV / ° C means that the battery float voltage. Ordinary charger for the best working condition at 25 °C; charge less than the ambient temperature of 0 °C; at 45 °C may shorten the battery life due to severe overcharge. To make the battery to extend the working life, have a certain understanding and analysis of the working status of the battery, in order to achieve the purpose of protection of the battery. Battery, there are four states: normal state, over-current state over the state of charge, over discharge state. However, due to the impact of the different discharge current over-capacity and lifetime of the battery is not the same, so the battery over discharge current detection should be treated separately. When the battery is charging the state a long time, would severely reduce the capacity of the battery and shorten battery life. When the battery is the time of discharge status exceeds the allotted time, the battery, the battery voltage is too low may not be able to recharge, making the battery life is lower.Based on the above, the charge on the life of maintenance-free lead-acid batteries have a significant impact, while the battery is always in good working condition, battery protection circuit must be able to detect the normal working condition of the battery and make the action the battery can never normal working state back to normal operation, in order to achieve the protection of the battery.3.Units modular design3.1The charging module Chip, charging module block diagram shown in Figure 2. The circuitry includes solar battery array Charge controller controller Discharge controller DC load accumulatorcurrent limiting, current sensing comparator, reference voltage source, under-voltage detection circuit, voltage sampling circuit and logic control circuit.Figure2 Charging module block diagramThe module contains a stand-alone limiting amplifier and voltage control circuit, it can control off-chip drive, 20 ~30 mA, provided by the drive output current can directly drive an external series of adjustment tube, so as to adjust the charger output voltage and current . V oltage and current detection comparator detects the battery charge status, and control the state of the input signal of the logic circuit. When the battery voltage or current is too low, the charge to start the comparator control the charging. Appliances into the trickle charge state when the cut-off of the drive, the comparator can output about 20 mA into the trickle charge current. Thus, when the battery short-circuit or reverse, the charger can only charge a small current, to avoid damage to the battery charging current is too large. This module constitutes a charging circuit charging process is divided into two charging status: high-current constant-current charge state, high-voltage charge status and low-voltage constant voltage floating state. The charging process from the constant current charging status, the constant charging current of the charger output in this state. And the charger continuously monitors the voltage across the battery pack, the battery power has been restored to 70% to 90% of the released capacity when the battery voltage reaches the switching voltage to charge conversion voltage Vsam charger moves to the state of charge. In this state, the charger output voltage is increased to overcharge pressure driverV oltage amplifierV oltage sampling comparatorStart amplifier State level control Charging indicator Logical module Undervoltage detection circuit R- powerCurrent sampling comparator Limiting amplifier Power indicatorV oc is due to the charger output voltage remains constant, so the charging current is a continuous decline. Current down to charge and suspend the current Ioct, the battery capacity has reached 100% of rated capacity, the charger output voltage drops to a lower float voltage VF.3.2 Protection ModuleChip block diagram of the internal protection circuit shown in Figure 3. The circuit includes control logic circuit, sampling circuit, overcharge detection circuit, over-discharge detection comparator, overcurrent detection comparator, load short-circuit detection circuit, level-shifting circuit and reference circuit (BGR).Figure3 Block diagram of battery protectionThis module constitutes a protection circuit shown in Figure 4. Under the chip supply voltage within the normal scope of work, and the VM pin voltage at the overcurrent detection voltage, the battery is in normal operation, the charge and discharge control of the chip high power end of the CO and DO are level, when the chip is in normal working mode. Larger when the battery discharge current will cause voltage rise of the VM pin at the VM pin voltage at above the current detection voltage Viov, then the battery is the current status, if this state to maintain the tiov overcurrent delay time, the chip ban on battery discharge, then the charge to control the end of CO is high, the discharge control side DO is low, the chip is in the current mode, general in order to play on the battery safer and more reasonable protection, the chip will battery over-discharge current to take over the discharge current delay time protection. The general rule is that the over-discharge current is larger, over the Sampling circuitOver discharge detection comparator Control logic circuitLevel conversion circuit Overcharge detection comparator Over-current detection comparator2 Over-current detection comparator1Over-current detection circuitLoad short detection circuitshorter the discharge current delay time. Above Overcharge detection voltage, the chip supply voltage (Vdd> Vcu), the battery is in overcharge state, this state is to maintain the corresponding overcharge delay time tcu chip will be prohibited from charging the battery, then discharge control end DO is high, and charging control terminal CO is low, the chip is in charging mode. When the supply voltage of the chip under the overdischarge detection voltage (Vdd <Vdl,), then the battery is discharged state, this state remains the overdischarge delay time tdl chip will be prohibited to discharge the battery at this time The charge control side CO is high, while the discharge control terminal DO is low, the chip is in discharge mode.ProtectionmoduleFigure4 Protection circuit application schematic diagram4.Circuit DesignTwo charge protection module structure diagram, the circuit can be divided into four parts: the power detection circuit (under-voltage detection circuit), part of the bias circuit (sampling circuit, the reference circuit and bias circuit), the comparator (including the overcharge detection /overdischarge detection comparator, over-current detection and load short-circuit detection circuit) and the logic control part.This paper describes the under-voltage detection circuit (Figure 5), and gives the bandgap reference circuit (Figure 6).Figure5 Under-voltage detection circuitFigure6 A reference power supply circuit diagramBattery charging, voltage stability is particularly important, undervoltage, overvoltage protection is essential, therefore integrated overvoltage, undervoltage protection circuit inside the chip, to improve power supply reliability and security. And protection circuit design should be simple, practical, here designed a CMOS process, the undervoltage protection circuit, this simple circuit structure, process and easy to implement and can be used as high-voltage power integrated circuits and other power protection circuit.Undervoltage protection circuit schematic shown in Figure 5, a total of five components: the bias circuit, reference voltage, the voltage divider circuit, differential amplifier, the output circuit. The circuit supply voltage is 10V; the M0, M1, M2, R0 is the offset portion of the circuit to provide bias to the post-stage circuit, the resistance, Ro, determine the circuit's operating point, the M0, M1, M2 form a current mirror; R1 M14 is the feedback loop of the undervoltage signal; the rest of the M3, M4 and M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, composed of four amplification comparator; M15, DO, a reference voltage, the comparator input with the inverting Biasing circuit Reference circuit Bleeder circuit difference amplifier Output circuitAmplifierAmplifierinput is fixed (V+), partial pressure of the resistance R1, R2, R3, the input to the inverting input of the comparator, when the normal working of the power supply voltage, the inverting terminal of the voltage detection is lost to the inverting terminal voltage of the comparator is greater than V+. Comparator output is low, M14 cutoff, feedback circuit does not work; undervoltage occurs, the voltage divider of R1, R2, R3, reaction is more sensitive, lost to the inverting input voltage is less than V when the resistor divider, the comparator the output voltage is high, this signal will be M14 open, the voltage across R into M at both ends of the saturation voltage close to 0V, thereby further driving down the R1> R2, the partial pressure of the output voltage, the formation of the undervoltage positive feedback. Output, undervoltage lockout, and plays a protective role.5. Simulation results and analysisThe design of the circuit in CSMC 0.6 μm in digital CMOS process simulation and analysis of the circuit. In the overall simulation of the circuit, the main observation is that the protection module on the battery charge and discharge process by monitoring Vdd potential and Vm potential leaving chip CO side and DO-side changes accordingly. The simulation waveform diagram shown in Figure 7, the overall protection module with the battery voltage changes from the usual mode conversion into overcharge mode, and then return to normal working mode, and then into the discharge mode, and finally back to normal working mode. As the design in the early stages of the various parameters to be optimized, but to provide a preliminary simulation results.Figure7 Overvoltage and under-voltage protection circuit simulation waveform6.ConclusionDesigned a set of battery charging and protection functions in one IC. This design not only can reduce the product, they can reduce the peripheral circuit components. The circuit uses the low-power design. This project is underway to design optimization stage, a complete simulation can not meet the requirements, but also need to optimize the design of each module circuit.光伏系统中蓄电池的充电保护IC电路设计1.引言太阳能作为一种取之不尽、用之不竭的能源越来越受到重视。

毕业论文(设计)文献翻译本翻译源自于：维基百科wikiMicrocontroller毕业设计名称:基于STC89C52单片机的太阳能智能充电系统外文翻译名称：微控制器学生姓名：张钱勇院 (系)：电子信息学院专业班级：电气10803 指导教师：唐桃波辅导教师：唐桃波时间： 2012年4月15日至 2012年4月24日微控制器英特尔8742的核心, 片上集成12 MHz的CPU, 128字节的RAM, 2048字节EPROM, 以及IO设备。

微控制器，也称单片机（有时缩写为μC，UC或MCU）是一种在单个集成电路上包含一个控制器核心，内存和可编程输入输出外设的小型计算机。

类型为NOR Flash或OTP ROM的存储器也往往包括在芯片上，以及通常少量的RAM。

微控制器(MCU)是专为嵌入式应用，而相比之下，个人电脑或其他一般用途的应用中使用微控制器(CPU)。

微控制器用于自动控制产品和设备，如汽车发动机控制系统，植入式医疗设备，遥控器，办公设备，家用电器，电动工具，玩具。

比起使用一个单独的微控制器，内存和输入输出设备，微控制器通过降低尺寸和成本来更经济地数控更多的设备和流程。

混合信号微控制器是很常见的，整合了需要控制非数字电子系统的模拟组件。

有些微控制器可使用四位字长，操作频率的时钟速率低至4 kHz来实现低功耗（毫瓦或微瓦）。

他们通常在等待一个事件，如按一个按钮或其它中断时进入节能状态，处于节能状态（CPU时钟和大部分的外设关闭）时功耗可能只有纳瓦级别，使得他们很适合用电池供电长期工作。

其他微控制器，像数字信号控制器（DSP），可能需要注重性能，他们有更大的计算量，更高的时钟速度和更大的功耗。

历史在1971年第一款单片机4位英特尔4004被发布, 在随后的数年时间里英特尔8008和其它功能更为强大微控制器也开始出现。

然而,控制器需要外部芯片来实现某工作方式,这就提高了整个系统的成本,使它不能成为经济的电子器件。

中国矿业大学本科生毕业设计附外文文献及翻译基于MC-SILICON的双面太阳能电池在工业环境中的实现姓名：学号：学院：信息与电气工程学院专业：电气工程与自动化设计题目：单片机控制的太阳能充电器（硬件）专题：指导教师：职称：副教授摘要在污染和能源口趋紧张的背景下，太阳能作为一种新型的绿色可再生能源，具有储量大、利用经济、清洁环保等优点。

因此，太阳能的利用越来越受到人们的重视。

本文试图设计一种切实可行的太阳能充电控制器，通过对蓄电池充电，满足小功率的用户需求。

本文重点研究了用AT89S52实现太阳能充电控制技术。

详细介绍了100瓦太阳能电池板向12伏蓄电池充电的太阳能控制器硬件系统，包括系统的硬件电路设计、各部分电路的功能、工作原理和电子元器件型号的选取。

硬件系统由直流稳压电源电路，A/D实现对蓄电池端电压的动态监测及转换、AT89S52控制以及输出继电器开关电路四个部分组成，完成了整个太阳能充电控制器电路原理图的设计和制作。

用PROTEUS仿真软件进行了电路仿真，并且制作了相应的电路板。

但是由于时间关系，没能完成实物的实验测试。

本文还对太阳能电池的结构原理、太阳能电池板的伏安特性、常用的铅酸蓄电池原理及工作情况作了详细介绍，并在此基础上介绍常用的蓄电池充电方法。

关键词：太阳能；蓄电池；充电控制；AT89S52；ADC0809ABSTRACTAgainst the background of energy shortage and its pollution, solar energy as a new kind of energy has a lot of advantages such as large reserves, economic, cleanliness and so on. So, people begin to pay more attention to the use of solar energy. The paper designs a feasible solar energy charging controller and storage batteries are charged to meet the needs of low-power users.This article focuses on the use of single-chip realization of solar charge control technology. 100-watt solar panels to 12-volt solar battery charge controller hardware system is detailed, including system hardware circuit design, the various parts of the circuit functions, working principles and models of selected electronic components. Hardware system is composed of four parts, which are DC regulated power supply circuit, A / D to achieve on the battery terminal voltage of the dynamic monitoring and conversion, AT89S52 relay control and output switching circuit. And finish the entire solar charge controller circuit schematic design and production. PROTEUS simulation with circuit simulation software was accomplished, and a corresponding circuit board was produced. However, due to time constraints, failed to complete the kind of experimental test.In this paper, also the structure of the principle of solar cells, solar panels of the Volta metric characteristics of lead-acid batteries commonly used in the work of principle was detailed, and the basis of methods commonly used on rechargeable batteries was introduced.Key words: solar; battery; charge control; AT89S52; ADC0809目录摘要 (i)ABSTRACT (ii)1 绪论 (1)1.1 课题研究背景 (1)1.1.1 当前面临的能源和环境问题 (1)1.1.2 太阳能的开发和利用 (2)1.1.3 光伏发电的特点 (3)1.2 蓄电池充电系统 (3)1.2.1充电器的发展及其简单的类型 (3)1.2.2 太阳能充电器 (4)1.3 本课题研究的主要内容 (5)2 太阳能电池的研究和分析 (6)2.1 太阳能电池的原理 (6)2.2 太阳能电池的分类 (6)2.3 太阳能电池的等效电路 (7)2.4 太阳能电池板的输出特性及影响因素 (8)2.4.1光伏电池的主要参数 (8)2.4.2太阳的光照强度对光伏电池转换效率的影响 (10)2.4.3 温度对光伏电池输出特性的影响 (10)2.4.4 本系统所采用的光伏电池 (11)2.5 本章小结 (12)3 蓄电池 (13)3.1 蓄电池的概念及其一般特性 (13)3.1.1 电池的定义 (13)3.1.2 主要参数指标 (13)3.1.3 充放电特性 (15)3.2 铅酸蓄电池 (16)3.2.1 铅酸蓄电池的电极反应 (17)3.2.2 铅酸蓄电池的充放电特性 (18)3.3 太阳能----蓄电池充电技术研究 (20)3.3.1 恒流充电 (20)3.3.2 恒压充电 (21)3.3.3 恒压限流充电 (22)3.3.4 两阶段、三阶段充电 (22)3.3.5 快速充电 (22)3.3.6 智能充电 (23)3.4 本章小结 (23)4 太阳能充电控制器的研究及设计 (24)4.1太阳能充电器原理 (24)4.1.1 主控芯片的设计 (24)4.1.2 模数转换模块ADC0809简介 (28)4.1.3 电源模块的设计 (30)4.1.4 分频器的设计 (30)4.1.5 外围电路的设计 (30)4.1.6ADC0809与AT89S52接口 (32)4.1.7 74LS00 (33)4.2 单片机的防干扰技术 (35)4.2.1干扰分析 (35)4.2.2硬件抗干扰方法 (36)4.3 系统的软件设计概述 (37)4.4 本章小结 (39)5 结论 (40)5.1 全文工作总结 (40)5.2 进一步工作设想 (40)致谢 (42)参考文献 (43)翻译部分 (45)中文译文 (45)英文原文 (53)1 绪论1.1 课题研究背景1.1.1 当前面临的能源和环境问题[1,2,3,4]能源犹如人体的血液。