Energy-Efficient Instruction Cache using Page-Based Placement

Appeared in the Proceedings of International conference on Compilers, Architectures and synthesis for Embedded Systems, 2002.
Energy-Efficient Instruction Cache Using Page-Based Placement
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Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments. In order to optimize energy and energy-delay in the memory system, we investigate ways of splitting the instruction cache into several smaller units, each of which is a cache by itself called subcache. The subcache architecture employs a page-based placement strategy, a dynamic cache line remapping policy and a predictive precharging policy in order to improve the memory system energy behavior. Using applications from the SPECjvm98 and SPECint2000 benchmarks, the proposed subcache architecture is shown to be e ective in improving both the energy and energy-delay metrics.
S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin Department of Computer Science and Engineering The Pennsylvania State University, PA 16802 ABSTRACT
1.
Energy has become an important design consideration, together with performance, in computer systems 4 . This can be attributed to the proliferation of battery-driven mobile systems and the constraints imposed on the capabilities of these systems due to the limited improvements in the energy of commercially available re-chargeable batteries. As a result, there has been a great deal of interest recently in examining optimizations for energy reduction at various levels from the circuit to software view points. To address this increasingly important problem, this paper explores energye cient cache architectures in the memory hierarchy that can have a signi cant impact on the overall system energy consumption. The motivation for examining energy-e cient cache architectures stems from the following observations. It has been reported 15 that the memory system can consume a large fraction of the overall system energy, making this a ripe candidate for optimization. Whether a reference goes This work was supported in part by NSF grants 0073419, 0082064, 0093082, 0093085, and GSRC.
INTRODUCTION
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to the main memory or not, it has to go through the cache, putting this component in the critical path - from both the performance and energy viewpoints - of the memory hierarchy. An important trend in low power hardware design is the partitioning of hardware components into smaller and less energy consuming components 17 . The selective disabling of unused components is an e ective mechanism for reducing energy consumption. Partitioning has been used for caches for both performance and energy considerations. A large cache is broken down into smaller subbanks to reduce the wiring and di usion capacitances of the bitlines as well as the wiring and gate capacitances of the wordlines used to activate the memory cells. The reduced capacitance helps lower the dynamic energy consumption when accessing the caches. Existing approaches have looked at partitioning the caches at the circuit level and enabling disabling these subbanks at the architectural level from both the performance and energy viewpoints 1, 5 . This paper focuses on partitioning the cache resources architecturally for energy, performance and energy-delay optimizations. Speci cally, we examine ways of splitting the cache into several smaller units, each of which is a cache by itself called subcache. The proposed technique reduces energy consumption by precharging and accessing only the subcache predicted to hold the required data. Further, the technique employs a strategy to improve the cache performance by using a dynamic remapping scheme for cache lines. In turn, this policy also provides additional energy bene ts by reducing on-chip and o -chip accesses. It must be noted that each subcache can further be partitioned into subbanks for energy and performance similar to traditional cache con guration 16 . In this paper, we concentrate on the instruction cache. As the instruction cache is accessed on every clock cycle, it consumes more energy than the data cache. Figure 1 shows percentage energy breakdown between instruction accesses and data accesses for the benchmark programs used in this paper. The cache con guration used is 32KB direct-mapped instruction and data caches with 32 byte cache line. The energy includes the one consumed in caches as well as in bus and main memory. Instruction accesses consume 70 on the average of the total memory system energy. So optimizing energy consumption of instruction accesses has a big impact on total memory system energy consumption. The rest of this paper is organized as follows. The next section discusses the related work. In section 3, we explain