RJ714P1-C中文资料

PhotocouplerProduct Data SheetLTV-814824844 (M,S,S-TA,S-TA1,S-TP) SeriesSpec No.:DS-70-96-0013Effective Date:01/05/2019LITE-ON DCCRELEASEBNS-OD-FC001/A4PhotocouplerLTV-8X4series 1.DESCRIPTION1.1FeaturesCurrent transfer ratio(CTR:MIN.20%at I F=±1mA,V CE=5V)High input-output isolation voltage(V iso=5,000Vrms)Response time(tr:TYP.4µs at V CE=2V,I C=2mA,R L=100Ω)Dual-in-line package:LTV-814:1-channel typeLTV-824:2-channel typeLTV-844:4-channel typeWide lead spacing package:LTV-814M:1-channel typeLTV-824M:2-channel typeLTV-844M:4-channel typeSurface mounting package:LTV-814S:1-channel typeLTV-824S:2-channel typeLTV-844S:4-channel typeTape and reel packaging:LTV-814S-TA:1-channel typeLTV-814S-TA1:1-channel typeLTV-814S-TP:1-channel typeLTV-824S-TA1:2-channel typeSafety approvalUL1577VDE DIN EN60747-5-5(VDE0884-5)CSA CA5ANordic Safety(FIMKO/NEMKO/SEMKO/DEMKO)BSI RoHS ComplianceAll materials be used in device are followed EU RoHS directive(No.2002/95/EC,2011/65/EU,and2015/863).ESD pass HBM8000V/MM2000VMSL class11.2ApplicationsHybrid substrates that require high density mounting.Programmable controllersPhotocoupler LTV-8X4series2.PACKAGE DIMENSIONS2.1LTV-8142.2LTV-814M2.3LTV-814SNotes :1.2.3.Year date code.2-digit work week.Factory identification mark shall be marked(W:China-CZ,Y:Thailand)4.5.6.Rank shall be or shall not be marked.“●”for halogen free option.“4”or”V”for VDE option.Dimensions in millimeters (inches).Photocoupler LTV-8X4series2.4LTV-8242.5LTV-824M2.6LTV-824SNotes :1.2.3.Year date code.2-digit work week.Factory identification mark shall be marked (W:China-CZ,Y:Thailand)4.5.Rank shall be or shall not be marked.“●”for halogen free option.6.VDE option shall be.Dimensions in millimeters (inches).PhotocouplerLTV-8X4series 2.7LTV-8442.8LTV-844M2.9LTV-844SNotes:1.2.3.Year date code.2-digit work week.Factory identification mark shall be marked(W:China-CZ,Y:Thailand)4.5.Rank shall be or shall not be marked.“●”for halogen free option.6.VDE option shall be.Dimensions in millimeters(inches).PhotocouplerLTV-8X4series 3.TAPING DIMENSIONS3.1LTV-814S-TA 3.2LTV-814S-TA1Tape wide WP0F16±0.3(0.63)4±0.1(0.15)Pitch of sprocket holes7.5±0.1(0.295)2±0.1(0.079)Distance of compartmentP2Distance of compartment tocompartmentP112±0.1(0.472)3.3Quantities Per ReelQuantities(pcs)1000Photocoupler LTV-8X4series3.4LTV-814S-TPTape wide W P 0F 16±0.3(0.63)4±0.1(0.15)Pitch of sprocket holes 7.5±0.1(0.295)2±0.1(0.079)Distance of compartment P 2Distance of compartment tocompartmentP 18±0.1(0.315)3.5Quantities Per ReelQuantities (pcs)2000Photocoupler LTV-8X4series3.6LTV-824S-TA3.7LTV-824S-TA1Tape wide W P 0F 16±0.3(0.63)4±0.1(0.15)Pitch of sprocket holes 7.5±0.1(0.295)2±0.1(0.079)Distance of compartment P 2Distance of compartment tocompartmentP 112±0.1(0.472)3.8Quantities Per ReelQuantities (pcs)1000Photocoupler LTV-8X4series4.RATING AND CHARACTERISTICS4.1Absolute Maximum Ratings at Ta=25°CI F mA mW V Forward Current ±5070InputPower Dissipation P Collector -Emitter VoltageV CEO V ECO I C 35Emitter -Collector Voltage6V OutputCollector Current 50mA mW mW V rmsCollector Power Dissipation Total Power DissipationP C 150P tot 2001.Isolation VoltageOperating Temperature (LTV-824/844)Operating Temperature (LTV-814)Storage TemperatureV iso T opr T opr T stg T sol5000-30~+100-50~+110-55~+125260o o o oC C C C2Soldering Temperature1.AC For 1Minute,R.H.=40~60%Isolation voltage shall be measured using the following method.(1)Short between anode and cathode on the primary side and between collector and emitter on thesecondary side.(2)The isolation voltage tester with zero-cross circuit shall be used.(3)The waveform of applied voltage shall be a sine wave.2.For 10SecondsPhotocoupler LTV-8X4series4.2ELECTRICAL OPTICAL CHARACTERISTICS at Ta=25°CForward VoltageV F—1.21.4VI F =±20mAInputTerminal Capacitance C t ——3530——250100—pF nA VV=0,f=1KHz V CE =20V,I F =0I C =0.1mA,I F =0Collector Dark Current Collector-EmitterI CEOBV CEOOutputBreakdown Voltage Emitter-Collector BV ECO6——VI E =10µA,I F =0Breakdown Voltage Collector Current I C 0.220——3mA%I F =±1mA,V CE =5V 1.Current Transfer Ratio CTR300Collector-Emitter Saturation Voltage V CE(sat)—0.10.2V I F =±20mA,I C =1mA DC500V,Isolation Resistance Floating CapacitanceCut-off Frequency R iso Cff c5×10101×100.680411—1ΩpFkHz µsTRANSFER 40~60%R.H.CHARACTERISTICS—V=0,f=1MHz V CE =5V,I C =2mA ——1818R L =100Ω,-3dBResponse Time (Rise)Response Time (Fall)tr —V CE =2V,I C =2mAR L =100Ω,tf—3µsI C 1.CTR =×100%IFPhotocoupler LTV-8X4series5.RANK TABLE OF CURRENT TRANSFER RATIO CTRA5010010020150200300300300300A5BLTV-814I F =±1mA V CE =5V A or B or No markNo mark No markTa=25CoLTV-824LTV-8442020Photocoupler LTV-8X4series6.CHARACTERISTICS CURVESFig.2Collector Power Dissipation Fig.1Forword CurrentFig.2Collector Power Dissiptionvs.Ambient Temperaturevs.Ambient Temperatute601601401201008060200150100505050404030201003020100604020-30-20-3002025405060758010010012512025205040756010080125100-60-40-20-60-40120T A -Ambie A n m t T b e ie m n p t e te r m at p u e re rat -u o r C e Ta (C)T A -Ambient Ambien temperaturet Temperatur Ta e-(o C)C Fig.3Collector-emitter SaturationVoltage vs.Forward CurrentFig.4Forward Current vs.ForwardVoltage6Ta=25C20010051251015Forward voltage V F (V)Fig.5Current Transfer Ratio vs.Forward CurrentFig.6Collector Current vs.Collector-emitter Voltage100010002008030252015105T A =25o CV C 1E =850VT A =16025V CE =5VV CE =5V Ta=25I F =30mAT A =25CoTa=25CC70o C 20mA605040302010Pc(MAX.)1401201008010010010mAI =10mA F 1060V CE =0.4VP C MAX.5mAI F =5mA 4020I F =1mA1011251020501234567898246100.10.1111010110000Forward current I (mA)Collector-emitter voltage V (V)F V CE(non-sat)-Non-Saturated Collector E CE mitterVoltage -VI IF F --Fo Forward rward Cur Current rent -mA -mAPhotocoupler LTV-8X4seriesFig.7Relative Current Transfer Ratiovs.Ambient TemperatureFig.8Collector-emitter Saturation Voltagevs.Ambient Temperature0.10100Ambient temperature Ta (C)Fig.9Collector Dark Current vs.Fig.10Response Time vs.Load Resistancevs.Ambient Temperature10-6100V =2V CE 50Ic=2mA 10-7Ta=25Ctr20105tf10-8td 10-921ts10-100.510-110.20.110-12-300204060801000.10.20.512510Ambient Temperature Ta (C)Load resistance R (k )LFig.11Frequency Response Test Circuit for Response TimeInput VccV =2V Ic=2mATa=25Output R L10%90%InputR DOutputCtdts trtfR L =10k 1k 100-10-20Test Circuit for Frequency ResponseVccR LR DOutput0.20.5125101001000Frequency f (kHz)Photocoupler LTV-8X4series7.TEMPERATURE PROFILE OF SOLDERING7.1IR Reflow soldering (JEDEC-STD-020C compliant)Onetimesolderingreflowisrecommendedwithintheconditionoftemperatureandtimeprofileshownbelow.Donotsolder morethanthreetimes.Profile itemConditionsPreheat-Temperature Min (T Smin )150˚C 200˚C -Temperature Max (T Smax -Time (min to max)(ts)Soldering zone)90±30sec-Temperature (T L )-Time (t L )217˚C 60sec Peak Temperature (T P )Ramp-up rate 260˚C 3˚C /sec max.3~6˚C /secRamp-down rate20secRamp-upTP 260CTL 217CTsmax 200CRamp-downTsmin 150C60sec tL (Soldering)25CTime (sec)60~120sec ts (Preheat)35~70secPhotocoupler LTV-8X4series7.2Wave soldering (JEDEC22A111compliant)Onetimesolderingisrecommendedwithintheconditionoftemperature.Temperature:260+0/-5˚C Time:10sec.Preheat temperature:25to140˚C Preheat time:30to80sec.7.3Hand soldering by soldering ironAllowsingleleadsolderingineverysingleprocess.Onetimesolderingisrecommended.Temperature:380+0/-5˚C Time:3sec max.PhotocouplerLTV-8X4series 8.RECOMMENDED FOOT PRINT PATTERNS(MOUNT PAD)8.14PIN8.28PIN8.316PINNote:Dimensions in millimeters.PhotocouplerLTV-8X4series 9.NAMING RULELTV-8X4(1)-(2)-(3)-GDEVICE PART NUMBER(1)No suffix=Dual-in-Line packageM=Wide lead spacing packageS=Surface mounting package(2)TAPING TYPE(TA,TA1,TP or none)(3)CTR RANK(4)Halogen free optionExample:LTV-814S-TA1-A-GLTV8X4(1)(2)(3)-V-GDEVICE PART NUMBER(1)No suffix=Dual-in-Line packageM=Wide lead spacing packageS=Surface mounting package(2)TAPING TYPE(TA,TA1,TP or none)(3)CTR RANK(4)VDE order option(5)Halogen free optionExample:LTV814STA1A-V-G10.NOTESLiteOn is continually improving the quality,reliability,function or design and LiteOn reserves the right to make changes without further notices.The products shown in this publication are designed for the general use in electronic applications such as office automation equipment,communications devices,audio/visual equipment,electrical application and instrumentation.For equipment/devices where high reliability or safety is required,such as space applications,nuclear power control equipment,medical equipment,etc,please contact our sales representatives.When requiring a device for any”specific”application,please contact our sales in advice.If there are any questions about the contents of this publication,please contact us at your convenience.The contents described herein are subject to change without prior notice.Immerge unit’s body in solder paste is not recommended.。

74AC32, 74ACT32 — Quad 2-Input OR GateQuad 2-Input OR GateFeatures■ I CC reduced by 50% on 74AC only ■ Outputs source/sink 24mA ■ ACT32 has TTL-compatible inputsGeneral DescriptionThe AC32/ACT32 contains four, 2-input OR gates.Ordering InformationDevice also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.All packages are lead free per JEDEC: J-STD-020B standard.Connection Diagram Logic SymbolIEEE/IECOrder NumberPackage NumberPackage Description74AC32SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74AC32MTC MTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74AC32PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT32SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT32MTC MTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74ACT32PCN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide元器件交易网74AC32, 74ACT32 — Quad 2-Input OR GateRecommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.V CC Supply Voltage –0.5V to +7.0VI IKDC Input Diode Current V I = –0.5V –20mA V I = V CC + 0.5+20mAV I DC Input Voltage –0.5V to V CC + 0.5VI OKDC Output Diode Current V O = –0.5V –20mA V O = V CC + 0.5V+20mAV O DC Output Voltage–0.5V to V CC + 0.5VI O DC Output Source or Sink Current ±50mA I CC or I GND DC V CC or Ground Current per Output Pin±50mAT STG Storage Temperature –65°C to +150°CT JJunction Temperature140°CSymbol ParameterRatingV CCSupply Voltage AC 2.0V to 6.0V ACT4.5V to5.5V V I Input Voltage 0V to V CC V O Output Voltage 0V to V CCT A Operating Temperature–40°C to +85°C∆ V / ∆ t Minimum Input Edge Rate, AC Devices:V IN from 30% to 70% of V CC , V CC @ 3.3V , 4.5V , 5.5V 125mV/ns ∆ V / ∆ tMinimum Input Edge Rate, ACT Devices: V IN from 0.8V to 2.0V , V CC@ 4.5V , 5.5V125mV/ns元器件交易网74AC32, 74ACT32 — Quad 2-Input OR GateNotes:1.All outputs loaded; thresholds on input associated with output under test.2.Maximum test duration 2.0ms, one output loaded at a time.3.I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC .5.5 2.75 3.85 3.85V ILMaximum LOW Level Input Voltage3.0V OUT = 0.1V or V CC – 0.1V1.50.90.9V4.5 2.25 1.35 1.355.5 2.75 1.65 1.65V OHMinimum HIGH Level Output Voltage3.0I OUT = –50µA2.99 2.9 2.9V 4.5 4.49 4.4 4.45.5 5.495.4 5.43.0V IN = V IL or V IH ,I OH = –12mA 2.56 2.464.5V IN = V IL or V IH ,I OH = –24mA 3.86 3.765.5V IN = V IL or V IH ,I OH = –24mA (1) 4.864.76V OLMaximum LOW Level Output Voltage3.0I OUT = 50µA0.0020.10.1V 4.50.0010.10.15.50.0010.10.13.0V IN = V IL or V IH ,I OL = 12mA 0.360.444.5V IN = V IL or V IH ,I OL = 24mA 0.360.445.5V IN = V IL or V IH ,I OL = 24mA (1) 0.360.44I IN (3) Maximum Input Leakage Current 5.5V I = V CC , GND ±0.1±1.0µA I OLD Minimum Dynamic Output Current (2) 5.5V OLD= 1.65V Max.75mA I OHD 5.5V OHD = 3.85V Min.–75mA I CC (3)Maximum Quiescent Supply Current5.5V IN = V CC or GND2.020.0µA 元器件交易网Notes:4.All outputs loaded; thresholds on input associated with output under test.5.Maximum test duration 2.0ms, one output loaded at a time.4.5V IN = V IL or V IH ,I OL = 24mA 0.360.445.5V IN = V IL or V IH ,I OL = 24mA (4)0.360.44I IN Maximum Input Leakage Current 5.5V I = V CC , GND ±0.1±1.0µA I CCT Maximum I CC /Input 5.5V I = V CC – 2.1V 0.6 1.5mA I OLD Minimum Dynamic Output Current (5) 5.5V OLD = 1.65V Max.75mA I OHD 5.5V OHD = 3.85V Min.–75mA I CCMaximum Quiescent Supply Current5.5V IN = V CC or GND4.040.0µANote:7.Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance CCt PLH Propagation Delay 5.0 1.0 6.59.0 1.010.0ns t PHL Propagation Delay 5.0 1.0 6.59.0 1.010.0nsSymbol Parameter Conditions Typ.UnitsC IN Input Capacitance V CC= OPEN 4.5pFC PD Power Dissipation Capacitance V CC= 5.0V20.0pFFigure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner NOTES:UNLESS OTHERWISE SPECIFIEDA)THIS PACKAGE CONFORMS TO JEDECMS-012,VARIATION AB,ISSUE C,B)ALL DIMENSIONS ARE IN MILLIMETERS.C)DIMENSIONS DO NOT INCLUDE MOLDFLASH OR BURRS.D)LANDPATTERN STANDARD:SOIC127P600X145-14ME)DRAWING CONFORMS TO ASME Y14.5M-1994F)DRAWING FILE NAME:M14AREV138°0°SEATING PLANEDETAIL ASCALE:20:1GAGE PLANE 0.25X 45°0.10C CB C ASEE DETAIL A(0.33)1.75MAX1.501.250.250.100.250.19(1.04)0.900.500.36R0.10R0.100.500.25Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannerFigure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.C.DIMENSIONS ARE EXCLUSIVE OF BURRS,MOLD FLASH,AND TIE BAR EXTRUSIONSF.DRAWING FILE NAME:MTC14REV6R0.09min12.00°TOP&BOTTOM1.00D.DIMENSIONING AND TOLERANCES PER ANSI Y14.5M,1982R0.09minNDPATTERN STANDARD:SOP65P640X110-14M A.CONFORMS TO JEDEC REGISTRATION MO-153,VARIATION AB,REF NOTE 6B.DIMENSIONS ARE IN MILLIMETERSFigure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.NOTES:UNLESS OTHERWISE SPECIFIEDA)THIS PACKAGE CONFORMS TO JEDEC MS-001VARIATION BAB)ALL DIMENSIONS ARE IN MILLIMETERS.C)DIMENSIONS ARE EXCLUSIVE OF BURRS,MOLD FLASH,AND TIE BAR EXTRUSIONS.D)DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994E)DRAWING FILE NAME:MKT-N14AREV78.127.620.350.203.563.305.33MAX 0.38MIN1.771.140.580.352.543.813.178.82subsidiaries,and is not intended to be an exhaustive list of all such trademarks.ACEx ®Build it Now ™CorePLUS ™CROSSVOLT ™CTL™Current Transfer Logic™EcoSPARK ®EZSWITCH™*™®Fairchild®Fairchild Semiconductor ®FACT Quiet Series™FACT ®FAST ®FastvCore ™FlashWriter ®*FPS ™FRFET ®Global Power Resource SM Green FPS ™Green FPS ™e-Series ™GTO ™i-Lo ™IntelliMAX ™ISOPLANAR ™MegaBuck™MICROCOUPLER ™MicroFET ™MicroPak ™MillerDrive™Motion-SPM™OPTOLOGIC ®OPTOPLANAR ®®PDP-SPM™Power220®Power247®POWEREDGE ®Power-SPM ™PowerTrench ®Programmable Active Droop ™QFET ®QS ™QT Optoelectronics ™Quiet Series ™RapidConfigure ™SMART START ™SPM ®STEALTH™SuperFET ™SuperSOT ™-3SuperSOT ™-6SuperSOT ™-8SyncFET™®The Power Franchise ®TinyBoost ™TinyBuck ™TinyLogic ®TINYOPTO ™TinyPower ™TinyPWM ™TinyWire ™µSerDes ™UHC ®Ultra FRFET ™UniFET ™VCX ™*EZSWITCH™and FlashWriter ®are trademarks of System General Corporation,used under license by Fairchild Semiconductor.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY,FUNCTION,OR DESIGN.FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS,NOR THE RIGHTS OF OTHERS.THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,SPECIFICALLY THE WARRANTY THEREIN,WHICH COVERS THESE PRODUCTS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body or (b)support or sustain life,and (c)whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury of the user.2.A critical component in any component of a life support,device,or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status DefinitionAdvance InformationForm First Productionative or In DesignThis datasheet contains the design specifications for productdevelopment.Specifications may change in any manner without notice.PreliminaryThis datasheet contains preliminary data;supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.74AC32, 74ACT32 — Quad 2-Input OR Gate。

Errata Revision: *CMay 02, 2007RAM9 QDR-I/DDR-I/QDR-II/DDR- II ErrataCY7C129*DV18/CY7C130*DV25CY7C130*BV18/CY7C130*BV25/CY7C132*BV25CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/CY7C151*V18 /CY7C152*V18This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality.Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.Devices AffectedTable 1. List of Affected devicesProduct StatusAll of the above densities and revisions are available in sample as well as production quantities.QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata SummaryThe following table defines the issues and the fix status for the different devices which are affected.Density & Revision Part Numbers Architecture 9Mb - Ram9(90 nm)CY7C130*DV25QDRI/DDRI 9Mb - Ram9(90 nm)CY7C129*DV18QDRII 18Mb - Ram9(90nm)CY7C130*BV18CY7C130*BV25CY7C132*BV25QDRI/DDRI18Mb - Ram9(90nm)CY7C131*BV18CY7C132*BV18CY7C139*BV18CY7C191*BV18QDRII/DDRII36Mb - Ram9(90nm)CY7C141*AV18CY7C142*AV18QDRII/DDRII 72Mb -Ram9(90nm)CY7C151*V18CY7C152*V18QDRII/DDRIIItemIssueDeviceFix Status1.DOFF pin is used for enabling/dis-abling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K . The value of the external pull-up resistor should be 500 or less in order to ensure DLL is enabled.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-II/DDR-II DevicesThe fix involved removing the in-ternal pull-down resistor on the DOFF pin. The fix has been im-plemented on the new revision and is now available.ΩΩTable 2.Issue Definition and fix status for different devices1. DOFF Pin Issue•ISSUE DEFINITIONThis issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K ) as an external pullup resistor to enable the DLL. If a 10K or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL.•PARAMETERS AFFECTEDThe functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. •TRIGGER CONDITION(S)Having a 10K or higher external pullup resistor for disabling the DOFF pin.•SCOPE OF IMPACTThis issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled.•EXPLANATION OF ISSUEFigure 1 shows the DOFF pin circuit with an internal 5K internal resistor. The fix planned is to disable the internal 5K leaker.•WORKAROUND2.O/P Buffer enters a locked up unde-fined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II Devices The fix has been implemented onthe new revision and is now avail-able.3.The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II DevicesThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuit-ry by the JTAG signal. The fix has been implemented on the new re-vision and is now available.Figure 1.DOFF pin with the 5K internal resistorItemIssueDeviceFix StatusΩΩΩΩΩΩThe workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is <500). When DOFF pins from multiple QDR devices are connected through the same pull-up resistors on the board, it is recommended that this DOFF pin be directly connected to Vdd due to the lower effective resistance since the "leakers" are in parallel.Figure 2 shows the proposed workaround and the fix planned.•FIXSTATUSFix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. The following table lists the devices affected, current revision and the new revision after the fix.Table 3.List of Affected Devices and the new revison2.Output Buffer IssueFigure 2.Proposed workaround with the 500 external pullupCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ΩΩ•ISSUE DEFINITIONThis issue involves the output buffer entering an unidentified state when the input signals (only Control signals or Clocks) are floating during reset or initialization of the memory controller after power up. •PARAMETERS AFFECTEDNo timing parameters are affected. The device may drive the outputs even though the read operation is not enabled. A dummy read is performed to clear this condition.•TRIGGER CONDITION(S)Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#) are floating during reset or initialization of the memory controller after power up.•SCOPE OF IMPACTThis issue will jeopardize any number of writes or reads which take place after the controls or clock are left floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.•EXPLANATION OF ISSUEFigure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens. Array•WORKAROUNDThis is viable only if the customer has the trigger conditions met during reset or initialization of the memory controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The “dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implemen-tation.In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be performed on every SRAM on the board. Below is an example sequence of events that can be performed before valid access can be performed on the SRAM.1) Initialize the Memory Controller2) Assert RPS# Low for each of the memory devicesNote:For all devices with x9 bus configuration, the following sequence needs to be performed:1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummyread.2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummyread.If the customer has the trigger conditions met during normal access to the memory then there is no workaround at this point.•FIX STATUSThe fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix.3. JTAG Mode Issue•ISSUE DEFINITIONIf the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry (ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid K clock cycles to drive the outputs from high impedance to low impedance levels.•PARAMETERS AFFECTEDThis issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality of the device will not be affected.•TRIGGER CONDITION(S)EXTEST command executed immediately after power-up without providing any K clock cycles.•SCOPE OF IMPACTThis issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality of the device is not affected. •EXPLANATION OF ISSUEImpedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance levels.•WORKAROUNDElimination of the issue: After power-up, before any valid operations are performed on the device, insert a minimum of 1000 valid clocks on K input.•FIX STATUSThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix..Table 4.List of Affected devices and the new revisionCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C130*DV25CY7C130*EV25CY7C130*BV18CY7C130*CV18CY7C130*BV25CY7C130*CV25CY7C132*BV25CY7C132*CV25CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ReferencesAll 90nm QDRI/DDRI/QDRII/DDRII datasheets:-Table 5.List of Datasheet spec# for the Affected devicesSpec#Part#DensityArchitecture38-05628CY7C1304DV259-MBIT QDR(TM) SRAM 4-WORD BURST 38-05632CY7C1308DV259-MBIT DDR-I SRAM 4-WORD BURST 001-00350CY7C1292DV18/1294DV189-MBIT QDR- II(TM) SRAM 2-WORD BURST 38-05621CY7C1316BV18/1916BV18/1318BV18/1320BV1818-MBIT DDR-II SRAM 2-WORD BURST 38-05622CY7C1317BV18/1917BV18/1319BV18/1321BV1818-MBIT DDR-II SRAM 4-WORD BURST 38-05623CY7C1392BV18/1393BV18/1394BV1818-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05631CY7C1323BV2518-MBIT DDR-I SRAM 4-WORD BURST 38-05630CY7C1305BV25/1307BV2518-MBIT QDR(TM) SRAM 4-WORD BURST 38-05627CY7C1303BV25/1306BV2518-MBIT QDR(TM) SRAM 2-WORD BURST 38-05629CY7C1305BV18/1307BV1818-MBIT QDR(TM) SRAM 4-WORD BURST 38-05626CY7C1303BV18/1306BV1818-MBIT QDR(TM) SRAM 2-WORD BURST 38-05619CY7C1310BV18/1910BV18/1312BV18/1314BV1818-MBIT QDR - II (TM) SRAM 2-WORD BURST 38-05620CY7C1311BV18/1911BV18/1313BV18/1315BV1818-MBIT QDR - II SRAM 4-WORD BURST 38-05615CY7C1410AV18/1425AV18/1412AV18/1414AV1836-MBIT QDR-II(TM) SRAM 2-WORD BURST 38-05614CY7C1411AV18/1426AV18/1413AV18/1415AV1836-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05616CY7C1416AV18/1427AV18/1418AV18/1420AV1836-MBIT DDR-II SRAM 2-WORD BURST 38-05618CY7C1417AV18/1428AV18/1419AV18/1421AV1836-MBIT DDR-II SRAM 4-WORD BURST 38-05617CY7C1422AV18/1429AV18/1423AV18/1424AV1836-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05489CY7C1510V18/1525V18/1512V18/1514V1872-MBIT QDR-II SRAM 2-WORD BURST 38-05363CY7C1511V18/1526V18/1513V18/1515V1872-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05563CY7C1516V18/1527V18/1518V18/1520V1872-MBIT DDR-II SRAM 2-WORD BURST 38-05565CY7C1517V18/1528V18/1519V18/1521V1872-MBIT DDR-II SRAM 4-WORD BURST 38-05564CY7C1522V18/1529V18/1523V18/1524V1872-MBITDDR-II SIO SRAM 2-WORD BURSTDocument History PageDocument Title: RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata Document #: 001-06217 Rev. *CREV.ECN NO.IssueDateOrig. ofChange Description of Change**419849See ECN REF New errata for Ram9 QDR2/DDR2 SRAMs.*A493936See ECN QKS Added Output buffer and JTAG mode issues, Item#2 and #3Added 9Mb QDR-II Burst of 2 and QDR-1/DDR-I part numbers.*B733176See ECN NJY Added missing part numbers in the title for Spec#’s 38-05615,38-05614,38-05363,38-05563 on Table 5 on page 7.*C1030020 See ECN TBE Updated the fix status of the three issues, and modified the description forthe Output Buffer workaround for x9 devices on page 5.。