nLint_ppt

• Step4:add your select file
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Run nLint
• Run nLint
• Check your coding style
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Use .f file run nLint
• Prepare data
• 要檢查的RTL code
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Use .f file run nLint
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nLint rule(3)
• Coding Style – Line Too Long – TAB Used in Indentation – More than One Statement per Line – Unconventional Port Declaration Order • VITAL Compliant
• reference
- /uer/cad/spring_soft/verdi/2006.04v1/nLint/doc/pdf/rule.pdf
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Save your rule file
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• step1 • step2
• step3
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• step1
• step2 • Step3:Selec t your file
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nLint rule(2)
• Design Style – Two-process Style Not Used for FSM – Clock Driven by Sequential Logic – Clock Signal Used on Both Edges – No Set or Reset Signal – No Glue Logic Allowed in Top Module Language Construct – Bit Width Mismatch in Assignment – Multi-bit Expression when One Bit Expression is Expected – Bit Range Specified for Parameter – Bit Width Mismatch Between Module Port and Instance Port HDL Translation – Verilog/VHDL Reserved Words – Include Compiler Directive Used Naming Convention – Port Name Too Long – Clock Name Prefix or Suffix – Active Low Signal Name Prefix or Suffix – Port Name Does Not Follow the Connected Signal
• 選擇所需rules
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nLint rule(1)
• Simulation – Combinational Loop – Infinite Loop – Signal in Sensitivity List Changed in the Block – Loss of Significant Bit Synthesis – Logic Expression Used in Sensitivity – Delay in Non-blocking Assignment – Blocking/Non-blocking Assignment in Edge-triggered Block – Inferred Latch ERC – Floating Net – Partial Input Floating – Output Floating – Input Floating DFT – Gated Clock – Buffered Clock – Reset Driven by Combinational Logic
nLint 操作教學
.tw 1
在終機下
• Step1:#source /usr/cad/spring_soft/CIC/debussy.cshrc
• Step2:#nLint -gui
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Select rule(1)
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Select rule(2)
– For VHDL only
• Clock – Generated Reset – Generated Clock – Tri-state Buffer in a Clock Path • Block Interconnect – Conflict of Hierarchy Interconnection – Block Assembly Error in the Same Hierarchy Level
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Source debussy.cshrc
• Run nLint by .f file
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Use .f file run nLint
• Link check
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